Design and Implementation of Stream Cipher Based on LFSR...
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Arab Academy for Science and Technology and Maritime Transport
College of Engineering and Technology
Electronics & Communications Engineering Department
Design and Implementation of Stream Cipher
Based on LFSR and FCSR
A thesis submitted in partial fulfillment of the requirements for the
degree of
Master of Science
in
Electronics and Communications Engineering
By
Eng. Alaa Mohammed Alshobaki
Supervised by
Dr. Nabil H. Shaker
Comsec Consultant
Prof. Dr. Khaled A. Shehata
Assistant Dean for Graduate Studies and
Scientific Research
Alexandria
2006
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بسن هللا الشحوي الشحن
﴾ىىوسسىله و الوؤه عولكن هللا يل أعولىا فسشوق﴿
صذق هللا العظن
األيح, اىتتحسزج
٥٠١
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مو خسذ , ىنو قية يثض تسثل, ىنو شثس ػيى أزضل اىقدسح, ــطيفلســـــــ ىل يــا
قدا , ؼادك أ ظو ىل يدا تثي... فداءا ىلءىنو أب أ يقد أتا, يصف أخيل
.ػيى طسيق اىسسيح
هــــــــــــــــــــــــــــــــــــــــــــــــــذاءا
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DECLARATION
We certify thai \\'e have read the present wcrk dlld hat in our oplni()11 It
is fully adeqlla ll ' in scq)~ and quality as a di~;se,-t;1tio'i t~lwarJs the partial
fulfillmenL of the Masler degree requirement:-; III FLc(t({'( ,.Jl .f~J
from the Arah Academy for Science and Techl1l)llJf~Y and tvlariti11le
Transport,
5 lIpervisors:
Name J< hc~Ltd A {;' S ttehc{1?:t Positiol1 Its;; ( 5> tui\t ~al1- G!L'r 'f £/Y/ A f} c-- '/ '-'I
fV2:f, K-h...W 5~~o..-t~ Signature
Name rJ~ bt' L 1141nc:AJ St14/C2( Position L) C!J D
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Examiners:
Nt1Il1e . prof. 11c.tnj filC rj /t( as 4 ;
Position f a /;/ G Gc..{Vc.3/)C 5 g C6 O J/Vi, Tkpf
(tin S)~ltn ~ U (ll' VE\(~ 1+1 -~---
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Name , Prof- . Yahr'o. fJ,/ , I AbCiU j(re.sZs /ttq Position . fr<Jf. MILl C {t:'ru I E jjf+
Signature '-~------
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I
Acknowledgements
My thanks are wholly devoted to ALLAH for His blessings and for helping me all the
way to conclude this work successfully. I would like to express my endless appreciation
to my family for their constant love, support, patience and understanding. Special
appreciation and thanks go to my dearly loved wife, for her patience and understanding
throughout the course of this endeavor. Moreover, I feel thankful to my lovely son
Mohammed, 2-year-old, his smile has truly helped me through some of the difficult times
during last years.
At the outset, I would like to express my deepest gratitude and sincere appreciation to
my supervisors Dr. Nabil Hamdy Shaker and Prof. Dr. Khaled Ali Shehata for their
advice during my master research. I owe also special thanks to all of my professors and
teachers. Finally, a special acknowledgment to Mentor Graphics who supported AAST
with their tools through the HEP program. I used their FPGA Adv. Pro throughout this
thesis.
Alaa Mohammed Alshobaki
AAST, 2006
ACKNOWLEDGEMENTS
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II
Abstract
In the field of data security, there are two standard approaches for cipher design; block
cipher and stream cipher. Block cipher takes n-bit block as input plaintext and produces
an n-bit ciphertext block, while stream cipher operates on individual bits or characters by
using key stream sequence to be mixed with plaintext sequence to produce ciphertext
sequence. Stream ciphers are cryptographic primitives used to ensure privacy in the
majority of future computer and digital communication systems. Many electronic
components are used in stream cipher design. In this thesis we focus on two main
components; linear feedback shift registers (LFSRs) and a new type of random number
generator called the feedback with carry shift register (FCSR).
For performance as well as for physical security reasons, it is often advantageous to
realize cryptographic algorithms in hardware. In order to overcome the well-known
drawback of reduced flexibility that is associated with traditional ASIC solutions, this
thesis proposes architecture which is optimized for modern field programmable gate
arrays (FPGAs).
This thesis handles novel design and FPGA implementation of a stream cipher algorithm
based on LFSR and FCSR, which generates a key stream sequences under the control of
secret information (key) which is known only to the plaintext sender and receiver. The
proposed stream cipher is designed, analyzed, specified its cryptographic properties and
evaluated to some known attacks and randomness tests.
As one of FCSR applications, we demonstrates how FCSR Galois architecture can be
used as a function with one input-output variable. The advantages and disadvantages of
this application, in addition to discussions on the effects of FCSR function on some type
of attacks are presented. Also, we elucidate comparisons between FCSR and LFSR with
respect to architecture and generated sequences.
ABSTRACT
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Abstract
III
The designed architecture of stream cipher algorithm have been simulated, verified,
implemented and tested using the FPGA advantage pro tools from Mentor Graphics. The
thesis provides the absolute area and timing analysis for the architecture on Altera
FLEX10K70 series FPGA.
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IV
Acknowledgements I
Abstract II
Chapter 1 Introduction 1
1.1 Thesis Motivation ----------------------------------------------------------------------------- 2
1.2 Thesis Organization --------------------------------------------------------------------------- 3
Chapter 2 Stream Cipher Systems 6
2.1 Cryptology ------------------------------------------------------------------------------------- 7
2.2 Stream Cipher Techniques ----------------------------------------------------------------- 10
2.2.1 Additive Synchronous Stream Ciphers --------------------------------------------- 11
2.2.2 Additive Self-Synchronous Stream Ciphers --------------------------------------- 11
2.3 Linear Feedback Shift Register Theory -------------------------------------------------- 12
2.3.1 Maximal Length Sequences ---------------------------------------------------------- 13
2.3.2 Feedback Tap Specifications --------------------------------------------------------- 13
2.3.3 Randomness of m-sequences --------------------------------------------------------- 14
2.3.4 Linear Complexity --------------------------------------------------------------------- 15
2.4 Boolean Function ---------------------------------------------------------------------------- 15
2.4.1 Combination with Memory ----------------------------------------------------------- 20
Contents
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Contents
V
2.4.2 Summation Generator ----------------------------------------------------------------- 22
2.5 Security and Features of Stream Cipher ------------------------------------------------- 23
2.6 Cryptanalysis --------------------------------------------------------------------------------- 25
2.6.1 Methods of Attacks -------------------------------------------------------------------- 26
2.6.2 Survey of Existing Attacks ----------------------------------------------------------- 27
2.6.2.1 Generic Attacks ......................................................................................... 27
2.6.2.2 Specific Attacks ........................................................................................ 35
Chapter 3 Feedback with Carry Shift Register 47
3.1 Mathematical Background ---------------------------------------------------------------- 48
3.1.1 Basics of 2-adic Numbers ------------------------------------------------------------ 48
3.1.2 Primes, Primitive Roots -------------------------------------------------------------- 52
3.2 Register Description ------------------------------------------------------------------------ 53
3.3 Implementation ------------------------------------------------------------------------------ 54
3.3.1 FCSR Fibonacci Architecture -------------------------------------------------------- 54
3.3.2 FCSR Galois Architecture ------------------------------------------------------------ 55
3.4 Analysis and Characteristics of FCSR -------------------------------------------------- 56
3.4.1 Memory Requirements ---------------------------------------------------------------- 58
3.4.2 Initial Loading ------------------------------------------------------------------------- 59
3.4.3 Degenerate Initial Loading----------------------------------------------------------- 59
3.5 Synthesis of FCSR ------------------------------------------------------------------------- 60
3.5.1 2-adic Span and Complexity --------------------------------------------------------- 61
3.5.2 Rational Approximation Algorithm ------------------------------------------------ 63
3.6 -sequences ---------------------------------------------------------------------------------- 65
3.6.1 Properties of -sequences ------------------------------------------------------------ 68
3.6.2 Linear Complexity of 2-adic -sequences ----------------------------------------- 69
3.7 FCSR Function ------------------------------------------------------------------------------ 76
3.7.1 Concatenation of LFSR and FCSR -------------------------------------------------- 77
3.7.1.1 Period ........................................................................................................ 77
3.7.1.2 Algebraic Degree ...................................................................................... 78
3.7.1.3 Linear Complexity .................................................................................... 80
3.7.1.4 2-adic Complexity ..................................................................................... 81
3.7.2 FCSR Function and Attacks ---------------------------------------------------------- 81
3.8 FCSR Verses LFSR ------------------------------------------------------------------------- 83
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Contents
VI
Chapter 4 Concept of FPGA 88
4.1 FPGA Architecture -------------------------------------------------------------------------- 89
4.2 FPGA Technology -------------------------------------------------------------------------- 90
4.2.1 SRAM Based FPGA ------------------------------------------------------------------- 90
4.2.2 Antifuse Based FPGA ----------------------------------------------------------------- 91
4.2.3 EPROM, EEPROM, and FLASH Based FPGA ----------------------------------- 92
4.3 Commercial FPGAs ------------------------------------------------------------------------- 93
4.4 EDA Tools ----------------------------------------------------------------------------------- 94
4.5 HDL-implementation Procedures --------------------------------------------------------- 95
4.5.1 Design Planning ------------------------------------------------------------------------ 95
4.5.2 Design Flow ---------------------------------------------------------------------------- 95
4.5.2.1 RTL Simulation ........................................................................................ 96
4.5.2.2 Synthesis Step ........................................................................................... 98
4.5.2.3 Functional Gate-Level Verification .......................................................... 99
4.5.2.4 Place and Route....................................................................................... 100
4.5.2.5 Timing Simulation .................................................................................. 101
4.5.2.6 Static Timing Analysis ............................................................................ 101
Chapter 5 Design and Implementation of The Proposed Stream Cipher 103
5.1 Design Criteria of the Proposed Stream Cipher --------------------------------------- 104
5.2 Design Description ------------------------------------------------------------------------- 104
5.2.1 Design Parameters -------------------------------------------------------------------- 105
5.2.2 Period ----------------------------------------------------------------------------------- 106
5.2.3 Key-Diversity -------------------------------------------------------------------------- 107
5.2.4 Correlation Immunity and Probability --------------------------------------------- 108
5.2.5 Algebraic Degree --------------------------------------------------------------------- 110
5.2.6 Linear Complexity -------------------------------------------------------------------- 110
5.2.7 2-adic Complexity -------------------------------------------------------------------- 111
5.3 Security Measurements -------------------------------------------------------------------- 113
5.3.1 Statistical Tests Results -------------------------------------------------------------- 113
5.3.2 Security Arguments ------------------------------------------------------------------- 114
5.4 Implementation of the Proposed Stream Cipher --------------------------------------- 116
5.4.1 Architecture of the Proposed Design Module ------------------------------------ 117
5.4.2 VHDL Code for the Design Modules ---------------------------------------------- 125
5.4.3 Function Simulation for the Design Modules and Sub- ------------------------- 127
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Contents
VII
5.4.4 Timing Simulation for the Design Module ---------------------------------------- 130
5.4.5 Synthesis of the Design -------------------------------------------------------------- 131
5.5 Testing of the Proposed Stream Cipher ------------------------------------------------- 131
5.5.1 Visual Basic Program Interface ----------------------------------------------------- 133
5.5.2 Receiving Processing ----------------------------------------------------------------- 134
Chapter 6 Conclusion 138
Appendix A 142
References 149
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VIII
Chapter 2
Figure 2.1 Two parties in a symmetric cipher conversation with an adversary listening in
on the unsecured channel .................................................................................................... 8
Figure 2.2 Two parties engaged in a public-key cipher conversation. The adversary can
see the ciphertext and the puplic-key .................................................................................. 9
Figure 2.3 Additive synchronous stream ciphers ............................................................. 11
Figure 2.4 Additive self-synchronous stream ciphers...................................................... 11
Figure 2.5 Fibonacci linear feedback shift register .......................................................... 12
Figure 2.6 Galois linear feedback shift register ............................................................... 12
Figure 2.7 Nonlinear combining function with memory ................................................. 20
Figure 2.8 One-bit memoryless combiner of maximum correlation-immunity N – 1
allowing maximum nonlinear order in f............................................................................ 21
Figure 2.9 Summation generator of two LFSRs (3-bit real adder) .................................. 22
Figure 2.10 Algorithm computing the statistic Xu for Maurer's universal statistical test 32
Figure 2.11 The structure of a dynamic LCT search tree ................................................ 38
Figure 2.12 Principle of Siegenthaler's correlation attack ............................................... 42
Figure 2.13 Model used by Meier and Staffelbach .......................................................... 43
Chapter 3
Figure 3.1 Fibonacci Feedback With Carry Shift Register .............................................. 53
Figure 3.2 Shift register with ripple adder ....................................................................... 54
Figure 3.3 Galois FCSR architecture ............................................................................... 56
Figure 3.4 Rational Approximation Algorithm ............................................................... 65
List of Figures
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List of Figures
IX
Figure 3.5 Fibonacci and Galois FCSR with q = 37 ........................................................ 72
Figure 3.6 2-adic complexity profiles .............................................................................. 75
Figure 3.7 Series of 2-adic number divided by integer q which correspond to FCSR .... 76
Figure 3.8 Concatenation of LFSR and FCSR function .................................................. 77
Figure 3.9 Autocorrelation of LFSR and FCSR sequences ............................................. 85
Chapter 4
Figure 4.1 The basic structure of the FPGA-chip ............................................................ 89
Figure 4.2 SRAM controlled programmable switches .................................................... 91
Figure 4.3 Antifuse structure ........................................................................................... 91
Figure 4.4 Antifuse-FPGA architecture ........................................................................... 92
Figure 4.5 High-level design flow ................................................................................... 96
Figure 4.6 RTL simulation flow ...................................................................................... 97
Figure 4.7 Sample area report .......................................................................................... 98
Figure 4.8 Dataflow diagram of the place and route ..................................................... 100
Chapter 5
Figure 5.1 The proposed stream cipher algorithm ......................................................... 105
Figure 5.2 Initialization mode ........................................................................................ 116
Figure 5.3 Generation mode .......................................................................................... 117
Figure 5.4 Schematic of proposed stream cipher ........................................................... 118
Figure 5.5 Input–Stream frame ...................................................................................... 118
Figure 5.6 Schematic of proposed algorithm ................................................................. 119
Figure 5.7 The Implemented PRG ................................................................................. 120
Figure 5.8 Schematic of Implemented PRG .................................................................. 121
Figure 5.9 Concatenation of LFSR1 and FCSR1 module ............................................... 123
Figure 5.10 Reprogrammable LFSR1 of Length 19 module .......................................... 123
Figure 5.11 VHDL code of AutoMode module ............................................................. 125
Figure 5.12 VHDL code of LFSR1 module ................................................................... 125
Figure 5.13 VHDL code of PPStorage of LFSR1 module ............................................ 126
Figure 5.14 Function simulation of LFSR1 module ....................................................... 127
Figure 5.15 Function simulation of FCSR1 module....................................................... 128
Figure 5.16 Function simulation of concatenation of LFSR1 and FCSR1 module ........ 128
Figure 5.17 Function simulation of PRG module .......................................................... 128
Figure 5.18 Function simulation of AutoMode module ................................................ 129
Figure 5.19 Function simulation of proposed algorithm ............................................... 129
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List of Figures
X
Figure 5.20 Timing simulation of proposed algorithm .................................................. 130
Figure 5.21 PC and FPGA-board communication method ............................................ 132
Figure 5.22 Span-shot from the user interface visual basic program ............................ 133
Figure 5.23 Timing simulation of proposed stream cipher with RS-232 serial standard
......................................................................................................................................... 135
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XI
Chapter 2
Table 2.1 The truth table of Boolean function f(x1,x2,x3) = x1 x2 + x2 x3 + x3 .................. 16
Table 2.2 Selected percentiles of the 2 (Chi-square) distribution .................................. 29
Table 2.3 Mean and variance of the statistical Xu for random sequences ........................ 32
Chapter 3
Table 3.1 Values of q giving –sequences for lengths 8, LC and period ...................... 67
Table 3.2 The states of FCSR with q = 37 ....................................................................... 73
Table 3.3 2-RA results ................................................................................................. 75
Table 3.4 The number of bad keys which make T = T .................................................. 78
Table 3.5 Simulation examples of the period and linear complexity .............................. 80
Table 3.6 Simulation examples of the period and 2-adic complexity.............................. 81
Table 3.7 Hardware Complexity of LFSR and FCSR ..................................................... 83
Chapter 5
Table 5.1 Parameters of LFSRs and FCSRs .................................................................. 106
Table 5.2 Correlation probability of the summation generator ...................................... 108
Table 5.3 Truth Table & Correlation Probability. Table 5.4 Wf of Z ................ 109
Table 5.5 Simulation examples of the period and linear complexity ............................ 110
Table 5.6 Simulation examples of the period and 2-adic complexity............................ 112
Table 5.7 Statistical Tests Results of FIPS 140-2 Tests for Randomness ..................... 113
List of Tables
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List of Tables
XII
Table 5.8 Statistical Tests Results of Sequence length = 1,000,000 bits ....................... 114
Table 5.9 Statistical tests results of the designed PRNG ............................................... 122
Table 5.10 Report area of the proposed algorithm ........................................................ 131
Table 5.11 Pin assignments of serial port and the corresponding FPGA port …..…… 131
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XIII
2-RA 2-adic Rational Approximation Algorithm
AES Advanced Encryption Algorithm
ANF Algebraic Normal Form
ASIC Application Specific Integrated Circuit
BSC Binary Symmetric Channel
CAD Computer-Aided Design
CI Correlation Immunity
CLB Configurable Logic Block
CPLD Complex Programmable Logic Device
DCE Data Communication Equipment
DES Data Encryption Standard
DFF Data Flip-Flop
DTE Data Terminal Equipment
ECB Electronic Code Block
EDA Electronic Design Automation
EEPROM Electrically Erasable Programmable Read-Only Memory
EIA Electronic Industrial Association
EPROM Erasable Programmable Read-Only Memory
FCSR Feedback with Carry Shift Register
FG Function Generator
List of Acronyms
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List of Acronyms
XIV
FIPS Federal Information Processing Standards
FPGA Field Programmable Gate Array
GSM Global System Mobile
HDL Hardware Descriptive Language
ISUM Improved Summation Generator
IV Initial Vector
LC Linear Complexity
LCM Least Common Multiple
LCT Linear Consistency Test
LFSR Linear Feedback Shift Register
OTP One Time Pad
PC Personal Computer
PKI Public Key Infrastructure
PLD Programmable Logic Device
PRG Pseudo Random Generator
RTL Register Transfer Level
SDF Standard Delay Format
SRAM Static Random Access Memory
TTL Truth Table Form
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus
WHT Walsh Hadamard Transform