Design and Analysis of Pulse-width

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improving the supply-terminal current waveform. In 1997,Zhu and Ioinovici [9] performed a comprehensive andaccurate steady-state analysis of step-up SC converter. In2003, Chang [10, 11] proposed an integrated SC step-up/down converter. Recently, Axelrod et al. [12] suggested ahybrid PWM switched-capacitor/inductor converter, and

Tan et al. [13] proposed a low-electromagnetic interferenceSC by interleaving control. However, Ioinovici SC has the

voltage gain proportional to the number of pumpingcapacitors, so it still needs a larger device area.

In 1991, Ueno proposed much of the new known structures:series-parallel, Fibonacci, and so on. The SC transformer idea

was proposed for the step-up ratio of Fibonacci series torealise an emergency power supply[14], and then a low-rippleor low-input-current SC converters were presented [15, 16].However, these converters were suffering from a very limitedline regulation capability. In 1997, Makowski [17] suggested a

canonical structure of multiplier charge pump with two-phasecascaded voltage doublers. An n-stage Makowski chargepump can obtain the voltage gain limited by the (n+ 1)thFibonacci number. Its steady-state analysis, voltage/power loss

were discussed, and it has been proved just to require the leastnumber of pumping capacitors in the two-phase SC [1820].Following this idea, Starzyket al. [21] proposed a new chargepump scheme of multi-phase voltage doubler (MPVD) byusing multi-phase operation different from two-phase before.Further, the relevant analysis and performance limits werediscussed, and the relationship between voltage gain andphase number was presented by generalised Fibonacci number[22, 23]. An n-stage Starzyk charge pump can boost the

voltage gain up to 2n at most, that is, the number of pumpingcapacitors in Starzyk is required fewer than that in Makowskifor the same voltage gain. Nevertheless, some improved spacesstill exist as follows: (i) Since the battery voltage is decreasing

with time, or it has the impure DC, such a source variationoften occurs. Besides, the loading variation arises fromunexpected failure or adding/removing the load. They alwaysaffect the output current. Here, for keeping output currentstable and constant, we add a constant current source in ourscheme to reinforce output robustness. (ii) Since Starzykscircuit is fixed, the output voltage is a constant value. In fact,the more flexible output is needed for the different desired

outputs. Here, we adopt PWM technique to enhance outputcurrent regulation. Our main purpose is to propose a closed-loop current-mode multi-phase voltage doubler (CMPVD)for step-up conversion and output current regulation.

2 Configuration of CMPVD

2.1 Structure of CMPVD

Fig. 1a shows a closed-loop two-stage CMPVD, and itcontains two major parts: power part and control part. Thepower part, a two-stage CMPVD in the upper half of

Fig. 1a, is proposed based on Starzyk charge pump [21]. TheCMPVD is composed of two voltage doublers and onecurrent source ID in series between source VS and output Vo.

For more details, it includes two pumping capacitors C1, C2,output capacitor Co and eight metal-oxide semi-conductorfield effect transistor (MOSFET) switches S1n, S1p, S2n, . . .,S4p, where each capacitor has the same capacitance C(C1 C2 C) with equivalent series resistance (ESR) rC,and S1n, S1p, S2n, . . ., S4p are operated as static switches with

on-state resistance rT. Here, one current source ID is set for astable and constant output current and realised by one currentreference and two current mirrors. Assume that+Vis an ideal

voltage, and the current reference Im is adjusted by changingRm (if needed more precise, the bandgap reference should beemployed forIm). With the help ofIm and two current mirrors(current ratio: a1, a2), ID can be assigned to a constant value ofa1a2Im. When largera1 orRm is selected, Im can be smaller. AsmallerIm will not result in too large power consumption.

First, the CMPVD operation is discussed. Fig. 1bshows thetheoretical waveforms in one switching cycle TS (TS 1/fS, fS is

the switching frequency). Each TS contains four small phases(phases I, II, III and IV, phase numberp 4), and each phasehas the same phase cycle T (T TS/4). In phase I (t[ [t0,t1]), letS1 (S1p, S1n) be turn-on, and the other S22 S4 be off.So, voltage vC1 across C1 is charged up to VS, as shown inFig. 2a. In phase II (t[ [t1, t2]), let S2, S3 be turn-on, andvC2 across C2 is charged with the series of VS, vC1 as inFig. 2b. In phase III (t[ [t2, t3]), it repeats the phase Ioperation. In phase IV (t[ [t3, t4]), let S2, S4 be on. Underthe series ofVS, vC1 , vC2 as in Fig. 2c, vC0 across Co is charged

viaID within t[ [t3, t3+DT] to supply RL, where D is theduty cycle of T (0 D 1). Thus, output voltage vo andcurrent i

ocan be regulated with the charging time DT. Since

vC1/vC2 is towards the goal value of VS/2VS, vo can be boostedup to four times the voltage of VS at most. Second, the controlpart, where PWM controller is shown in the lower half ofFig. 1a, is functionally composed of low-pass filter (LPF),PWM block and phase generator. In view of signal flow,output io is fed back into LPF for high-frequency noiserejection. Then, the filtered Io is compared with the desiredoutput reference Irefto produce the duty cycle Dvia the PWMblock. The main goal is to keep Io on following Iref. With thedigital programmable chip/frequency divider, a phase generatorcan be realised to generate the multi-phase driver signals ofS12 S4 just like the waveforms in Fig. 1b. For the duty-cycle

control in phase IV, signal S4n in Fig. 1b can be generated vialogic AND between S4n and D.

A remark is given about phase number p. Exactly, thesufficient phase number is p 3 for the maximum voltagegain being four [22]. In our paper, the phase number istaken as p 4, and it seems to be a little redundant in timeexecution. In fact, it does not affect the performance toomuch. Some reasons to keep the redundancy are as follows:(i) The timing control circuit (phase generator) is madeeasier when p 4. As shown in Fig. 1b, we need two sets ofsymmetrical driver signals: S1, S2 and S3, S4 for multi-phase

operation. It is noticeable that these waveforms aresymmetrical. In one switching cycle TS (3608), S1 is leading908 ahead of S2, and S3 is leading 1808 ahead of S4. Such a

270 IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 269281

& The Institution of Engineering and Technology 2010 doi: 10.1049/iet-cds.2009.0111

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symmetrical regularity makes the phase generator realisationmuch easier. (ii) When phase number is p 3 (TS has three

phases), vC1 across C1 is charged once (phase I) per threephases. But, in our paper p 4 (TS has four phases), so vC1across C1 is charged twice (phases I and III) per four phases.

According to the charge distribution, charging twice per fourphases (p 4) is more helpful to the boosting response,

even though the switching cycle of p

4 is 1/4 cycle longerthan that of p 3. Of course, we need a larger output

capacitor Co when p 4, but not very large. When p 3,

Figure 1 Configuration and operation of CMPVD

a Closed-loop configuration of CMPVDb Theoretical waveforms of CMPVD

IET Circuits Devices Syst., 2010, Vol. 4, Iss. 4, pp. 269 281 271

doi: 10.1049/iet-cds.2009.0111 & The Institution of Engineering and Technology 2010

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Co has to stand up alone for 2/3 cycle to supply the load. In ourpaper (p 4), so Co has to supply the load alone for 3/4 cycle.

By comparing the two cases, our output capacitorCo is neededjust 9/8 times the capacitance value ofCo forp 3.

2.2 Formulation of CMPVD

First, in phase I, let S1 be turn-on and other MOSFETs beoff, and the topology is shown in Fig. 2a. So, the dynamicequation for phase I can be described as

vC1 (t)

vC2 (t)vCo (t)

=1RC

0 0

0 0 0

0 01

RLCo

vC1 (t)

vC2 (t)vCo (t)

+0

1

RC

0 0

0 0

IDVS

(1a)

vo(t)

iS(t)

=

0 0 1

1

R

0 0

vC1 (t)

vC2 (t)

vCo (t)

+

0 0

01

R

ID

VS

(1b)

where R 2rT+ rC is the parasitic resistance of CMPVD,and vo(t), iS(t) are the output voltage and supply-terminalcurrent, respectively. In phase II, according to the topologyin Fig. 2b, the relevant dynamic equation is derived as

vC1 (t)

vC2 (t)

vCo (t)

=

1

2RC

1

2RC 01

2RC

12RC

0

0 01

RLCo

vC1 (t)

vC2 (t)

vCo (t)

+0

12RC

01

2RC0 0

ID

VS

(2a)

vo(t)

iS(t)

=

0 0 11

2R

12R

0

vC1 (t)vC2 (t)

vCo (t)

+ 0 0

01

2R

ID

VS

(2b)

Next, phase III repeats the phase I operation, so the equationfor phase III is identical to (1). In phase IV, letS2, S4 be on,and the topology is in Fig. 2c. Based on the topology, thedynamic equation for phase IV is derived as

vC1 (t)

vC2 (t)

vCo (t)

=

0 0 00 0 0

0 01

RLCo

vC1 (t)

vC2 (t)

vCo (t)

+

DC

0

DC

0

D

Co0

ID

VS

(3a)

vo(t)

iS(t)

=

0 0 1

0 0 0

vC1 (t)vC2 (t)

vCo (t)

+ 0 0D 0

ID

VS

(3b)

In this paper, we assume that the CMPVD is operatingonly in fast-switching-limit (FSL) mode [23]. So, by usingstate-space averaging (SSA) technique in FSL mode,that is, [(1)+ (2)+ (1)+ (3)]/4, the state-space averageddescription of two-stage CMPVD can be derived as

x(t) = Aavx(t)+Bavu(t) (4a)y(t) = Cavx(t)+Davu(t) (4b)

Figure 2 Topologies of CMPVD

a Phase I, IIIb Phase IIc Phase IV



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where

x(t) = vC1 (t) vC2 (t) vCo (t) T

(5a)

u(t) = ID VS T

(5b)

y(t) = vo(t) iS(t)

T (5c)

Aav=

58RC

1

8RC0

1

8RC

18RC

0

0 01

RLCo

(5d)

Bav=

D4C

3

8RC

D

4C

1

8RCD

4Co0

(5e)

Cav=0 0 138R

18R

0

(5f)

Dav=0 0

D

4

5

8R

(5g)

3 Theoretical analysis of CMPVD

3.1 Steady-state and dynamic analysis

First, the steady-state analysis is discussed. By substitutingx(t) 0 of (4), the steady-state output voltage Vo, outputcurrent Io and supply-terminal currentIS can be derived as

Vo = (Cav,1A1av Bav+Dav,1)u=DRL

4ID (6a)

Io =VoRL =

D

4 ID (6b)

IS = (Cav,2A1av Bav+Dav,2)u= DID (6c)

where Cav,1/Cav,2 (Dav,1/Dav,2) are the matrices with the first/second row of Cav (Dav). From (6b), it is observed that Iois not a function of source VS and load RL. When VS isdecreasing orRL is varying, Io is not affected immediately. Inother words, such a source/loading variation makes noimmediate response on Io. This is an excellence of CMPVDfor the output robustness. Next, the dynamic analysis isdiscussed. We set all variables with two parts as vC1 (t) =VC1 + vC1 (t), vC2 (t) = VC2 + vC2 (t), vCo (t) = VCo + vCo (t),vo(t) = Vo+ vo(t), D(t) = D+ d(t), where VC1 , VC2 , VCo ,Vo and D are static operating signals, and vC1 , vC2 ,

vCo , vo and d are dynamic small signals. By the small-signaltechnique around one operating point, the small-signalequation of CMPVD can be derived as (7), and then thetransfer function is presented as (8).

vC1 (t)

vC2 (t)

vCo (t)

=

5

8RC

1

8RC 01

8RC

18RC

0

0 01

RLCo

vC1 (t)vC2 (t)vCo (t)

+

ID4C

ID4C

ID4Co

d(t) (7a)

vo(t) = vCo (t) (7b)

G(s) = vo(s)d(s)

= ID4Co

1

s+ 1/RLCo(8)

3.2 Power conversion efficiency

Based on (6), the steady-state input/output power can becomputed as

Pi = VSIS = VSDID (9a)

Po = VoIo = VoD

4ID (9b)

Based on (9), the power conversion efficiency is derived as

h= PoPi=

VoD

4

ID

VSDID= 1

4

VoVS

= M

4(10a)

M=

Vo

VS =RLID

4VSD (10b)

where M is the DCDC step-up voltage conversion ratio,and it can be regulated by duty cycle D. Based on (10a), his rising with increasing M, and h is close to 100% whenM approaches to 4. In this two-stage CMPVD, Vo isboosted up to four times the voltage of VS at most. Fornominal conditions, the maximum attainable output Vo is4VS-voltage drops in the charging and discharging circuits.But, when M is operating much smaller than 4 (Vo is muchlower than 4VS), h will be quite bad. For better efficiency,it is good to choose Vo to be close to 4VS as much as

possible. If not realised, we will change source VS ormanipulate phase number p (from 4 to 3, 2 or 1) to fit pVSfor the outputVo as close as possible [18, 22].



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Here, an additional remark is given about comparison toZhus circuit [9]. Basically, Zhus circuit belongs to a

voltage-mode SC converter with the maximum voltage gainproportional to stage n, that is, Vo,max (n+ 1)VS. Thus,the efficiency can be approximated as h Vo/[(n+ 1)VS].Exactly, some of our results are similar to the conclusions

presented by Zhu and Ioinovici [9] in 1997. However, ourcircuit belongs to a current-mode SC converter, so thecurrent-mode operation here is different from that of Zhu.Besides, because our power stage is based on Starzykstructure [21], the maximum voltage gain is 2 to the powerof stage n, that is, Vo,max 2

nVS. In our paper, since thetwo-stage scheme is considered (n 2), the voltage gain

will be 22 4 at most. So, the efficiency is derived ash Vo/[4VS] M/4 as (10a). To conclude, we have twopoints different from contents of Zhu: (i) current-modeanalysis and design and (ii) MPVD-based power stage.

3.3 Output ripple percentage

According to Fig. 1b, vo is decaying exponentially fromVo,max to Vo,min during the discharging interval of (42D)Tcyclically, and then it can be modelled as

vo(t) = Vo,maxet/t, 0 t (4 D)T, (T= TS/4)(11)

where the maximum/minimum value in the discharging intervalis denoted byVo,max/Vo,min and formulated byVo,max vo(0) andVo,min vo((42D)T) Vo,maxe

2(42 D)T/t, and t RLCois the discharging time constant. So, the ripple variation of vocan be defined as

Dvo = Vo,max Vo, min = Vo, max[1 e(4D)T/t] (12)

Based on (11) and (12), the averaged output voltage can becalculated as

Vo =1

(4 D)T

(4D)T0

vo(t) dt=4

4 D fStDvo (13)

Thus, the output ripple percentage is presented as

rp = DvoVo

100% = 4D4fSt

= 4D4fSRLCo

= 4D4

TSRLCo

(14)

Obviously, rp is worse while the load is heavier, but it can beimproved by increasing fS or Co. When the CMPVD isunloaded (RL 1), rp is almost zero. For a desired ripple rp,based on (14) and D 1 (heavy load), the minimum outputcapacitor can be estimated as

Co Co, min = 34fSRLrp(15)

4 Control design of CMPVD

4.1 Stability and capacitance selection

Based on (5d), the characteristic equation can be derived as(16a), and its three roots are obtained as (16bd).

D(s) = |sIAav| = s+1

RLCo

s2 + 34RC

s+ 116R2C2

= 0 (16a)

p1 = 1

RLCo(16b)

p2 = 3

5

8RC(16c)

p3 = 3+

5

8RC(16d)

For better boosting response, the phase time constantRCinFig. 2amust be smaller than phase cycle T(T TS/4). Basedon (14), the discharging time constant RLCo is asked muchlarger than TS for the lower ripple. By summarising theserelationships, the time inequality can be obtained as

RC, T= TS4, TS , RLCo (17)

According to (15), output capacitor Co is chosen largerfor the lower output ripple. According to (17), pumpingcapacitor C should be chosen smaller for the faster boostingresponse. In other words, (15)/(17) provides for theselection of Co/C. In general, Co is times or above largerthan the value of C. In addition, for the better conversion,RL is much larger than the parasitic rT, rC (RL rT, rC).In fact, RL is about in V-level and rT, rC is about inmV-level. So, RLCo is really much larger than 8RC(RLCo 8RC) because of Co . C and RL rT, rC.Obviously, p1 21/RLCo is the system dominant pole as

shown in (16b). Because p1 is located in the left half ofs-plane, the CMPVD is locally stable. Thus, the CMPVDhas an inherent good local stability. In addition, accordingto (17), the phase cycle T (i.e. switching period of SSA) isreally much shorter than the system time constantRLCo, sothe SSA analysis above can be valid.

An additional remark about capacitors is given here. In thenon-interleaved SC, output capacitor Co generally has tostand up alone for 1/2 cycle of TS to supply the load. Inour CMPVD, Co has to supply the load alone for 3/4cycle. Thus, our Co is needed 1.5 times the value of output

capacitor used in the non-interleaved SC. Really, a largerCo is needed, but we still benefit from reducing the numberof pumping capacitors.



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4.2 PWM control for CMPVD

This PWM controller is shown in the lower half ofFig. 1a.First, output io is sent into LPF for high-frequency noiserejection. In the LPF, there is a parameter of cut-offfrequency wL, which is chosen according to what range the

possible high-frequency noises occur at. Certainly, to avoidaffecting the system response, wL is generally taken biggerthan times the value of dominant pole p1 (wL . |p1|).

Then, the filtered Io is compared with the desired Iref toproduce duty cycle D via the PWM block. The closed-loopgoal is to keep Io on following Iref. Fig. 3 shows the closed-loop control diagram of CMPVD, and D can bedetermined as

D=f(Iref, Io) =4IrefID

+ KP(Iref Io) (18)

where the first term of (18) is based on (6b) for building astatic operating point of duty cycle D 4Iref/ID, that is,this D can drive Io to catch up with Iref. The second termof (18) is a simple proportional compensator of gain KP forthe performance compensation, for example, rise or settlingtime. Next, the design ofKP is discussed. Around the staticD, based on Fig. 3 plus (8), the closed-loop characteristicequation can be derived as

Dclosed(s) = s+1

RLCo+ KP

ID4RLCo

1

1+ s/wL= 0 (19)

When we consider the dynamic response at the frequencylower than wL, (19) can be approximated as

Dclosed(s) = s+1

RLCo1+ KPID

4

= 0 (20)

Then, the closed-loop settling time tS within a settling errorof +5% is obtained as

tS = 3RLCo1+ KPID/4(21)

So, the minimum gain ofKP can be designed for keepingtS

to be shorter than some desired settling time tS as

KP . KP,min =3RLCo tS

tSID/4(22)

4.3 Source lower bound

Based on (6b), Io is not directly affected by VS. However,when VS is decreasing, it is becoming more difficult to keepSD saturated for the current source ID. Of course, VS has alower bound limit. When SD is saturated, the currentrelationship is ID K(VSG2 Vt)

2 (K is the processparameter and Vt is the threshold voltage). The twosaturated conditions of SD are (i) VSG . Vt, (ii) VDG , Vt.In Fig. 1a, SD is connected with other PMOS as a currentmirror. With the reference Im and current mirrors a1, a2,ID is assigned to a1a2Im as a current source. Based onID K(VSG2 Vt)

2 a1a2Im, the source-gate voltage VSG

can be obtained as

Vcon = VSG =a1a2Im

K

+ Vt (23)

where Vcon is defined by the value of VSG for someID a1a2Im. From (23), obviously, Vcon VSG . Vtsatisfies the first saturated condition. Next, based on (4),VC1, VC2 across C1, C2 can be computed as

VC1 = 1 0 0

A1av Bavu= VS RDID (24a)

VC2 = 0 1 0 A1av Bavu= 2VS 3RDID (24b)According to phase IV topology in Fig. 2c, the gate and drainvoltages ofSD can be obtained as

VGate = VSource Vcon = VS + VC1 + VC2 2RDID Vcon= 4VS 6RDID Vcon (25a)

VDrain = Vo (25b)

From (25), the gatedrain voltage VDG is obtained as

VDG = VDrain VGate = Vo (4VS 6RDID Vcon)(26)

With the help ofVDG , Vt (second saturated condition), thesource lower bound can be derived as

VS . VS,min =Vo + Vcon Vt+ 6(2rT + rC)ID

4(27)

where VS,min is the minimum supply voltage for current-mode operation. For some output Vo, it is obvious that VSneeds to be higher than Vo/4. For larger parasitic resistances

(rT, rC), higher VS,min is needed. In other words, theparasitic will narrow down the effective range of supplyvoltage for current-mode operation.Figure 3 Closed-loop control diagram of CMPVD



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4.4 Current source selection

The upper bound of ID is estimated here. Based on (10b),because M 4 (two-stage CMPVD) plus D 1 (heavyload), ID requires satisfying

ID 16VS

RL(28)

It is notable that (28) is a result with no parasitic, but itprovides a simple way to select ID. Clearly, h could bebetter while ID is selected closer to the value of 16VS/RL.

When the parasitic is considered, via substituting (6a) into(27), the precise upper bound of ID can be derived as

ID ID,max =16VS 4(Vcon Vt)RL + 24(2rT + rC)

(29)

Figure 4 Steady-state response

a Output current (Iref 33 mA)b Output voltage ripple (Iref 33 mA)c Output current (Iref 41 mA)d Output voltage ripple (Iref 41 mA)



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Obviously, (29) still fits in with the inequality of (28). Bysubstituting (29) into (10b), the maximum conversion ratioMmax can be suggested as

Mmax =4 (Vcon Vt)/VS

1+ 24(2rT + rC)/RL(30)

Here, ifrT, rC are small enough to be neglected, and furtherVcon2 Vt VS, then Mmax does approach to 4. By

combining (10a) with (30), (9b) with (6), (29), themaximum efficiency/output power are also presented as

hmax =1 (Vcon Vt)/4VS

1+ 24(2rT + rC)/RL(31a)

Po,max =[4VS (Vcon Vt)]2

RL[1+ 24(2rT + rC)/RL]2(31b)

Figure 5 Source and loading variation

a Output robustness to exponential source disturbance (Iref 33 mA)b Output robustness to sinusoidal source disturbance (Iref 33 mA)c Output current while the load failure occurs (Iref 28 mA)d Output current while adding/removing the load (Iref 28 mA)



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5 Example of CMPVD

In this section, a closed-loop two-stage CMPVD is simulatedby OrCAD tool (PSPICE), and the hardware implementationis realised and tested for various desired outputs, source orloading variation. All the results are illustrated to verify the

efficacy of the proposed scheme. First, according to Fig. 1a,the closed-loop CMPVD is designed by PSPICE forsimulation. The basic function is to boost Vo up to fourtimes voltage of VS (3.6 V) at most for supplying thestandard load RL (310 V) via the current source ID at theswitching frequency fS (20 kHz). The main goal is to keepoutput Io on following the desired Iref. Based on (28), ID isselected at 180 mA (Vcon 1.224 V). According to (15),output capacitor Co is designed at 50 mF (ESR 0.01 V) forthe desired ripple rp 0.4%. By (17), pumping capacitor Cis selected at 10 mF (ESR 0.01 V). In the PWM controller,wL is taken by about 1000 Hz for high-frequency noise

rejection, and KP is designed at eight based on (22), wherethe desired settling time tS is temporarily assigned to 35 ms.Here, several simulation cases are discussed as (i) steady-stateoutput, output ripple and power efficiency, (ii) robustness tosource disturbances, (iii) regulation for loading variations and(iv) output ripple and power efficiency for the differentoutput and loading. Finally, the CMPVD hardwareimplementation is tested for the cases of steady-stateresponse, source or loading variation.

1. First, the steady-state response is considered. TheCMPVD is simulated for the two Iref 33, 41 mA,

respectively (assigned arbitrarily), and the results areobtained as shown in Fig. 4. In Figs. 4a and c,the CMPVD is at the stable step-up conversion, and Io arereally following the desired Iref 33, 41 mA. Also, thesettling time is observed at about 30 ms, and it is reallyshorter than the desired tS. From Figs. 4b and d, theripples are obtained as rp 0.276, 0.237%, and they arereally lower than rp. Then, the efficiencies are alsoobtained as h 67.2, 81.4%. These two results can be

verified by theoretical conclusion of (10): the bigger Iref,the higher Vo becomes, and then M and h are rising. Thus,the results show that the CMPVD has a good steady-stateperformance.

2. Second, the robustness to source variation is considered.Here, we have two cases of source variations (exponentialand sinusoidal) to discuss as follows. (a) Case 1: VS isassumed at 3.6 V plus exponential drop from 3.6 to 3.1 V, asshown in the upper half of Fig. 5a. The CMPVD issimulated for the desired Iref 33 mA, and then the outputcurrent is shown in the lower half ofFig. 5a. Obviously, Io isstill firmly following Iref, even though VS has decreased to3.1 V. According to (27), the source lower bound VS,min isestimated at 2.7 V. Since the minimum point of VS (3.1 V)is higher than VS,min (2.7 V), the current-mode operation is

still running. (b) Case 2: VS is assumed at 3.6 V plussinusoidal disturbance with peak peak voltage of 0.4 V,as shown in the upper half of Fig. 5b. The CMPVD

is simulated for Iref 33 mA, and the output currentis obtained as lower half of Fig. 5b. Clearly, Io is stillfollowing Iref in spite of sinusoidal disturbance. So, theresults show that the CMPVD has good robustness tosource variation.

3. Third, the regulation for loading variation is discussed.Here, we have two cases to consider as follows: (a) Case 1:RL is assumed about 310 V normally, and it suddenlychanges from 310 V to 100 V at 40 ms due to short-circuitfailure. After a short period, the load recovers from the

Figure 6 Ripple and efficiency

a Ripple for different output and loadingb Efficiency for different output and loading

Figure 7 Hardware implementation of closed-loop CMPVD



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Figure 8 Experimental results of CMPVD hardware

a Steady-state output and duty cycle (Iref 5 mA)b Output voltage when VS 3.0 V (Iref 4.5 mA)c Output voltage when VS 2.7 V (Iref 4.5 mA)d Output voltage while the same load is added (Iref 5 mA)

e Output voltage while the added load is removed (Iref

5 mA)



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failure, and RL changes from 100 V back to 310 V at 80 ms.Fig. 5c shows the transient output current at the moment ofloading variations, that is, RL 310 V 100 V 310 V.Obviously, Io can still hold on Iref 28 mA. (b) Case 2: Thesame load is added in parallel at 40 ms, and then the addedload is removed at 80 ms, that is,

RL 310 V 155 V 310 V. Fig. 5d shows the outputcurrent waveform, and we found that Io is still followingIref 28 mA in spite of loading variation. Of course, thecurve shape of Io becomes thicker during the heavier load(4080 ms), that is, the output ripple becomes bigger atthis moment. Thus, the closed-loop CMPVD has a prettygood regulation capability.

4. The ripple and efficiency are discussed for differentoutput and loading. With the consideration of different RL(2401260 V) and Iref (10 40 mA), the ripples andefficiencies can be obtained by simulation as shown in

Figs. 6a and b. In Fig. 6a, the output ripples are decreasingwith increasing RL, and all the values are smaller than0.35%. The results are sure to agree with (14) derivedtheoretically, and all the ripples are really lower than thedesired rp. In Fig. 6b, the efficiencies for various Iref arerising with increasing RL. In view of (10), when RL isincreasing, M and h are rising theoretically. So, the resultsin Fig. 6b correspond to (10).

Finally, the hardware implementation of CMPVD isrealised as shown in Fig. 7. In the figure, there are twocircuit boards including two-stage CMPVD (lower) and

PWM controller (upper). The layout sizes are about15 cm 6 cm and 15 cm 9 cm, respectively, and thecircuit wires are made by the prototype circuit-carvingmachine. In addition, the type of capacitors we suggested isa radial low-ESR aluminium electrolytic capacitor. Becauseits electrolyte film is made very thin, the large capacitancecan be realised in a small volume. Here, we used this kind oflow-ESR capacitors. Next, the hardware circuit is testedpractically for the steady-state response, source/loading

variation (VS 3.0 V, RL 2.2 kV, ID 40 mA,oscilloscope: Agilent Infiniium 54830B). (i) First, thesteady-state response is discussed. Here, the desired outputis selected by Iref 5 mA. In other words, Vo is expected at

11 V (Vo IoRL 5 mA 2.2 kV 11 V). Fig. 8a showsthe measured waveforms of Vo and D. Obviously, theimplemented CMPVD is at the stable step-up conversion,and the mean value of Vo is measured at 10.9965 V, and the

value of D is about 49.9% now. The result shows that Voreally holds on about 11 V, and it can be verified by (6a). Inaddition, the output ripple is measured at about rp 2.27%,and the efficiency is about h 83.61%. (ii) Second, theoutput robustness is considered. Here, the desired output isIref 4.5 mA, that is, Vo is expected at 10 V. Now, for twodifferentVS 3.0 V and 2.7 V, the waveforms of Vo and VSare measured as shown in Figs. 8b and c. In Fig. 8b, Vo is

measured at 10.0522 V when VS

3.0348 V. In Fig. 8c, Vois about 9.9823 V when VS has decreased to2.6956 V. Obviously, Vo still holds on the value of 10 V

although VS changes from 3 to 2.7 V, that is, Io is stillfollowing Iref 4.5 mA in spite of source variation(VS 3.0 V 2.7 V). (iii) Third, the loading variation isconsidered. Fig. 8d shows the waveforms of Vo and VS whenthe same load is added in parallel, and Fig. 8e shows the

waveforms of Vo and VS when the added load is removed

away. In Fig. 8d, the abrupt drop of Vo is appearing whilethe same load is added. Even so, Vo is still regulated quicklyto follow the value of 11 V (Iref 5 mA). In Fig. 8e, theabrupt jump of Vo is turning up while the added load isremoved, but the output regulation can be achieved soon.

Thus, these experimental results are really illustrated to showthe efficacy of the proposed scheme.

6 Conclusions

A new closed-loop two-stage CMPVD is presented by

combining multi-phase operation and PWM technique forlow-power DCDC step-up conversion and output currentregulation. Some relevant theoretical analysis and design arederived. Finally, the closed-loop CMPVD is simulated,and the hardware implementation is realised and tested.

The advantages of the proposed scheme are summarised asfollows: (i) The SC-based CMPVD scheme needs nomagnetic element, so IC fabrication will be promising; (ii)

This CMPVD can obtain high voltage gain by the leastnumber of pumping capacitors; (iii) Since the current-modeoperation is employed here, the steady-state output currentis not a function of supply voltage and load, so the source/loading variation will not make immediate response on theoutput current; (iv) The dominant pole is located in the lefthalf of s-plane, so the open-loop CMPVD is locally stable.So, this scheme has an inherent good local stability. Ofcourse, the disadvantages of our scheme are honestlyenumerated as follows: (i) When the desired Vo is muchsmaller than 4VS, the efficiency will be bad. For betterefficiency, it is helpful to choose Vo to be close to 4VS asmuch as possible. If not realised, we will change source VSor manipulate phase number p (from 4 to 3, 2, or 1) to fitpVS for Vo as close as possible. (ii) It is not easy to realisethe constant ID. After all, it is much easier to obtain aconstant voltage source than a current source. In our paper,

ID is realised with one current reference and two currentmirrors. With a view to implementation, some current-source devices, for example, JFET, DMOST, . . ., and soon, can bring out more convenient approaches. In thefuture, based on this two-stage scheme, it will be a newdirection to develop a generalised structure of multi-stageCMPVD.

7 Acknowledgment

The research of converter circuit theory and application of

Yuen-Haw Chang is financially supported by the NationalScience Council of Taiwan, Republic of China, underGrant NSC 98-2221-E-324-024.



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8 References

[1] DICKSON J.K.: On-chip high voltage generation in

NMOS integrated circuits using an improved voltage

multiplier technique, IEEE J. Solid-State Circuits, 1976, 11,

pp. 374 378

[2] TANZAWA T., TANAKA T.: A dynamic analysis of the Dickson

charge pump circuit, IEEE J. Solid-State Circuits, 1997, 32,

(8), pp. 12311240

[3] WANG C.C., WU J.C.: Efficiency improvement in charge

pump circuits, IEEE J. Solid-State Circuits, 1997, 32, (6),

pp. 852860

[4] MAKO.C., WONG Y.C., IOINOVICI A.: Step-up DC power supply

based on a switched-capacitor circuit, IEEE Trans. Ind.

Electron., 1995, 42, (1), pp. 9097

[5] CHEN J., IOINOVICI A.: Switching-mode DCDC converter

with switched capacitor based resonant circuit, IEEE

Trans. Circuits Syst.-I, 1996, 43, (11), pp. 933938

[6] ZHU G ., IOINOVICI A.: DC-to-DC converter with no

magnetic elements and enhanced regulation, IEEE Trans.

Aerosp. Electron. Syst., 1997, 33, (2), pp. 499506

[7] NGO K.D.T., WEBSTER R.: Steady-state analysis and design

of a switched-capacitor DC-DC converter, IEEE Trans.

Aerosp. Electron. Syst., 1994, 30, (1), pp. 92 101

[8] CHUNG H., IOINOVICI A.: Switched-capacitor-based DC-to-

DC converter with improved input current waveform.

IEEE Int. Symp. Circuits and Systems, Atlanta, USA, 1996,

pp. 541544

[9] ZHU G ., IOINOVICI A.: Steady-state characteristics of

switched-capacitor electronic converters, J. Circuits Syst.

Comput., 1997, 7, (2), pp. 6991

[10] CHANG Y.-H.: Design and analysis of power-CMOS-gate-

based switched-capacitor DCDC converter with step-

down and step-up modes, Int. J. Circuit Theory Appl.,

2003, 31, pp. 483511

[11] CHANG Y.-H.: CPLD-based closed-loop implementation of

switched-capacitor step-down DC DC converter for

multiple output choices, IET Electr. Power Appl., 2007, 1,

(6), pp. 926935

[12] AXELROD B., BERKOVICH Y., IOINOVICI A.: Switched-capacitor/

switched-inductor structures for getting transformer-less

hybrid DCDC PWM converter, IEEE Trans. Circuits Syst.-

I: Regular Papers, 2008, 55, (2), pp. 687696

[13] TAN S.C., NUR M., KIRATIPONGVOOT S., E T A L.: Switched-

capacitor converter configuration with low EMI obtained

by interleaving and its large-signal modeling. IEEE Int.

Symp. Circuits and Systems (ISCAS 2009), Taipei, Taiwan,May 2009, pp. 10811084

[14] UENO F., INUOE T., OOTA I., HARADA I.: Emergency power

supply for small computer systems. IEEE Int. Symp.

Circuits and Systems, 1991, pp. 10651068

[15] U EN O F., I NO UE T., O OTA I .: Real izat io n o f a

switched-capacitor AC DC converter using a new phase

controller. IEEE Int. Symp. Circuits and Systems, 1991,

pp. 10571060

[16] UMENO T., TAKAHASHI K., UENO F., INOUE T., OOTA I.: A newapproach to low ripple-noise switching converters on the

basis of switched-capacitor converters. IEEE Int. Symp.

Circuits and Systems, 1991, pp. 10771080

[17] MAKOWSKI M.S.: Realizability conditions and bound on

synthesis of switched-capacitor DC DC voltage multiplier

circuits, IEEE Trans. Circuits Syst.-I: Fundam. Theory Appl.,

1997, 44, (8), pp. 684691

[18] MAKOWSKI M.S., MAKSIMOVIC D.: Performance limits of

switched-capacitor DC-DC converter. IEEE PESC95 Conf.,

1995, vol. 2, pp. 12151221

[19] ARNTZEN B., MAKSIMOVIC D.: Switched-capacitor DC/DC

converters with resonant gate drive, IEEE Trans. Power

Electron., 1998, 13, (5), pp. 892902

[20] LIU L., CHEN Z.: Analysis and design of Makowski charge-

pump cell. 6th Int. Conf. ASIC (ASICON 2005), 2005, vol. 1,

pp. 497502

[21] STARZYK J.A., JAN Y.-W., QIU F.: A DCDC charge pump

design based on voltage doublers, IEEE Trans. Circuits

Syst.-I, 2001, 48, (3), pp. 350359

[22] MAKOWSKI M.S.: On performance limits of switched-

capacitor multi-phase charge pump circuits. Remarks on

paper of Starzyk et al.. 2008 Int. Conf. Signals and Electronic

Systems (ICSE 2008), 14 17 September 2008, pp. 309 312

[23] SEEMAN M.D., SANDERS S.R.: Analysis and optimization of

switched-capacitor DCDC converter, IEEE Trans. Power

Electron., 2008, 23, (2), pp. 841851



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