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bias conditions. This analytic solution may be used directly in surfacepotential-based current models by evaluating it at the drain and sourceends of the channel. Alternatively, the total inversion charge calculatedfrom the potential at the drain and source ends may be introduced incharge-based current models.

REFERENCES

[1] Q. Chen, K. A. Bowman, E. M. Harrell, and J. D. Meindl, “Double jeop-ardy in the nanoscale court,” IEEE Circuits Devices Mag., vol. 19, no.1, pp. 28–34, Jan. 2003.

[2] J. P. Colinge, “Multiple-gate SOI MOSFETs,” Solid State Electron., vol.48, pp. 897–905, 2004.

[3] R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, “Recentenhancements of MOS Model 11,” in Workshop on Compact Mod-eling, NSTI-Nanotech 2004, vol. 2, Boston, MA, Mar. 7–11, 2004,pp. 60–65.

[4] Y. Taur, “An analytical solution to a double-gate MOSFET with undopedbody,” IEEE Electron Device Lett., vol. 21, no. 4, pp. 245–247, Apr.2000.

[5] Y. Taur, “Analytic solutions of charge and capacitance in symmetric andasymmetric double-gate MOSFETs,” IEEETrans. ElectronDevices, vol.48, no. 12, pp. 2861–2869, Dec. 2001.

[6] X. Shi and M. Wong, “Analytical solutions to the one-dimensionaloxide-silicon-oxide system,” IEEE Trans. Electron Devices, vol. 50, no.12, pp. 1793–1800, Dec., 2003.

[7] Y. Taur, Y. X. Liang, W. Wang, and H. Lu, “A continuous, analytic drain-current model for DG MOSFETs,” IEEE Electron Device Lett., vol. 25,no. 2, pp. 107–109, Feb. 2004.

[8] A. Ortiz-Conde, F. J. G. Sánchez, and M. Guzmán, “Exact analyticalsolution of channel surface potential as an explicit function of gatevoltage in undoped-body MOSFETs using the Lambert W function anda threshold voltage definition therefrom,” Solid State Electron., vol. 47,pp. 2667–2674, 2003.

[9] R. M. Corless, G. H. Gonnet, D. E. G. Hare, D. J. Jeffrey, and D. E.Knuth, “On Lamberts W function,” Adv. Comput. Math., vol. 5, pp.329–359, 1996.

[10] A. Ortiz-Conde, F. J. G. Sánchez, and J. Muci, “Exact analyticalsolutions of the forward nonideal diode equation with series and shuntparasitic resistances,” Solid State Electron., vol. 44, pp. 1861–1864,2000.

[11] T. C. Banwell, “Bipolar transistor circuit analysis using the Lam-bert W-function,” IEEE Trans. Circuits Syst. I, vol. 47, no. 12, pp.1621–1633, Dec. 2000.

[12] J. He, J. X. Xi, C. H. Lin, M. Chan, A. Niknejad, and C. Hu, “Anoncharge-sheet analytic theory for undoped symmetric double-gateMOSFET from the exact solution of Poisson’s equation using SSPapproach,” in NSTI-Nanotech 2004, vol. 2, Boston, MA, Mar. 7–11,2004, pp. 124–127.

[13] S.-H. Kim and J. G. Fossum, “Nanoscale CMOS: Potential nonclassicaltechnologies versus a hypothetical bulk-silicon technology,” Solid StateElectron., vol. 49, pp. 595–605, 2005.

[14] UFDG MOSFET Model Users Guide (Ver. 2.4): SOI Group (2003, Oct.).[Online]. Available: http://www.soi.tec.ufl.edu

[15] A. Ortiz-Conde, F. J. G. Sánchez, P. E. Schmidt, and A. Sa-Neto, “Thenonequilibrium inversion layer charge of the thin-film SOI MOSFET,”IEEE Trans. Electron Devices, vol. 36, no. 11, pp. 1651–1656, Nov.1989.

[16] J. J. Liou, A. Ortiz-Conde, and F. J. G. Sánchez, Design and Analysis ofMOSFETs: Modeling, Simulation, and Parameter Extraction. Boston,MA: Kluwer, 1998.

[17] A. Ortiz-Conde, F. J. G. Sánchez, P. E. Schmidt, and A. Sa-Neto, “Onthe charge-sheet model of the thin-film MOSFET,” inProc ISA TwentiethAnnual Modeling and Simulation Conf., vol. 20, Pittsburgh, PA, 1989,pp. 1341–1345.

[18] A. Ortiz-Conde, R. Herrera, P. E. Schmidt, F. J. G. Sánchez, and J. An-drian, “Long-channel silicon-on-insulator MOSFET theory,” Solid StateElectron., vol. 35, pp. 1291–1298, 1992.

[19] A. Chatterjee, C. F. Machala, and P. Yang, “A submicron DC MOSFETmodel for simulation of analog circuits,” IEEE Trans. Computer-AidedDesign Integr. Circuits Syst., vol. 14, pp. 1193–1207, 1995.

Design and Analysis of Multichannel LIGBTs inJunction Isolation Technology

David W. Green, Shyam Hardikar, Ramakrishna Tadikonda,Mark Sweet, Konstantin V. Vershinin, and E. M. Sankara Narayanan

Abstract—Performance of multichannel lateral insulated gate bipolartransistors (MC-LIGBTs) fabricated in a cost-effective, fully implanted,CDMOS-compatible process in junction isolation technology is reported.Due to the presence of additional MOS cathode cells, the MC conceptenables a reduction in the forward voltage drop. Furthermore, the MCconcept is combined with the segmented N P/P anode (SA-NPN) con-cept in an LIGBT structure. The SA-NPN anode concept reduces turnofflosses due to a reduction in injection of holes and from the collection ofelectrons by the narrow base–collector shorted NPN bipolar transistorformed at the anode. It is shown that combining the MC and the SA-NPNAnode concepts creates a device that exhibits both low on-state and turnofflosses and thus best placed for use in power IC applications.

Index Terms—High voltage, lateral insulated gate bipolar transistors(LIGBTs), multichannel (MC), power IC, segmented anode.

I. INTRODUCTION

Design modifications to lateral insulated gate bipolar transistor(LIGBT) enabling the device to operate at higher current densitiesare of great interest. Multichannel LIGBTs (MC-LIGBT) have beenpreviously demonstrated in the double epitaxial layer dielectric iso-lation [1] and silicon-on-insulator (SOI) technologies [2], [3]. TheMC-LIGBT offers a reduction in forward voltage drop due to theadditional channels, which drive the base of the PNP transistor inthe LIGBT. The increase in current due to the addition of cathodecell(s) should offset the increase in area in order to make the devicearea efficient. It is reported in [1] that device enhancement is pos-sible through optimising the spacing between cells. The downside tofabricating the MC-LIGBT in the technologies reported previouslyis the high fabrication complexity and high cost of SOI substrates,whereas junction isolation (JI) is simple and highly cost effective. Toour knowledge, MC-LIGBT fabricated in a fully implanted CDMOScompatible JI process is yet to be reported.

A key problem with the use of conductivity modulated devices inJI technology, such as the LIGBT is the possibility of carriers beinginjected into the substrate, which can cause malfunction of associatedlogic and control circuits in a power IC. However, effective methodsof crosstalk suppression have recently been proposed to alleviate suchproblems [4].

Due to conductivity modulation, a significant volume of carrierstrapped in the drift region must either recombine or be extractedbefore the device can turn off. One of the most promising anodeconcepts so far proposed to offer enhanced switching characteristicsis the segmented N +P/P+ anode (SA-NPN) [6]–[8]. This concepthas been proven to improve the tradeoff between conduction/turnofflosses much more significantly than shorted anode LIGBTs [6].Consequently, we have combined the SA-NPN and the MC conceptsto form a single device with improved tradeoff between conductionand turnoff losses.

Manuscript received January 10, 2005; revised April 4, 2005. This work wassupported in part by the Engineering and Physical Sciences Research Councilunder Grant GR/R95029/01 and in part by Semelab Plc, U.K. The review of thisbrief was arranged by Editor G. Groeseneken.

The authors are with the Emerging Technologies Research Centrer, De Mont-fort University, Leicester LE1 9BH, U.K. (e-mail: DGreen@dmu.ac.uk).

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Fig. 1. Simplified 3-D schematic of the MC-LIGBT with SA-NPN anode inJI with 1.5-cathode cells.

II. STRUCTURE AND OPERATION

A simplified three-dimensional (3-D) schematic of the MC-LIGBTwith SA-NPN anode is shown in Fig. 1. The cathode of the MC-LIGBTconsists of one full cell with two N-MOS channels and a half cell withone N-MOS channel. Although further “full cells” could be added be-yond the one shown in Fig. 1, we have found that the addition of asingle “full cell” gives optimum performance with the current designrules. All the gates and cathodes are tied respectively together to forma three-terminal device. To turn on, the gates are biased above thethreshold voltage of the N-MOS, which supplies the base current to thePNP transistors. As the anode voltage is increased, the vertical PNP (P+

anode/N-buffer/N-drift/P-substrate) transistor is driven into saturationat low anode voltages. With further increase in anode voltage, the Kirkeffect results in the relocation of the electric field from the N-drift/P-substrate junction below the anode to the P-substrate/P+isolation junc-tion [1]. This enables conductivity modulation to occur deep in the sub-strate, not only below the drift region but, critically below the additionalcathode cell(s) and the sandwich region. Consequently, the possibilityof any JFET effects in the pinch-off region is removed, allowing elec-trons from the additional channels to flow easily under the cathode cellsand into the drift region. The resistance of the sandwich region is animportant factor, which influences the forward voltage drop. Althoughreducing the spacing between cells will reduce the overall area of thedevice, it will also lead to an increase in the JFET resistance of thesandwich region. Therefore, cell spacing must be optimized for the bestdevice performance.

The device is turned off by biasing the gate below the thresholdvoltage. The narrow base–collector shorted junction formed at theanode in the SA-NPN enhances the turnoff loss characteristics of theLIGBT. The NPN component formed at the anode extracts electronsfrom the drift region during turnoff. The narrow P-base region atthe anode has a moderate doping level and provides a path of highdiffusivity for minority carriers. During turnoff, minority carriers (inthe case of the P-base region, electrons) are removed from the driftregion through the P-base anode region. Once electrons enter theP-base region, they are swept out by the electric field formed by thebuilt-in potential of the base–collector shorted junction. Further detailson the design and operation of the SA-NPN can be found in [6]–[8].

III. EXPERIMENTS

Both single-channel and MC-LIGBT structures with conventionalanodes and SA-NPN anodes have been fabricated using a CDMOScompatible process in junction isolation (JI) technology [6]. All de-vices have a racetrack type layout. For the MC devices the distance

Fig. 2. Measured breakdown voltage behavior of the LIGBT and MC-LIGBTwith and without additional N-Well implant.

between the two cathode cells, LSP, was varied between 6 and 18 �m.For the MC device with SA-NPN anode the ratio of N+/P-base to P+

segments at the anode was set at 0.6, which has been shown to givea good tradeoff between conduction and turnoff losses [6], and its cellspacing was set at 9 �m. In addition, a selection of MC-LIGBT deviceshave an additional N-Well implant incorporated in the sandwich regionin a similar manner to those reported in [3]. This was implemented inthe same process step as the N-Buffer region at the anode so as to re-duce the number of mask steps. The additional N-Well implant was alsoincorporated into the design of the MC-LIGBT with SA-NPN anode.The majority of the experimental study will focus on devices that havea drawn drift length of 50 �m. An additional study is made on the ef-fect of varying the drift length, between 30 and 60 �m. The dopingconcentration of the drift region is optimized to fulfil the RESURF con-dition. As the MC-LIGBT operates in a similar manner to the LIGBTwhen under reverse bias, the breakdown behavior of the MC-LIGBTis no different to the LIGBT. Consequently for a 50-�m drift lengtha breakdown voltage in the region of 550 V is obtained, as shown inFig. 2. There is no noticeable difference in the reverse leakage currentand breakdown voltage behavior of MC-LIGBT with and without ad-ditional N-Well implant, which can also be seen in Fig. 2.

The difference in breakdown voltage between devices of differingcell spacing is within the margin of error between samples. The break-down voltage behavior of the MC-LIGBT is similar to a conventionalLIGBT as the potential in the sandwich region is at a low voltage.The presence of the N-Well between the cathode cells has no effecton the breakdown performance of the device. This is clearly evidentfrom Fig. 3(a) and (b) which shows potential contours for MC-LIGBT,LSP = 12 �m, under a reverse bias of 500 V for devices with andwithout N-Well, respectively. The breakdown voltage behavior is thesame in LIGBT and MC-LIGBT structures with identical drift regiondimensions and doping concentrations.

Our simulation study indicates that the latchup current density ofMC-LIGBTs must be higher than that of the single channel devices, asshown in Fig. 4. The higher latchup current of the MC-LIGBT is dueto sharing of the hole current between cathode cells. It was observedthat the higher the level of hole current flowing into the sandwich regionthe higher the latchup current. Therefore the MC-LIGBT with optimumcell spacing (12 �m) shows the highest level of latch-up current as ahigher proportion of current is flowing into the sandwich region.

1674 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005

Fig. 3. Potential contours of simulated MC-LIGBT ( = 12 m) undera reverse bias of 500 V for (a) without N-Well implant and (b) with N-Wellimplant.

Of the fabricated devices, the conventional LIGBT shows a staticlatch-up current density rating in excess of 350 A/cm2. In contrastto the expectations, due to a design error in the current batch ofdevices, the static and dynamic latch-up current densities were muchlower, in the region of 120 A/cm2, for all MC-LIGBTs. The cause ofthe reduced latch-up current in the experimental devices is believedto be due to electric field crowding at the cathode corners of theracetrack structures, due to the reduced radii of the internal corner inthe current design [9].

A. Steady-State Behavior

Equivalent structures to the experimental structures were simulated,with the predicted results in good agreement with the measured values.To illustrate the significant contribution made by the channels facingthe sandwich region the simulated MC-LIGBT (without N-Well) struc-ture with LSP = 6 �m showing current flow lines during on-stateis shown in Fig. 5, with an anode potential VANODE = 2 V andgate potential VGS = 5 V. For the experimental devices the forward

Fig. 4. Simulated latch-up current density as a function of cell spacing forMC-LIGBT and conventional LIGBT clearly showing enhanced latch-upcharacteristics for all MC-LIGBT devices.

Fig. 5. Simulated current flow lines for MC-LIGBT (without N-Well) with= 6 m with = 5 V and = 2 V, clearly showing a

significant amount of current flowing through the sandwich region.

voltage drop has been measured at VGS = 5 V and a current densityof 70 A/cm2. In Fig. 6 is shown the variation in the measured forwardvoltage drop with cell spacing for the fabricated MC devices, with andwithout N-Well, along with data points for conventional LIGBT withand without SA-NPN. As can be seen, devices without N-Well show aminimum for a cell spacing of 12 �m. When the additional N-Well im-plant is made, a cell spacing of 6 �m gives the lowest forward voltagedrop and no minimum is observed.

At high current densities, the advantages of the MC concept becomemore pronounced with increasing drift lengths, as shown in Fig. 7. Thebreakdown voltage varied from 300 V for 30-�m drift length devicesto 650 V for 60-�m drift length devices with no discernable differ-ence between the breakdown voltage of MC-LIGBT and conventionalLIGBT for equivalent drift lengths. With shorter drift lengths the effectof the current induced base widening is restricted and the majority ofcurrent flow occurs nearer the surface to the first cell. However, with alonger drift length carriers tend to flood deeper into the substrate. Thisenables an increase in modulation below the cathode cell(s), so that

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Fig. 6. Experimental forward voltage drop versus cell spacing for theMC-LIGBT with SA-NPN anode and for the MC-LIGBT with and withoutN-Well, showing reduced forward voltage drop in all instances in comparisonto conventional LIGBT.

Fig. 7. Forward voltage drop/drift length tradeoff for MC-LIGBT andConventional LIGBT, showing increased benefit from incorporating the MCconcept with longer drift lengths.

the contribution from the additional channels becomes higher, whichcauses further reduction in the forward voltage drop.

B. Turnoff Behavior

The turnoff characteristics have been measured using an inductiveload, L = 17 mH, VANODE = 200 V, RG = 22 ; VGS = +5=0 Vin 500 ns for all devices. Current and voltage waveforms for theMC-LIGBT and for conventional LIGBT are given in Fig. 8. Althoughthe MC-LIGBT (LSP = 12 �m) turns off noticeably faster thanthe conventional LIGBT the overall effect on switching losses is notsignificant.

The measured turnoff loss results for MC-LIGBT and conventionalLIGBT (with and without SA-NPN anode) for inductive switching areshown in Fig. 9. It can be seen that the MC-LIGBT without N-Well im-plant shows similar turnoff loss characteristics as that of a conventionalLIGBT [1]. The MC devices with N-Well implant show a marginal in-crease in turnoff losses. This is due to the higher doping concentration

Fig. 8. Measured inductive switching current and voltage waveforms forMC-LIGBT with and without SA-NPN anode and conventional LIGBT. With= 17 mH, = 200 V, = 22 = +5 0 V in 500

ns for all devices.

Fig. 9. Measured switching losses at 50 A/cm showing no significantvariation as a function of cell spacing for the MC device in comparison to aconventional device ( = 0 m).

and volume of carriers in the sandwich region, which slows the refor-mation of the depletion region.

The trend observed in the simulated results agrees well with themeasured results shown in Fig. 9, with the MC-LIGBT showingturnoff losses approximately equal to conventional LIGBT. As wehave clearly shown through measurements the additional N-Wellimplant reduces forward voltage drop but exhibits slightly increasedturnoff losses. Therefore the doping concentration of this region mustbe optimized. A further increase in the doping concentration of theN-Well implant leads to a further reduction in the forward voltagedrop, yet an increase in turnoff losses.

Although a conventional LIGBT with SA-NPN anode shows anincrease in forward voltage drop, the combination of the two concepts(MC and SA-NPN) has the effect of compensating for the reduced in-jection from the P-Base anode region, while maintaining low switchinglosses. The turnoff losses of the MC-LIGBT with SA-NPN anode arenot as low as conventional LIGBT with SA-NPN anode. This is dueto the additional carriers injected in the device. Typical current and

1676 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005

Fig. 10. Forward voltage drop/turnoff loss tradeoff for conventional LIGBTwith and without SA-NPN, optimum MC-LIGBT with and without N-welland MC-LIGBT with SA-NPN anode, the MC-LIGBT with SA-NPN showssignificantly improved tradeoff characteristics in comparison to all otherdevices

voltage switching waveforms for MC-LIGBT with SA-NPN anodeare shown in Fig. 8. The on-state/turnoff loss tradeoff is shown inFig. 10, along with data points for conventional LIGBT and optimallydesigned MC-LIGBT (with and without N-Well). Clearly combiningthe MC-LIGBT concept with SA-NPN anode concept generates oneof the most energy efficient devices reported to date—with both a lowon-state and low turnoff losses. For MC-LIGBT with SA-NPN anode,turnoff losses are reduced by over 60% and on-state losses reduced byover 12% in comparison to conventional LIGBT and by over 20% incomparison to conventional LIGBT with SA-NPN anode.

IV. CONCLUSION

We have successfully demonstrated the MC concept in JI technologythrough experiment and simulations in a fully implanted process. Addi-tionally, the concept has been combined with the segmented N+ P/P+anode concept. This combination of concepts creates one of the mostarea and energy efficient devices reported to date, which exhibits lowturnoff loss characteristics, comparable to the SA-NPN LIGBT andcritically low conduction loss characteristics. Moreover, all of our de-sign variations showed improvement in comparison to a conventionalLIGBT with respect to forward voltage drop. The results presentedherein show, for the first time, that in terms of cost and performance,the lateral MC-LIGBT with SA-NPN anode is a viable competitor toequivalent vertical IGBT up to 900 V either as a discrete (up to 5 A) oras fully integrated component in an area efficient power IC.

ACKNOWLEDGMENT

The authors would like to thank the staff from Semefab plc, U.K. forthe fabrication of the devices, and Dr. O. Spulber for helpful discus-sions. D. Green would like to thank Prime Faraday Partnership for hisIndustrial CASE studentship award.

REFERENCES

[1] Z. Qin and E. M. S. Narayanan, “A novel multichannel approach to im-prove LIGBT performance,” in Proc. ISPSD, 1997, pp. 313–316.

[2] T. Matsudai, M. Kitagawa, and A. Nakagawa, “A trench-gate injectionenhanced lateral IEGT on SOI,” in Proc. ISPSD, 1995, pp. 141–145.

[3] H. Funaki, T. Matsudai, A. Nakagawa, N. Yasuhara, and Y. Yamaguchi,“Multi-channel SOI lateral IGBTs with large SOA,” in Proc. ISPSD,1997, pp. 33–36.

[4] B. Bakeroot, J. Doutreloigne, and P. Moens, “A new substrate currentfree nLIGBT for junction isolated technologies,” in Proc. ESSDERC,1997, pp. 461–464.

[5] A. Nakagawa, H. Funaki, Y. Yamaguchi, and F. Suzuki, “Improvementin lateral IGBT design for 500 V 3 A one chip inverter ICs,” in Proc.ISPSD, 1997, pp. 321–324.

[6] S. Hardikar, R. Tadikonda, M. Sweet, K. Vershinin, and E. M. S.Narayanan, “A fast switching segmented anode npn controlled LIGBT,”IEEE Electron Device Lett., vol. 24, no. 11, pp. 701–703, Nov., 2003.

[7] S. Hardikar, Y. Z. Xu, M. M. De Souza, and E. M. S. Narayanan, “A seg-mented anode, Npn controlled lateral insulated gate bipolar transistor,”Solid State Electron., vol. 45, pp. 1055–1058, 2001.

[8] D. W. Green, S. Hardikar, M. Sweet, K. Vershinin, R. Tadikonda, M.M. De Souza, and E. M. S. Narayanan, “Influence of temperature anddoping parameters on the performance of segmented anode NPN (SA-NPN) LIGBT,” in Proc. ISPSD, 2004, pp. 285–288.

[9] S. Hardikar, J. Nicholls, D. Green, M. Sweet, and E. M. S. Narayanan,“Influence of layout design on the performance of LIGBT,” in Proc. 7thInt. Seminar Power Semiconductors Conf., 2004, pp. 235–238.

On the Parasitic Gate Capacitance of Small-GeometryMOSFETs

M. Jagadesh Kumar, Vivek Venkataraman, and Sumeet Kumar Gupta

Index Terms—Analytical model, device scaling, MOSFETs, parasitic ca-pacitance.

Parasitic capacitances in aggressively scaled-down MOSFETs playa major role in influencing the device performance. Often, accurateand simple models are required to predict the detrimental effect ofthe parasitic capacitances which often do not scale down with devicedimensions.

Reference [1] is the earliest paper to have reported a semi-analyticalmodel for the edge capacitance of thick electrodes. Using the Kam-chouchi model, various dependencies of the parasitic capacitances insmall geometry MOS devices are evaluated by Greeneich [2]. Later,Suzuki [3] evaluated the dependence of parasitic capacitance on gatelength, gate electrode thickness, and gate oxide thickness using atwo-dimensional (2-D) device simulator and compared his model withKamchouci model and concluded that either Kamchouci model orSuzuki model should be used for small size devices since both modelsreproduce the numerical data well.

Various capacitance components [3] in a scaled-down MOSFET areshown in Fig. 1.

The Kamchouchi model [1] for Cside; Cbottom, and Ctop is given as

Cside ="ox

�`n[a]

Manuscript received February 14, 2005. The review of this brief was arrangedby Editor V. R. Rao.

The authors are with the Department of Electrical Engineering, Indian Insti-tute of Technology, New Delhi 110 016, India (e-mail: mamidala@ieee.org).

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