Deployment of JTAG Based HW Self-test in RBS 6000 · 11/22/2011 · Slide title minimum 48 pt...

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DEPLOYMENT OF JTAG BASED

HW SELF-TEST IN RBS 6000

Gunnar Carlsson

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text in the footer area Deployment of JTAG Based HW Self-test in RBS 6000 | © Gunnar Carlsson, Ericsson | 2011-11-22 |

Outline

› Introduction – Co-operative Development

– Why HW Self-test

› RBS 6000 HW Self-test Approach

› SerDes Test via JTAG

› Functional Operation

› HW Implementation

› System Implementation

› Test Data Structure

› Test Development and Diagnosis

› Conclusion

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Co-operative Development

› The development of this Embedded JTAG Test

implementation was done in co-operation between

Ericsson (DU Radio) and SAAB (BA Support and Services)

› It is based on Ericsson concept and HW, and SAAB SW

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Why HW Self-test

› HW self-test is mainly intended for use in the field

› Faults we expect in the field

– The HW may have faults that escaped production test

– Faults may occur due to reliability issues and ageing

– Faults may be permanent, trancient or intermittent

› Fault indications

– The HW is continuously supervised by HW and SW, issuing alarms at fault indications

– The operator may observe strange behaviour, not detected by HW supervision, e.g. elevated dropped call rate

› Field test purposes

– Detect latent faults at power-on/restart of boards

– Validate HW faults related to alarms (do we need to replace HW?)

– Avoid non-faulty units being sent to repair (NFF)

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RBS 6000 HW Self-test Approach

› When is HW Self-test used?

– Automatically at power-up and restart

– At automatic recovery attempts (when everything else fails)

– Ordered by operator

– (Also used in production and repair )

› Test and recovery flow

1. JTAG based interconnect test (IEEE 1149.1 and IEEE 1149.6)

2. JTAG based MBIST and LBIST of ASIC’s

3. JTAG based PRBS test of serial links

4. JTAG based MBIST of DSP’s (when supported by vendors)

5. Functional test of serial links

6. Functional memory test

7. Functional Power on Self Test (POST) of DSP’s, provided by vendor

8. (Functional test of other complex devices)

9. Reset, and load & start of application SW

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Typical SerDes with JTAG controlled Test Features

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Functional Operation

› Two Major Modes of Operation:

› System mode

– Automatic test initiated at power-on and restart

– Test controlled via automatic fault escalation (at recovery attempts)

– Operator requested test started from his GUI

– Diagnostics down to replaceable unit (to the operator)

– More fine grained diagnostics in on-board flash log (for repair center)

› Command line mode

– Communication via Ethernet or RS232 link (front panel connector)

– Can be used at RBS level or on separate BB units

– Commands to start test and retrieve diagnostic info for manual analysis (or by

off-line tools)

– Diagnostics down to repair action supported by 3’rd party tool (today SAAB’s

TSTAP)

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Functional Operation (cont.)

› Generic test execution SW (Scan Engine, SE), works on all boards

with the same execution platform

› Individual board test data (JTAG test vectors), specific to each

board and revision, resident in boot flash

› SE sends JTAG vectors on the JTAG bus, receives response, and

compare against expected data

› SE can handle several different sets of vectors, selected by options

and commands

› SE sends results to System Fault Management, or through the

Command Line Interface (depending on mode of operation)

› Functional tests are now implemented in application SW, but will

be implemented in a single load module resident in flash, reusing

production test routines

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HW Implementation

ASIC

B DSP

ASIC

C DSP

ASIC

C DSP

ASIC

C DSP

DSP

DD

R3

DSP

Flash mP

Board Platform

Tra

ffic

Application

De

Se

ria

lize

r

ASIC

C

MTC

Tra

ffic

&

Co

ntr

ol

Syste

m B

scan

BScan

Protocol

Handler

ASIC

D

Scan

Engine

JTAG

Vectors

Support

FPGA

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JTAG Routing

mP

FPGA

MTC

TDI TDO

TMS

TCK

Logic tested via MTC

• At board production test, all devices are in active BScan mode

• At MTC test, mP and FPGA are in BYPASS

• Devlopment and debug of embedded JTAG vectors can be done

with traditional methods and tools

Develo

pm

ent

environm

ent

JTA

G b

oard

test connecto

r

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System Implementation

CHPI

CHPI

Future external IF

(Only for Scan

Engine tests) TEMI

BTMI

Board Test Manager

Scan Engine

TEM Server

Future test requester

Future test Engine DC power check

Board Manager

CHP Server

Scan Engine Func. Tests

Scan Engine Test Vectors

Resident in flash memory

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Test Data Structure

IR-Scan DR-Scan IR-Scan DR-Scan IR-Scan DR-Scan IR-Scan DR-Scan

L-BIST


M-BIST


Interconnect1

Vector files (bin. SVF)

TLR gen_reset 1 P gp_io 2 P gen_reset 3 P Et_run M-BIST

mbist

TLR gen_reset 0 P gen_reset 2 P gp_io 4 P Et_run L-BIST

lbist

TLR

Et_run Interconnect1

interconnect

Test definitions Sequence definitions

interconnect mbist

GONOGO

lbist

mbist

BIST

lbist

In System mode, the

GONOGO sequence is

selected by default.

Individual Sequences,

Tests and Vectors can

be run from the

Command Line Interface

One text file

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Test Development and Diagnosis

Bscan

development

environment

used today

at Ericsson

SVF Commercial

Development

Platform

Other

Development

Platform SVF

Command

Line

Interface

Traditional

Bscan test

RBS 6000 System

controlled test

Ethernet/RS 232

Baseband Board

Embedded

Scan Engine

5-pin

connector

Board Control SW

Commercial

Diagnostic

Tool

PC SW

Bscan prod. test i/f

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Conclusion

› An improved HW Test strategy for RBS 6000 has been

introduced, based on Embedded JTAG techniques

› A common Scan Engine is used by all products which are

using the same processing platform

› Product unique test vectors are resident on the HW

› Test development is largely simplified, using traditional

JTAG development platform and methods

› Embedded functional test will be the next step, including

methods to reuse production test routines

› The co-operation with SAAB gave us a jump-start into this

concept

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Deployment of JTAG Based HW Self-test in RBS 6000 · 11/22/2011 · Slide title minimum 48 pt...

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