Department of Information Engineering and Mathematics...

http://www.dii.unisi.it/~giorgi/teaching/hpca2

Vivado High Level Synthesis (HLS)

Department of Information Engineering and Mathematics

Presenter: Eng. Farnam Khalili(under supervision of Prof. Roberto Giorgi)

Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 551

Outline

• Introduction• HLS advantage/disadvantage• How does HLS work?• Vivado HLS work flow • Examples

Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 552

Introduction:

3Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 55


Available in production today C/C++/SystemC• Adopted across broad base of applications and

markets • Proven on real customer designs • Clear differentiator for accelerating design

productivity

[1]

FPGA

Image courtesy of Xilinx

Introduction:


• The idea of HLS is to accelerate the HDL production (IP Core) of your desired algorithm base on C/C++/SystemC

• Create RTL implementation from C level source code

• Implements the design based on defaults and user applied directives

• Implements different solutions with the same source C description


[1]


Sys Generator IP Catalog


[1]

Introduction:

5Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 55Image courtesy of Xilinx


[1]

• Only for 7 series FPGA and Zynq SoC Vivado Implementation

Introduction:

6Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 55 Image courtesy of Xilinx

Vivado High Level Synthesis (HLS)HLS Advantages:

• Increased system performance• Using HDL (Verilog/VHDL) sometimes is time consuming and inconvenient for high level algorithms like DSP (digital signal processing) and mathematical algorithms.

• BOM (Bill of Material )cost reduction • Reduced total power consumption • Build better system with fewer chips and faster way. • Efficient specification using C/C++/SystemC• Directive based design exploration• Comprehensive integration


Vivado High Level Synthesis (HLS)HLS Disadvantages:

The generated HDL code is not the most readable You have not any control on your hardware architecture!• Vivado HLS has following C/C++ limitations:

1) No dynamic memory (all need to be static). For instance, no malloc, new, delete or free

2) Doesn’t support STD, FILE-I/O (no system calls)3) Recursive functions must be avoided


Vivado High Level Synthesis (HLS)How does HLS work?

• Your code will be extracted as a Finite State Machine


Function Start

Function End

For Loop Start

For Loop End

Image courtesy of Dr. F Rincon Calle


• Operations are extracted and mapped to each states


A unified control dataflow behavior is created

Image courtesy of Dr. F Rincon Calle


• Scheduling the operations by mapping them into clock cycles

11Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 55Image courtesy of Dr. F Rincon Calle


• Assigning the operations to available functional units

12Roberto Giorgi, Universita' degli Studi di Siena, C218ES07--SL di 55Image courtesy of Dr. F Rincon Calle

Vivado High Level Synthesis (HLS)Key attributes of code


Functions: represents the design hierarchy

Top Level IO: Top-level arguments determine interface ports

Types: Types influences area and performance

Loops: Their scheduling has major impact on areaAnd performance

Operators: can be shared or replicated to meet performance

Arrays: mapped into memory. May become main performance bottlenecks

Vivado High Level Synthesis (HLS)Functions and RTL hierarchy


Source Code (Function)Each function is translated to an RTL block using in

Vivado block design (As an IP)

Vivado HLS Environment

Vivado Block Design Enviroment

Vivado High Level Synthesis (HLS)Example:

1) Definition of the function/algorithm2) Simulation the compiled code3) Synthesis of compiled cod (RTL implementation)4) Co-simulation the design


Vivado High Level Synthesis (HLS)Vivado HLS getting started:


Vivado High Level Synthesis (HLS)Creating a new project:


Vivado High Level Synthesis (HLS)Adding a new C/C++ file:


Vivado High Level Synthesis (HLS)Adding a test-bench file (c/c++):


Vivado High Level Synthesis (HLS)Setting the solution configuration:


Vivado High Level Synthesis (HLS)Vivado HLS Environment:


Commands Toolbar Environment Perspectives

Auxiliary Pane : you canSet different Directives and

OutlinesInformation Pane: you can open/edit your codes (C/C++/Verilog/VHDL/etc) and check

solution reports.

Console Pane: you can monitor system messages, errors, warnings

Explorer Pane: hierarchical of project files

Vivado High Level Synthesis (HLS)Specifying the Top Function:


Once your code are finished you have to specify the top

function

Vivado High Level Synthesis (HLS)Specifying the Top Function:


Once your codes are finished you have to specify the top function

Vivado High Level Synthesis (HLS)Running C Simulation:


To verify that your C code is correct and has no error!

Vivado High Level Synthesis (HLS)Debugging your C project:


You may be asked to open the Debug perspective

Vivado High Level Synthesis (HLS)Synthesizing your C code:


Vivado High Level Synthesis (HLS)Applying Directive to your Function:


Synthesizing your C code with new Directive:


Vivado High Level Synthesis (HLS)Running C/RTL Co simulation:


Vivado High Level Synthesis (HLS)Opening the wave viewer:


Vivado High Level Synthesis (HLS)Export RTL of your C code:


You can find generated Verilog from “impl” folder:



Using generated IP in Vivado block design:

•Creating a new Vivado project



• Getting started with Vivado 2017.2 design tool



•Getting started with Vivado 2017.2 design tool


Vivado High Level Synthesis (HLS)Using generated IP in Vivado block design:




• We have not any User VHDL/Verilog source code in our project, so just next please!



• We can later add the desired constraint file!




• Specifying the targeted Xilinx part



• Summary of the project that would be created:


Vivado High Level Synthesis (HLS)The Vivado design suite environment



HDL source HDL source codes/ Block

designsSynthesize Implement Generate

Bitstream

XSTXST BitGenBitGenFPGA

Bitstream

Translate Map Place & Route

Design flow in Vivado Design Suite



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Adding the generated IP to IP repositories of vivado project:


Vivado High Level Synthesis (HLS)Creating a new block design:


Vivado High Level Synthesis (HLS)Adding the generated IP into the block design:



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2

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Finally, your design could be something similiar to this:


Vivado High Level Synthesis (HLS)References:

• [1] www.Xilinx.com


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