Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Lecture 12: MOS...

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 12

Lecture 12: MOS Transistor Models

Prof. Niknejad


EECS 105 Fall 2003, Lecture 12 Prof. A. Niknejad

Lecture Outline

MOS Transistors (4.3 – 4.6)– I-V curve (Square-Law Model)– Small Signal Model (Linear Model)



Observed Behavior: ID-VGS

Current zero for negative gate voltage Current in transistor is very low until the gate

voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor)

Current increases rapidly at first and then it finally reaches a point where it simply increases linearly

GSV

DSI

TV

GSV

DSIDSV



Observed Behavior: ID-VDS

For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly

and the rate of increase of current slows Eventually the current stops growing and remains essentially

constant (current source)

DSV

/DSI k

“constant” current

resistor region

non-linear resistor region

2GSV V

3GSV V

4GSV V

GSV

DSIDSV



“Linear” Region Current

If the gate is biased above threshold, the surface is inverted

This inverted region forms a channel that connects the drain and gate

If a drain voltage is applied positive, electrons will flow from source to drain

p-type

n+ n+p+

Inversion layer“channel”

GS TnV V

100mVDSV G

DS

NMOS

x

y



MOSFET: Variable Resistor

Notice that in the linear region, the current is proportional to the voltage

Can define a voltage-dependent resistor

This is a nice variable resistor, electronically tunable!

( )DS n ox GS Tn DS

WI C V V V

L

1( )

( )DS

eq GSDS n ox GS Tn

V L LR R V

I C V V W W



Finding ID = f (VGS, VDS)

Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel



Inversion Charge at Source/Drain

)()0()( LyQyQyQ NNN

)()0( TnGSoxN VVCyQ )( LyQN

)( TnGDox VVC

DSGSGD VVV



Average Inversion Charge

Charge at drain end is lower since field is lower Simple approximation: In reality we should

integrate the total charge minus the bulk depletion charge across the channel

( ) ( )( )

2ox GS T ox GD T

N

C V V C V VQ y

Source End Drain End

( ) ( )( )

2ox GS T ox GS SD T

N

C V V C V V VQ y

(2 2 )( ) ( )

2 2ox GS T ox SD DS

N ox GS T

C V V C V VQ y C V V



Drift Velocity and Drain Current

“Long-channel” assumption: use mobility to find v

( ) ( ) ( / ) n DSn n

Vv y E y V y

L

Substituting:

( )2

DS DSD N ox GS T

V VI WvQ W C V V

L

( )2DS

D ox GS T DS

VWI C V V V

L

Inverted Parabolas



Square-Law Characteristics

Boundary: what is ID,SAT?TRIODE REGION

SATURATION REGION



The Saturation Region

When VDS > VGS – VTn, there isn’t any inversioncharge at the drain … according to our simplistic model

Why do curvesflatten out?



Square-Law Current in Saturation

Current stays at maximum (where VDS = VGS – VTn = VDS,SAT)

Measurement: ID increases slightly with increasing VDS

model with linear “fudge factor”

( )2DS

D ox GS T DS

VWI C V V V

L

, ( )( )2

GS TDS sat ox GS T GS T

V VWI C V V V V

L

2, ( )

2ox

DS sat GS T

CWI V V

L

2, ( ) (1 )

2ox

DS sat GS T DS

CWI V V V

L



Pinching the MOS Transistors

When VDS > VDS,sat, the channel is “pinched” off at drain end (hence the name “pinch-off region”)

Drain mobile charge goes to zero (region is depleted), the remaining elecric field is dropped across this high-field depletion region

As the drain voltage is increases further, the pinch off point moves back towards source

Channel Length Modulation: The effective channel length is thus reduced higher IDS

p-type

n+ n+p+

Pinch-Off Point

GS TnV V

DSVG

DS

NMOS

Depletion RegionGS TnV V



Linear MOSFET Model

Channel (inversion) charge: neglect reduction at drain

Velocity saturation defines VDS,SAT = Esat L = constant

- vsat / nDrain current:

)],()[(, TnGSoxsatNSATD VVCvWWvQI

|Esat| = 104 V/cm, L = 0.12 m VDS,SAT = 0.12 V!

)1)((, DSnTnGSoxsatSATD VVVWCvI



Why Find an Incremental Model?

Signals of interest in analog ICs are often of the form:

Direct substitution into iD = f(vGS, vDS) is tedious AND doesn’t include charge-storage effects … pretty rough approximation

( ) ( )GS GS gsv t V v t

Fixed Bias Point Small Signal



Which Operating Region?

3VGSV

3VDSV TRIODE

SAT

OFF



Changing One Variable at a Time

Assumption: VDS > VDS,SAT = VGS – VTn (square law)

GSV

/DSI k

3VDSV 1VTV

Square LawSaturation

Region

Linear TriodeRegion

Slope of Tangent: Incremental current increase



The Transconductance gm

Defined as the change in drain current due to a change in the gate-source voltage, with everything else constant

, ,

( )(1 )GS DS GS DS

D Dm ox GS T DS

GS GSV V V V

i i Wg C V V V

v v L

2, ( ) (1 )

2ox

DS sat GS T DS

CWI V V V

L

( )m ox GS T

Wg C V V

L

0

22DS

m ox ox DS

ox

IW Wg C C I

WL LCL

2

( )DS

mGS T

Ig

V V

Gate Bias

Drain Current Bias

Drain Current Bias and Gate Bias



Output Resistance roDefined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant

Non-Zero Slope

DSV

DSI



Evaluating ro

1

,GS DS

Do

DS V V

ir

v

2( ) (1 )2

oxD GS T DS

CWi V V V

L

02

1

( )2

oxGS T

rCW

V VL

0

1

DS

rI



Total Small Signal Current

( )DS DS dsi t I i

DS DSds gs ds

gs ds

i ii v v

v v

1ds m gs ds

o

i g v vr

TransconductanceConductance



Putting Together a Circuit Model

1ds m gs ds

o

i g v vr



Role of the Substrate Potential

Need not be the source potential, but VB < VS

Effect: changes threshold voltage, which changes the drain current … substrate acts like a “backgate”

QBS

D

QBS

Dmb v

i

v

ig

Q = (VGS, VDS, VBS)



Backgate Transconductance

Result:2 2

Tn mD Dmb

BS Tn BS BS pQ Q Q

V gi ig

v V v V

0 2 2T T SB p pV V V



Four-Terminal Small-Signal Model

1ds m gs mb bs ds

o

i g v g v vr



MOSFET Capacitances in Saturation

Gate-source capacitance: channel charge is not controlled by drain in saturation.



Gate-Source Capacitance Cgs

Wedge-shaped charge in saturation effective area is (2/3)WL(see H&S 4.5.4 for details)

ovoxgs CWLCC )3/2(

Overlap capacitance along source edge of gate

oxDov WCLC

(Underestimate due to fringing fields)



Gate-Drain Capacitance Cgd

Not due to change in inversion charge in channel

Overlap capacitance Cov between drain and sourceis Cgd



Junction Capacitances

Drain and source diffusions have (different) junctioncapacitances since VSB and VDB = VSB + VDS aren’t the sameComplete model (without interconnects)



P-Channel MOSFET

Measurement of –IDp versus VSD, with VSG as a parameter:



Square-Law PMOS Characteristics



Small-Signal PMOS Model



MOSFET SPICE Model

Many “levels” … we will use the square-law “Level 1” modelSee H&S 4.6 + Spice refs. on reserve for details.

Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 12 Lecture 12: MOS...

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