Department of Communication Engineering, NCTU 1 Unit 5 Programmable Logic and Storage Devices –...
Transcript of Department of Communication Engineering, NCTU 1 Unit 5 Programmable Logic and Storage Devices –...
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Department of Communication Engineering, NCTU 1
Unit 5 Programmable Logic and Storage Devices –RAMs and FPGAs
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Department of Communication Engineering, NCTU 2
Unit 5-1 Static Random Access Memory (SRAM)
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Department of Communication Engineering, NCTU 3
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Reason for using random access memory (RAM) Computers and other digital systems perform operations that
retrieve, manipulate, transform and store data Read only memories (ROMs) can not dynamically store data Registers support fast and random storage, but cannot be
used for mass storage because they are implemented with FFs and occupy too much physical area
RAM is faster and occupies less area than a register file Most RAMs are volatile- the information vanishes after
power is removed from the device There are two types of RAMs: static and dynamic
Dynamic RAMs need refresh and static RAMs don’t
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Department of Communication Engineering, NCTU 4
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Basic static RAM (SRAM) structureWord EN
Bit
_lin
e_N
Bit
_lin
e
cellCell_N
Word EN
Bit
_lin
e_N
Bit
_lin
e
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Department of Communication Engineering, NCTU 5
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
module SRAM1 (data_out, data_in, CS_N,WE_N); output data_out; input data_in; input CS_N, WE_N;
wire data_out = (CS_N==0) ? (WE_N==0) ? data_in : data_out : 1’bz;endmodule
Level-sensitive Verilog models of RAMs
A 32K 8 SRAM
data_outCS
WE
data_in
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
CSWEOE
MuxMux
Demux
D_IN
D_OUT
Decoder
data_in
data_out
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Department of Communication Engineering, NCTU 6
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Basic static RAM (SRAM) structure
A 16K SRAM
module SRAM2 (data, CS_N,WE_N,OE_N); output data_out; input CS_N, WE_N,OE_N;
wire latch_out = ((CS_N==0) && (WE_N==0)&&(OE_N==1)) ? data : latch_out;
assign data = ((CS_N==0) && (WE_N==1)&&(OE_N==0)) ? latch_out : 1’bz;
endmodule
data
CS
OE
WE
Column Input/OutputColumn Input/Output
AA1010
AA99
AA00
AA33
AA22
AA11
AA00 DD7 7 DD6 6 DD5 5 DD44DD3 3 DD2 2 DD1 1 DD00
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Department of Communication Engineering, NCTU 7
Unit 5-3 Altera FPGA Architecture
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Department of Communication Engineering, NCTU 8
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Architecture of Stratix Logic array blocks (LABs) :
10 logic elements (LEs) in each LAB Memory block structures
512 RAM: simple dual-port memory blocks (512 +parity =576) M4K RAM: true dual-port memory blocks (4K + parity =4608) M-RAM: true dual-port memory blocks (512K+parity=589,824)
DSP blocks 9×9- or 18×18- or 36×36-bit multiplier with add and subtraction 18-bit input shift registers
I/O element (IOE) : contains a bidirectional I/O buffer and six registers Supports single-ended, differential I/O standards and external
memory devices such as DDR-SDRAM
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Department of Communication Engineering, NCTU 9
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 10
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Logic elements (LE) : the smallest unit of logics in the Stratix architecture each of which contains : A four-input LUT A programmable register :
can be configured for D, T, JK and SR FFs Asynchronous data,
Support single bit addition and subtraction
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Department of Communication Engineering, NCTU 11
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 12
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 13
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 14
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 15
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 16
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 17
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 18
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 19
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Single-Clock SRAM without read-through-write behavior
module ram_infer (q, a, d, we, clk);output reg [7:0] q;input [7:0] d;input [6:0] a;input we, clk;reg [7:0] mem [127:0];always @ (posedge clk) beginif (we)mem[a] <= d;q <= mem[a]; // q doesn't get d in this clock cycleendendmodule
clk
we
a A0 A1 A3
d d(A0)+ d(A1)+ d(A3)+
q d(A1)d(A0)
A2
d(A2)+
d(A2)
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Department of Communication Engineering, NCTU 20
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Single-Clock SRAM with read-through-write behavior
module ram_infer (q, a, d, we, clk);output [7:0] q;input [7:0] d;input [6:0] a;input we, clk;reg [6:0] read_add;reg [7:0] mem [127:0];always @ (posedge clk) beginif (we)mem[a] <= d;read_add <= a;endassign q = mem[read_add];endmodule
clk
we
a A0 A1 A3
d d(A0)+ d(A1)+ d(A3)+
q d(A1)+d(A0)+
A2
d(A2)+
d(A2)+
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Department of Communication Engineering, NCTU 21
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 22
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 23
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 24
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 25
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 26
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 27
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 28
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 29
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 30
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 31
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 32
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 33
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 34
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 35
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 36
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
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Department of Communication Engineering, NCTU 37
Unit 5-4 Model Simulation Library
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Department of Communication Engineering, NCTU 38
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Choose a working directory that you want to store the compiled Choose a working directory that you want to store the compiled Libraries Libraries
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Department of Communication Engineering, NCTU 39
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Create a new library for the compiled libraryCreate a new library for the compiled library
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Department of Communication Engineering, NCTU 40
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Create the library named:stratix_atoms
Repeat the above two procedures For the following two librariesaltera_mf 220model
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Department of Communication Engineering, NCTU 41
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Compile the Compile the stratix_atomsstratix_atoms
Library Library
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Department of Communication Engineering, NCTU 42
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Choose the Choose the stratix_atoms.vstratix_atoms.v
filefile
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Department of Communication Engineering, NCTU 43
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Notice the difference fromNotice the difference from
Map the stratix_atoms Map the stratix_atoms to the compiled stratix_atomsto the compiled stratix_atoms
librarylibrary
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Department of Communication Engineering, NCTU 44
Unit 5-5 Simulation with Altera mega-functions
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Department of Communication Engineering, NCTU 45
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Load Altera_mflibrary
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Department of Communication Engineering, NCTU 46
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Load Altera_mf
Then you are done
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Department of Communication Engineering, NCTU 47
Unit 5-5 Post Layout Simulation
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Department of Communication Engineering, NCTU 48
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Specify options for Generating output filesFor modelsimFile name : *.vo
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Department of Communication Engineering, NCTU 49
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Import top-level Test bench andtop-level design*.vo only
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Department of Communication Engineering, NCTU 50
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Load Stratix_atomslibrary
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Department of Communication Engineering, NCTU 51
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Load Stratix_atomslibrary
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Department of Communication Engineering, NCTU 52
Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu
Notice!! the Instance name of the top-level design, not its module nameNotice!! the Instance name of the top-level design, not its module name
Load *.sdo fileFrom the SDFOption andapply it to the Top-level design