Demo manual Dca - Analog Devices · 1 2064 Demo manual Dca Description LTC3300-1/LTC6803-2...
38
1 dc2064afa DEMO MANUAL DC2064A DESCRIPTION LTC3300-1/LTC6803-2 Bidirectional Cell Balancer Demonstration Circuit DC2064A is a bidirectional cell balancer using two LTC ® 3300-1 ICs to achieve active cell balancing of up to 12 Li-Ion batteries. The board uses the LTC6803-2 multi-cell addressable battery stack monitor to measure cell voltages and two LTC3300-1 ICs to provide active cell balancing. The demonstration circuit uses a two window GUI developed for the DC2064A. One window is a modified version of the GUI for the LTC6803-2 and also contains a tab to control the LTC3300-1 ICs through the DC590B USB Serial controller and the second window L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. PERFORMANCE SUMMARY BOARD PHOTO reports the status of the LTC3300-1 devices. All the functions of the LTC6803-2 GUI are supported except that cell balancing is achieved through the LTC3300-1 ICs by transferring charge from one to six batteries per LTC3300-1 to the stack or from the stack to one to six batteries per LTC3300-1. Design files for this circuit board are available at http://www.linear.com/demo/DC2064A Specifications are at T A = 25°C Battery Voltage Range 3.2V to 4.5V (2.5V to 4.5V)* Stack Voltage 60V Max Average Battery Balancing Charge Current (12 Cell) 2.6A (Typ) (4A)* Average Battery Balancing Discharge Current (12 Cell) 2.4A (Typ) (3.6A)* Average Battery Balancing Charge Current (6 Cell) 2.2A (Typ) (3.3A)* Average Battery Balancing Discharge Current (6 Cell) 2.4A (Typ) (3.6A)* Balancing Efficiency 92% (Typ) *The battery voltage range may be expanded to 2.5V-4.5V by changing resistor R TONS to 19.1k and resistor R TONP to 29.4k. The demo board’s average balancing current is adjustable up to 4A by scaling and installing new values of RS1A and RS1B through RS12A and RS12B.
Transcript of Demo manual Dca - Analog Devices · 1 2064 Demo manual Dca Description LTC3300-1/LTC6803-2...
1dc2064afa
DEMO MANUAL DC2064A
Description
LTC3300-1/LTC6803-2 Bidirectional Cell Balancer
Demonstration Circuit DC2064A is a bidirectional cell balancer using two LTC®3300-1 ICs to achieve active cell balancing of up to 12 Li-Ion batteries. The board uses the LTC6803-2 multi-cell addressable battery stack monitor to measure cell voltages and two LTC3300-1 ICs to provide active cell balancing. The demonstration circuit uses a two window GUI developed for the DC2064A. One window is a modified version of the GUI for the LTC6803-2 and also contains a tab to control the LTC3300-1 ICs through the DC590B USB Serial controller and the second window L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
performance summary
BoarD photo
reports the status of the LTC3300-1 devices. All the functions of the LTC6803-2 GUI are supported except that cell balancing is achieved through the LTC3300-1 ICs by transferring charge from one to six batteries per LTC3300-1 to the stack or from the stack to one to six batteries per LTC3300-1.
Design files for this circuit board are available at http://www.linear.com/demo/DC2064A
Specifications are at TA = 25°C
Battery Voltage Range 3.2V to 4.5V (2.5V to 4.5V)*
Stack Voltage 60V Max
Average Battery Balancing Charge Current (12 Cell) 2.6A (Typ) (4A)*
Average Battery Balancing Discharge Current (12 Cell) 2.4A (Typ) (3.6A)*
Average Battery Balancing Charge Current (6 Cell) 2.2A (Typ) (3.3A)*
Average Battery Balancing Discharge Current (6 Cell) 2.4A (Typ) (3.6A)*
Balancing Efficiency 92% (Typ)
*The battery voltage range may be expanded to 2.5V-4.5V by changing resistor RTONS to 19.1k and resistor RTONP to 29.4k. The demo board’s average balancing current is adjustable up to 4A by scaling and installing new values of RS1A and RS1B through RS12A and RS12B.
2dc2064afa
DEMO MANUAL DC2064A
Description
CELL VOLTAGE (V)2.6 2.8
75
EFFI
CIEN
CY (%
)
85
100
3.0 3.4 3.6
80
95
90
3.2 3.8 4.0
12-CELL
6-CELL
Power Stage Discharge Efficiency Power Stage Charge Efficiency
CELL VOLTAGE (V)2.6 2.8
75
EFFI
CIEN
CY (%
)
85
100
3.0 3.4 3.6
80
95
90
3.2 3.8 4.0
12-CELL
6-CELL
Figure 1. DC2064A Size 5.5" × 12.2"
3dc2064afa
DEMO MANUAL DC2064A
operating principle
Quick start proceDure
Operation of the LTC6803-2 is detailed in the LTC6803-2 data sheet and the operation of the DC2064A GUI is similar to the DC1652A GUI except additional functionality was added to control the LTC3300-1 balancing devices. Refer to the Quick Start Guide for the DC1652B for operation of the LTC6803-2 GUI. The DC2064A has a two window GUI, one window based on the DC1652A GUI to control the LTC6803-2 with a tab to control the LTC3300-1 for battery balancing and the second window to display the status of the LTC3300-1 based on the command and status registers read from the LTC3300-1.
The LTC3300-1 active balancer is a power stage control IC. The LTC3300-1 does not have a balancer algorithm built into it. The determination of the balancing times and directions are performed at a system level and conveyed to the LTC3300-1 through its SPI interface. The LTC3300-1 only accepts battery charge or discharge commands.
Charge is transferred to/from a cell (battery) from/to the stack, a series connection of adjacent cells, through a flyback converter that is operating in boundary mode.
During discharge of a cell, the current in the primary of a coupled inductor transformer with a turns ratio of 1:2, ramps up to 6.25A at which point the primary switch turns off. The charge in the primary inductor is transferred to the secondary inductor which is connected across the 12-cell pack. This pack current then passes through the series connected cells thus distributing the charge equally across each cell. When charging a cell, the current, in the secondary of the coupled inductor transformer, ramps up to 3.125A at which point the secondary switch turns off. The charge in the secondary inductor is transferred to the primary inductor which is connected across the cell. The secondary current is drawn from the series connected cells thus removing charge equally across each cell. The efficiency through the flyback converter is ≈92%.
The demonstration circuit is set up per Figure 29 to evaluate the performance of the DC2064A bidirectional cell balancer using the LTC3300-1.
Caution: BOT6_TS and TOP6_TS turrets must not be al-lowed to float and must be connected to their respective top of stack-battery terminal.
Using short twisted-pair leads for any power connec-tions, refer to Figure 29 for the proper measurement and equipment setup. The DC2064A will support a system of 4 to 12 batteries.
Recommended Cell Connection Sequence
The recommended cell connection sequence is to connect the V– connection first followed by connecting cells 1 through cell 12. Disconnection of the cells should follow this sequence in the reverse order with the V– connection being removed last. Connecting the V– connection first and removing last is recommended because the V– connection is the ground reference for the circuitry within the demo board. After connecting the V–, all other cell connection sequence is less critical as long as the cell circuit capacitances are matched as they are in the demo board.
Following the recommended cell connection removes the possibility of excessive voltage on any of the lower cells due to an imbalance in cell circuit capacitance.
Follow the procedure outlined in the DC1835A Quick Start Guide for general use of the modified LTC6803-2 GUI window. The 4-bit board ID code that is set by the A0 through A3 jumpers on the DC2064A must match the board Address box in the LTC6803-2 GUI window shown in Figure 2 for each board in the system.
Figure 2. Board Address Box
4dc2064afa
DEMO MANUAL DC2064A
The Voltage Comparator box must be turned off and the VREF must remain on during balancing. Set window by using the Up/Down arrows to the right of the box. See Figure 3.
Quick start proceDure
Figure 4. VOV and VUV text boxes
Figure 5. Write Configuration Box
Figure 3. Voltage Comparator Box
The DC2064A GUI periodically checks for OV and UV measured on the cells when balancing. To avoid the program from suspending balancing from an OV or UV measurement during normal operation, the OV and UV values must be entered in the VOV and VUV text boxes on the LTC6803-2 tab shown in Figure 4.
Once this is done, Click the WRITE CONFIG button and verify that the configuration was set correctly by clicking the READ CONFIG.
Click the START CELL VOLT button followed by the READ CELL VOLT to verify that the batteries are connected and that the LTC6803-2 can read the battery voltages.
Figure 6. Start Cell Voltage Read Box
To access the LTC3300-1 screen, click on the LTC3300-1 tab in the upper left of the LTC6803-2 GUI window.
Figure 7. LTC3300-1 Screen Select Box
Within this window you can manually select which cells are to be discharged by clicking the cell’s DISCHARGE button and which cells are to be charged by clicking the cell’s CHARGE button.
Figure 8. Balance Mode Select Boxes
To write this configuration, the WRITE button followed by the SEND button must be clicked. To enable the balancers, the EXECUTE button followed by the SEND button must be clicked. To pause the cell balancers, the SUSPEND button is clicked followed by clicking the SEND button. This will turn off all balancers until the EXECUTE button is clicked followed by clicking the SEND button. This will resume the previous settings of the cell charge/discharge settings.
5dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 9. Write/Execute Command Box
To change any of the settings “on the fly”, a new charge/discharge setting is entered using the respective CHARGE and DISCHARGE buttons followed by clicking the WRITE button followed by the SEND button and then the EXECUTE button followed by the SEND button. To disable any cell from operating, the cell’s NONE button must be clicked in the balance mode box followed by clicking the WRITE button followed by the SEND button and then the EXECUTE button followed by the SEND button.
The LTC3300-1 GUI allows the user to program the balancer to charge or discharge each cell for a specific amount of time. The LTC3300-1 is a power stage control IC. The determination of the balancing times and directions are done at the System level and conveyed to the LTC3300-1 through its SPI communications port. In order to perform a timed balance, the TIMED BALANCE check shown in Figure 10 must be selected to have access to the timed balance controls as shown in Figure 27.
Figure 10. TIMED BALANCE Check Box
To do this, select the DISCHARGE or CHARGE button for the desired cell, then enter the time in seconds into the cells “BALANCE TIME” text box. Press the enter key on the key board or select another button in the GUI to load the time. When all the desired balance actions and times have been entered, select the “Balance Cells” START but-ton to start the balancing sequence.
Figure 11. Balance Cells Start Box
The START button will display PAUSE. The balancing algorithm will first turn off all cells, then set all cells to be balanced. The cells will run until the first cell(s) have elapsed their balance time. At this time all cell balancing is suspended, the completed cell’s balancing action is set to “None”, the remaining times to balance are recalculated, then the remaining cells continue to balance until the next cell(s) have completed. This sequence continues until all of the balance times have elapsed.
Selecting the PAUSE button while the balancer is running, will shut off the active cell and pause the timer. The START button now displays CONTINUE. Selecting the CONTINUE button again will start the active cell balancing and continue the timer. After the last cell has completed balancing, all the cells are turned off. The START button will again display START. Selecting the RESET button will reset all the cell actions and times to the previous entered settings.
The LTC3300 STATUS window displays the status of all LTC3300-1 ICs in the system. This GUI is updated every time the LTC3300-1 status or command registers are read. When the balancer timer is running, the command register is read after each execute command is sent.
6dc2064afa
DEMO MANUAL DC2064A
Quick start proceDureCell Balancer Efficiency Measurements:
Figure 30 shows the proper connections for measuring the efficiency of a cell balancer. The secondary of the cell balancer connects to the top of stack. This connection needs to be to an isolated power source through a current sensing resistor (0.10Ω). Cells 1 through 6 are connected to the BOT6_TS turret with its return path the V– turret while Cells 7 through 12 are connected to the TOP6_TS turret with its return path the C6 turret. The primary side connections of the cell balancers are connected to a string of batteries that simulate the battery stack. Cell 1 is a 2-wire connection that connects the positive node, through a current sensing resistor (0.01Ω), to the C1 turret, and the negative node to the V– turret. Remote sense connections for power sources with remote sensing capabilities should be connected to the C1 and V– respectively. All other connections of the simulated string of batteries connect their positive node, through a current sensing resistor (0.01Ω), to respective turrets. Cell voltage measurements should be made across the C(x) and C(x – 1) turrets of the respective cells. Stack voltage measurements should be made at the BOT6_TS and TOP6_TS turrets and their return path turret.
To calculate cell balancer efficiency use the expressions below:
Cells 1-6
Charge Mode
Efficiency1 = Vm1 • Vm2 •10
Vm3 • Vm4•100%
Discharge Mode
Efficiency1 = Vm3 • Vm4
Vm1 • Vm2 •10•100%
Cells 7-12
Charge Mode
Efficiency11 = Vm5 • Vm6 •10
Vm7 • Vm8•100%
Discharge Mode
Efficiency11 = Vm7 • Vm8
Vm5 • Vm6 •10•100%
Cell Balancer Performance Measurements:
Table 2 through Table 5 present the typical operational data for a 12-cell and 6-cell balancer in both Discharge and Charge modes. The cell voltages were 3.6V and measure-ments of Cell Current, Stack Current, Operating Frequency were taken and transfer Efficiency was calculated from the data. Figure 12 through Figure 15 are actual in circuit waveforms taken on Cell 1 and Cell 7 while operating in both modes. The waveforms present voltage on the pri-mary side and secondary side MOSFET’s drain to source voltage and the primary side and secondary side current sense inputs to the LTC3300-1.
Figures 16 through 19 are cell and stack currents taken over a range of cell voltages from 2.6V to 4.0V. The RTONP and RTONS resistors for these graphs were set for 2.6V cell voltage operation. All cells were set to the cell voltage under test. The slight negative slope in current at higher voltages is due to the increased operating frequency and the circuit delays and dead time becoming a higher percent-age of the operating period.
7dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure12 Cell Discharge
Table 2. Typical 12 Cell Discharge DataCell I (A) Stack I (A) Frequency (kHz) Efficiency
2.444 0.188 127.7 92.21%
Figure 12. 12 Cell Discharge Waveforms
12 Cell Charge
Table 3. Typical 12 Cell Charge DataCell I (A) Stack I (A) Frequency (kHz) Efficiency
2.601 0.237 149.1 91.71%
Figure 13. 12 Cell Charge Waveforms
6 Cell Discharge
Table 4. Typical 6 Cell Discharge DataCell I (A) Stack I (A) Frequency (kHz) Efficiency
2.448 0.277 126.1 92.33%
Figure 14. 6 Cell Discharge Waveforms
6 Cell Charge
Table 5. Typical 6 Cell Charge DataCell I (A) Stack I (A) Frequency (KHz) Efficiency
2.219 0.399 133.1 92.72%
Figure 15. 6 Cell Charge Waveforms
8dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 16. Cell Discharge Current
CELL VOLTAGE (V)2.6
CELL
DIS
CHAR
GE C
URRE
NT (A
)
3.0
3.5
4.0
3.2 3.6
2.5
2.0
2.8 3.0 3.4 3.8 4.0
1.5
1.0
12-CELL
6-CELL
CELL VOLTAGE (V)2.6
STAC
K DI
SCHA
RGE
CURR
ENT
(A) 0.45
3.2
0.30
0.20
2.8 3.0 3.4
0.15
0.10
0.50
0.40
0.35
0.25
3.6 3.8 4.0
12-CELL
6-CELL
Figure 17. Stack Discharge Current
CELL VOLTAGE (V)2.6
CELL
CHA
RGE
CURR
ENT
(A)
3.0
3.5
4.0
3.2 3.6
2.5
2.0
2.8 3.0 3.4 3.8 4.0
1.5
1.0
12-CELL
6-CELL
Figure 18. Cell Charge Current
CELL VOLTAGE (V)2.6
STAC
K CH
ARGE
CUR
RENT
(A)
0.45
3.2
0.30
0.20
2.8 3.0 3.4
0.15
0.10
0.50
0.40
0.35
0.25
3.6 3.8 4.0
12-CELL
6-CELL
Figure 19. Stack Charge Current
9dc2064afa
DEMO MANUAL DC2064A
Quick start proceDureTwo Board Setup and Operation:
As a result of communication latency to the PC, the system only supports two series DC2064A boards
When connecting two DC2064A boards together, the in-terface cables must be connected in sequence as shown in Figure 20 to avoid large inrush currents. The DC590B
must be connected to the PC USB port and the bottom DC2064A board first and then the top DC2064A board may be connected.
The 24 cells should be interconnected to allow balancing between the two 12-cell stacks, as shown in Figure 21.
Figure 20. Two DC2064A SPI Connection Sequence
DC2064A DC2064A
10dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 21. 24 Cell Interconnected Stacks
11dc2064afa
DEMO MANUAL DC2064A
Quick start proceDureOn the LTC6803-2 tab on the DC2064A GUI, the Number of Boards in the System drop down box will need to be changed to 2. Make sure the address for each board in the Hex Address box matches the address set by the A0 to A3 jumpers on the respective DC2064A board. The board selection buttons on the bottom left side of the GUI highlight which board is selected in maroon, as shown and the set hexadecimal address is displayed under each board. To change the hexadecimal address on the GUI, select the board to change by clicking on the appropriate board selection number and then select the correct ad-dress in the Hex Address Box.
Figure 22. DC2064A GUI Board Selection Controls
To set up the charge and discharge actions for each LTC3300, the appropriate board must be selected first and then the commands for each LTC3300-1 can be selected and written to the LTC3300-1 tab. When all the desired actions are selected and written to the four LTC3300-1 ICs, then a single execute command will send an execute command to both boards simultaneously provided the Broadcast Execute/Suspend button is selected as shown in Figure 23.
Figure 23. Broadcast Execute/Suspend Tab
Additional Circuitry
Additional circuitry has been added to increase the robust-ness of the design for fault insertions.
Cell 6 Wire Disconnection
A 10A 200V Schottky diode has been added for a high current path when the connection between battery cells is broken when a battery stack load is present. The 200V reverse voltage rating of the diode was selected to mini-mize the reverse leakage current at a battery voltage of 4.2V. The 10A current rating was selected for its low forward voltage drop which will minimize the current in the parallel diode within the LTC3300-1 as well as surviving the fusing current of the 7A fuses on the DC2064A.
Two overvoltage detection circuits have been added to the design that will sense an overvoltage condition on Cell 6 and Cell 7 when a disconnection of the Cell 6 wire con-nection between battery Cell 6+ and battery Cell 7– of the battery stack occurs. When Cell 6 is being discharged and other cells controlled by the U1, the lower LTC3300-1, and U2, the upper LTC3300-1 are operational, an overvoltage can occur on Cell 7. The overvoltage on Cell 7 will shut down the operation of Cell 7-Cell 12 but Cell 1-Cell 6 will continue to operate. The overvoltage sensing circuit Q15, D21, D23 and R51 will turn off the operations of Cell 1-Cell 6 through the internal overvoltage protection circuit within the LTC3300-1 of U1.
A similar event occurs when Cell 6 is operating in the Charge Mode and the Cell 6 connection from the board to the battery is lost. The overvoltage on Cell 6 will shut down the operation of Cell 1-Cell 6 but Cell 7- Cell 12 will continue to operate. The overvoltage sensing circuit Q16, D22, D24 and R52 will turn off the operations of Cell 7-Cell 12 through the internal overvoltage protection circuit within the LTC3300-1 of U2.
12dc2064afa
DEMO MANUAL DC2064A
Quick start proceDureCell Bypass Capacitors
The DC2064A contains bypass capacitors from the cell connections and the stack connections. These capacitors have a dual function of smoothing the high triangular current wave before the current travels down the inter-connecting wires to the cells and they also help balance the voltage between cells when hot-plugging cells in a random order. The RMS current rating of these capaci-tors is a critical parameter for these bypass capacitors as well as their physical size. These high triangular current waveforms produce an RMS current that passes through the capacitors which result in an internal heat rise. Larger physical size MLCC capacitors have higher RMS current rating due to their greater surface area to dissipate the heat rise. The capacitance of MLCC capacitors decreases with applied voltage and this must be taken into account when selecting the capacitance value. If a connection is lost during balancing, the differential voltage seen by the LTC3300-1 power circuit on each side of the break may increase or decrease in depending on whether the power stage is charging or discharging and where the break occurred. The worst-case scenario is when the balanc-ers on each side of the break are active and balancing in opposite directions. Here the differential voltage will increase rapidly on one side and decrease rapidly on the
other. The LTC3300-1 contains an overvoltage protection comparator which monitors the cell voltage and will shut down all balancers before the differential voltage on any cell input reaches the maximum absolute voltage rating.
Each cell node must have an equivalent capacitance across it to prevent an overvoltage condition when randomly con-necting cells to the LTC3300-1 battery balancer circuit. In addition to the smoothing capacitors across each balancer power circuit, there are capacitors across the Cx pins of the LTC3300-1 to reduce high frequency noise on these pins and capacitors across adjacent cells to act as a reservoir of charge for the cell’s MOSFET gate driver circuits. These reservoir capacitors must also be of equal value to maintain the balancing of voltage and a capacitor of 2x the value of the reservoir capacitor must be connected between C1 and V– of the lowest LTC3300-1 and from the top cell to the cell below it to insure an equal voltage across all cells when the battery stack is initially connected. Figures 25 and 26 detail these capacitor connections and their values. The reservoir capacitors must be large compared to the capacitors across the Cx pins to force the MOSFET gate charging current to flow through the reservoir capacitors. An effective 10:1 ratio between these cell capacitors was selected when considering that a capacitor across two cells would result in a 5:1 ratio.
13dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 24. DC2064A LTC6803-2 Setup Screen
14dc2064afa
DEMO MANUAL DC2064A
Figure 25. Bypass Capacitors on Lowest LTC3300-1
Figure 26. Bypass Capacitors on the Top LTC3300-1
Quick start proceDure
DC2064a F25
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
I2P
G4P
I4P
G3P
I3P
G2P
I2P
C1
C2
C3
C4
C5
C6
G5P
I5P
G6P
I6P
36
3738394041
35
3433
3231
30
29
2827
26
25
2019 21 22 23 24
C6K1µF16V0603
C5K1µF16V0603C4K1µF16V0603C3K1µF16V0603
C2K1µF16V0603
C6 G6P I6PBOOST+BOOST–BOOST
V– C1G1PI1PWDT
G1PI1PWDTA
SDO
C94.7µF16V0805
C114.7µF16V0805
C124.7µF16V0805
C104.7µF16V0805
C1K1µF16V0603
C2310µF10V0805
C144.7µF16V0805
42
C30.1µF16V0402
C40.22µF16V0603
CMMSH2-40R5 R6
6.81
D1D2CMMSH2-40
1
1
2
2
0 OPT
DC2064a F26
C5
G5P
I5P
C4
G4P
I4P
C3
G3P
I3P
C2
G2P
I2P
G10P
I10P
G9P
I9P
G8P
I8P
C7
C5
C8
C9
C10
C11
C12
G11P
I11P
G12P
I12P
36
3738394041
35
3433
3231
30
29
2827
26
25
2019 21 22 23 24
C12K1µF16V0603
C11K1µF16V0603C10K1µF16V0603C9K1µF16V0603
C8K1µF16V0603
C6 G6P I6PBOOST+BOOST–BOOST
V– C1G1PI1PWDT
G7PI7P
C6
WDTC
SDO
C154.7µF16V0805
C174.7µF16V0805
C184.7µF16V0805
C164.7µF16V0805
C2410µF10V0805
C7K1µF16V0603
C204.7µF16V0805
42
C70.1µF16V0402
C80.22µF16V0603
CMMSH2-40R9 R10
6.81
D3D4CMMSH2-40
1
1
2
2
0 OPT
C134.7µF16V0805
15dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 27. DC2064A LTC3300-1 Setup Screen with Timed Balance Controls
Figure 28. DC2064A LTC3300-1 Status GUI Screen
16dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 29. Proper Measurement Equipment Setup for Bidirectional Cell Balancer
Note: All connections from equipment should be Kelvin connected directly to the Board Pins which they are connected to on this diagram and any input, or output, leads should be twisted pair, where possible.
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
17dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
Figure 30. Proper Equipment Setup for Cell Balancer Efficiency Measurements
18dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 31. Proper Equipment Setup for Minimum Number of Cell Efficiency Measurements
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
19dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 32. Configuring the Board for Six Batteries
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
20dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 33. Configuring the Board for Seven Batteries
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
21dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 34. Configuring the Board for Eight Batteries
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
22dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 35. Configuring the Board for Nine Batteries
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
23dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 36. Configuring the Board for Ten Batteries
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
24dc2064afa
DEMO MANUAL DC2064A
Quick start proceDure
Figure 37. Configuring the Board for Eleven Batteries
System Setup Requirements:LFP or Li-Ion Battery ≥ 10AHr Internal Resistance < 30mΩ
Recommended Battery Simulator: Power Supply 2V to 5.0 V ±10AInterconnect Resistance < 25mΩ
25dc2064afa
DEMO MANUAL DC2064A
schematic Diagrams1 1
AA
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
OPT
OPT
OPT
OPT
OPT
OPTOP
TOP
TOP
T
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
2.5V
- 4.5VN-
1
BATT
ERY
CELL
VOL
TAGE
S
2.5A
NC -
C -
BOT6
_TS
BOT6
_TS
BOT6
_TS
V-
V-V- V-
V-
V-
C1
BOT6
_TS
BOT6
_TS
BOT6
_TS
C4
C1
C5C6
C5
C3
C2
C4 C3
C2
G3P
I3P
G3S
I3S
C3
G2P I2P
G2S
I2S
C2
G1P
I1P
G1S
I1S
C1
G6P
I6P
G6S
I6S
C6
G5P
I5P
G5S
I5S
C5
G4P
I4P
G4S
I4S
C4
V-
BOT6
_TS
REVI
SION
HIS
TORY
DESC
RIPT
ION
DATE
APPR
OVED
ECO
REV
J.DRE
WPR
ODUC
TION
FAB
-1
1 - 11
- 13
REVI
SION
HIS
TORY
DESC
RIPT
ION
DATE
APPR
OVED
ECO
REV
J.DRE
WPR
ODUC
TION
FAB
-1
1 - 11
- 13
REVI
SION
HIS
TORY
DESC
RIPT
ION
DATE
APPR
OVED
ECO
REV
J.DRE
WPR
ODUC
TION
FAB
-1
1 - 11
- 13
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
15
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
15
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
15
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
C2H
470p
FC2
H47
0pF
D5A
DFLS
260
D5A
DFLS
260
21
RS6B
0.016
RS6B
0.016
21
43
R1F
5.1R1F
5.1R3F
5.1R3F
5.1
C2C
100u
F
1210
6.3V
C2C
100u
F
1210
6.3V
T5
WUR
TH-7
5031
2504
T5
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
Q6A
SiR8
82DP
Q6A
SiR8
82DP
6
4
23
18
5
7
C1A
100u
F
1210
6.3V
C1A
100u
F
1210
6.3V
C3C
100u
F
1210
6.3V
C3C
100u
F
1210
6.3V
R3A
20 1206
R3A
20 1206
D1A
DFLS
260
D1A
DFLS
260
21
C6E 47
0pF
100V
0603
C6E 47
0pF
100V
0603
RS2A
0.008
RS2A
0.008
21
43
R5B
18 1206
R5B
18 1206
Q5A
SiR8
82DP
Q5A
SiR8
82DP
6
4
23
18
5
7
RS5A
0.008
RS5A
0.008
21
43
C3T
2.2uF
1210
100V
C3T
2.2uF
1210
100V
Q1B
SiS8
92DN
Q1B
SiS8
92DN
6
4
23
18
5
7D5
FSB
R10U
200P
5D5
FSB
R10U
200P
5
213
D3A
DFLS
260
D3A
DFLS
260
21
D4C
CMOS
H-4E
D4C
CMOS
H-4E
21
T2
WUR
TH-7
5031
2504
T2
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
C3E
470p
F
100V 0603
C3E
470p
F
100V 0603
Q3B
SiS8
92DN
Q3B
SiS8
92DN
6
4
23
18
5
7
D6A
DFLS
260
D6A
DFLS
260
21
RS2B
0.016
RS2B
0.016
21
43 C1F
470p
F10
0V06
03C1F
470p
F10
0V06
03
R3C
5.1R3C
5.1
Q2A
SiR8
82DPQ2
ASi
R882
DP
6
4
23
18
5
7
C3S
2.2uF
1210
100V
C3S
2.2uF
1210
100V
C6A
100u
F12
106.3
V
C6A
100u
F12
106.3
V
C5E
470p
F10
0V06
03
C5E
470p
F10
0V06
03
D5C
CMOS
H-4E
D5C
CMOS
H-4E
21
C5F
470p
F10
0V06
03C5F
470p
F10
0V06
03
D3C
CMOS
H-4E
D3C
CMOS
H-4E
21
R3G
20R3G
20
C2E
470p
F
100V
0603
C2E
470p
F
100V
0603
T4
WUR
TH-7
5031
2504
T4
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
Q6B
SiS8
92DN
Q6B
SiS8
92DN
6
4
23
18
5
7
C4G
2.2nF
C4G
2.2nF
C6F
470p
F10
0V06
03C6F
470p
F10
0V06
03
R4G
20R4G
20
C1T
2.2uF
1210
100VC1
T2.2
uF
1210
100V
C5T
2.2uF
1210
100V
C5T
2.2uF
1210
100V
R2F
5.1R2F
5.1
R4F
5.1R4F
5.1
D2A
DFLS
260
D2A
DFLS
260
21
R1B
18 1206
R1B
18 1206
C6R
2.2uF
1210
100V
C6R
2.2uF
1210
100V
C5R
2.2uF
1210
100V
C5R
2.2uF
1210
100V
D3B
DFLS
1100
D3B
DFLS
1100
21
Q5B
SiS8
92DN
Q5B
SiS8
92DN
6
4
23
18
5
7
C5A
100u
F
1210
6.3V
C5A
100u
F
1210
6.3V
C5B
100u
F
1210
6.3V
C5B
100u
F
1210
6.3V
C1C
100u
F
1210
6.3V
C1C
100u
F
1210
6.3V
D3F
SBR1
0U20
0P5
D3F
SBR1
0U20
0P5
213
R3H
20R3H
20
C2A
100u
F
1210
6.3V
C2A
100u
F
1210
6.3V
Q2B
SiS8
92DN
Q2B
SiS8
92DN
6
4
23
18
5
7
R6B
18 1206
R6B
18 1206
D5B
DFLS
1100
D5B
DFLS
1100
21
C2F
470p
F10
0V06
03C2F
470p
F10
0V06
03
D1B
DFLS
1100
D1B
DFLS
1100
21
RS4B
0.016
RS4B
0.016
21
43
R2C
5.1R2C
5.1
C4R
2.2uF
1210
100V
C4R
2.2uF
1210
100V
E8 BOT6
_TS
E8 BOT6
_TS
R4C
5.1R4C
5.1
C3A
100u
F
1210
6.3V
C3A
100u
F
1210
6.3V
T3
WUR
TH-7
5031
2504
T3
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
C3B
100u
F
1210
6.3V
C3B
100u
F
1210
6.3V
R4H 20R4H 20
C3G
2.2nF
C3G
2.2nF
D1C
CMOS
H-4E
D1C
CMOS
H-4E
21
C4H
470p
FC4
H47
0pF
D6B
DFLS
1100D6
BDF
LS11
00
21
C1R
2.2uF
1210
100V
C1R
2.2uF
1210
100V
F13
7A 1210
F13
7A 1210
C6C
100u
F
1210
6.3V
C6C
100u
F
1210
6.3V
R1C
5.1R1C
5.1
C1S
2.2uF
1210
100V
C1S
2.2uF
1210
100V
R2B
18 1206
R2B
18 1206
D2F
SBR1
0U20
0P5
D2F
SBR1
0U20
0P5
213
R4A 20
1206
R4A 20
1206
C4T
2.2uF
1210 100V
C4T
2.2uF
1210 100V
C3H
470p
FC3
H47
0pF C2
S2.2
uF
1210
100V
C2S
2.2uF
1210
100V
C4S
2.2uF
1210
100V
C4S
2.2uF
1210
100V
C5S
2.2uF
1210
100V
C5S
2.2uF
1210
100V
C2R
2.2uF
1210
100V
C2R
2.2uF
1210
100V
J2 1793
1300
0_SC
J2 1793
1300
0_SC
BO
T6_T
S1
BO
T6_T
S2
D2B
DFLS
1100
D2B
DFLS
1100
21
D4A
DFLS
260
D4A
DFLS
260
21
D1F
SBR1
0U20
0P5
D1F
SBR1
0U20
0P5
213
C2T
2.2uF
1210
100V
C2T
2.2uF
1210
100V
C4C
100u
F
1210
6.3V
C4C
100u
F
1210
6.3V
C3F
470p
F10
0V06
03C3F
470p
F10
0V06
03
C3R
2.2uF
1210
100V
C3R
2.2uF
1210
100V
R1G 20R1G 20
R4B
18 1206
R4B
18 1206
Q4A
SiR8
82DP
Q4A
SiR8
82DP
6
4
23
18
5
7
RS4A
0.008
RS4A
0.008
21
43
R1A
20 1206
R1A
20 1206
C6B
100u
F
1210
6.3V
C6B
100u
F
1210
6.3V
T6
WUR
TH-7
5031
2504
T6
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
C5G
2.2nF
C5G
2.2nF
D6F
SBR1
0U20
0P5
D6F
SBR1
0U20
0P5
213
R1H
20R1H
20
R5G
20R5G
20
C4E
470p
F10
0V06
03
C4E
470p
F10
0V06
03
R3B
18 1206
R3B
18 1206
R6G 20R6G 20
C4F
470p
F10
0V06
03C4F
470p
F10
0V06
03
C1G
2.2nF
C1G
2.2nF
C6T
2.2uF
1210
100V
C6T
2.2uF
1210
100V
R6A
20 1206
R6A
20 1206
R6F
5.1R6F
5.1
C6G
2.2nF
C6G
2.2nF
C6S
2.2uF
1210
100V
C6S
2.2uF
1210
100V
R6H 20R6H 20
C1B
100u
F
1210
6.3V
C1B
100u
F
1210
6.3V
C1H
470p
FC1
H47
0pF
C4B
100u
F
1210
6.3V
C4B
100u
F
1210
6.3V
RS5B
0.016
RS5B
0.016
21
43
Q4B
SiS8
92DN
Q4B
SiS8
92DN
6
4
23
18
5
7
C4A
100u
F
1210
6.3V
C4A
100u
F
1210
6.3V
R2G
20R2G
20
RS1A
0.008
RS1A
0.008
21
43
T1
WUR
TH-7
5031
2504
T1
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
D4F
SBR1
0U20
0P5
D4F
SBR1
0U20
0P5
213
D2C
CMOS
H-4E
D2C
CMOS
H-4E
21
RS3B
0.016
RS3B
0.016
21
43
R5F
5.1R5F
5.1
D4B
DFLS
1100D4B
DFLS
1100
21
R5H
20R5H
20
C6H
470p
FC6
H47
0pF
R2A
20 1206
R2A
20 1206
C5H
470p
FC5
H47
0pF
R2H
20R2H
20
R6C
5.1R6C
5.1
RS3A
0.008
RS3A
0.008
21
43
C2G
2.2nF
C2G
2.2nF
C2B
100u
F
1210
6.3V
C2B
100u
F
1210
6.3V
R5A
20 1206
R5A
20 1206
Q1A
SiR8
82DPQ1
ASi
R882
DP
6
4
23
18
5
7
RS1B
0.016
RS1B
0.016
21
43
C1E
470p
F10
0V06
03
C1E
470p
F10
0V06
03
D6C
CMOS
H-4E
D6C
CMOS
H-4E
21
RS6A
0.008
RS6A
0.008
21
43
Q3A
SiR8
82DP
Q3A
SiR8
82DP
64
23
18
5
7
C5C
100u
F
1210
6.3V
C5C
100u
F
1210
6.3V R5
C
5.1R5C
5.1
Figu
re 3
8. S
chem
atic
Dia
gram
Pag
e 1
26dc2064afa
DEMO MANUAL DC2064A
schematic Diagrams
Figu
re 3
9. S
chem
atic
Dia
gram
Pag
e 2
1 1
AA
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
PLAC
E RC
CLO
SE TO
LTC3
300
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
OPT
C -
CN 2.5
A
BATT
ERY
CELL
VOL
TAGE
SN-
1-
2.5V
- 4.5V
TOP6
_TS
C6 C6
TOP6
_TS
C6
TOP6
_TS
C6
TOP6
_TS
TOP6
_TS
TOP6
_TS
C6
C6
C7
C8
C10
C9
C8
C12
C11 C1
0 C9
C7
C11
G10P
C9
G12P
G7P
G9P
I12S
I8S
I9P
G7S
I7P
I10P
I8P
G8P
G11P
C6
I11P
C8
G9S
I7S
I12P
I10S
G10S
C11
G8S
I11S
I9S
C7
G12S
G11S
C10
TOP6
_TS
C12
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
25
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
25
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
25
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
Q8B
SiS8
92DN
Q8B
SiS8
92DN
6
4
23
18
5
7
R8H
20R8H
20
C9B
100u
F
1210
6.3V
C9B
100u
F
1210
6.3V
R9F
5.1R9F
5.1
C12C
100u
F
1210
6.3V
C12C
100u
F
1210
6.3V
R11B
18 1206
R11B
18 1206
R7H
20R7H
20
D7F
SBR1
0U20
0P5
D7F
SBR1
0U20
0P5
213
RS7B
0.016
RS7B
0.016
21
43
D8A
DFLS
260
D8A
DFLS
260
21
RS11
A0.0
08RS
11A
0.008
21
43
Q7B
SiS8
92DN
Q7B
SiS8
92DN
6
4
23
18
5
7
C8A
100u
F
1210
6.3V
C8A
100u
F
1210
6.3V
D9F
SBR1
0U20
0P5
D9F
SBR1
0U20
0P5
213
C8C
100u
F
1210
6.3V
C8C
100u
F
1210
6.3V
T9
WUR
TH-7
5031
2504
T9
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
RS10
A0.0
08RS
10A
0.008
21
43
C8G
2.2nF
C8G
2.2nF
C12R
2.2uF
1210
100V
C12R
2.2uF
1210
100V
RS11
B0.0
16RS
11B
0.016
21
43
R9G 20R9G 20
C10E
470p
F10
0V06
03
C10E
470p
F10
0V06
03
R8F
5.1R8F
5.1
R10B
18 1206
R10B
18 1206
C10C
100u
F
1210
6.3V
C10C
100u
F
1210
6.3V
R12H 20R12H 20
D11A
DFLS
260
D11A
DFLS
260
21
D10C
CMOS
H-4E
D10C
CMOS
H-4E
21
J3 1793
1300
0_SC
J3 1793
1300
0_SC
TOP
6_TS
1TO
P6_
TS2
C7F
470p
F10
0V06
03C7F
470p
F10
0V06
03
D9C
CMOS
H-4E
D9C
CMOS
H-4E
21
C12G
2.2nF
C12G
2.2nF
T8
WUR
TH-7
5031
2504
T8
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
Q9A
SiR8
82DPQ9
ASi
R882
DP
6
4
23
18
5
7
C7S
2.2uF
1210
100V
C7S
2.2uF
1210
100V
D11C
CMOS
H-4E
D11C
CMOS
H-4E
21
R12B
18 1206
R12B
18 1206
C12A
100u
F12
106.3
V
C12A
100u
F12
106.3
V
Q7A
SiR8
82DPQ7A
SiR8
82DP
6
4
23
18
5
7
Q11B
SiS8
92DN
Q11B
SiS8
92DN
6
4
23
18
5
7
RS12
A0.0
08RS
12A
0.008
21
43
F14
7A 1210
F14
7A 1210
R10H 20R10H 20
D8C
CMOS
H-4E
D8C
CMOS
H-4E
21
D7C
CMOS
H-4E
D7C
CMOS
H-4E
21E1
5
TOP6
_TS
E15
TOP6
_TS
D12F
SBR1
0U20
0P5
D12F
SBR1
0U20
0P5
213
D11B
DFLS
1100
D11B
DFLS
1100
21
C10R
2.2uF
1210
100V
C10R
2.2uF
1210
100V
D7B
DFLS
1100
D7B
DFLS
1100
21
C7G
2.2nF
C7G
2.2nF
RS12
B0.0
16RS
12B
0.016
21
43
R8C
5.1R8C
5.1
RS8A
0.008
RS8A
0.008
21
43
T12
WUR
TH-7
5031
2504
T12
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
C11A
100u
F12
10 6.3V
C11A
100u
F12
10 6.3V
C9S
2.2uF
1210
100V
C9S
2.2uF
1210
100V
C11H
470p
FC1
1H47
0pF
C10S
2.2uF
1210
100V
C10S
2.2uF
1210
100V
C12T
2.2uF
1210
100V
C12T
2.2uF
1210
100V
RS8B
0.016
RS8B
0.016
21
43
R11F
5.1R11F
5.1
C12S
2.2uF
1210
100V
C12S
2.2uF
1210
100V
R11A 20 1206
R11A 20 1206
C11S
2.2uF
1210
100V
C11S
2.2uF
1210
100V
R8B
18 1206
R8B
18 1206
Q8A
SiR8
82DPQ8A
SiR8
82DP
6
4
23
18
5
7
D10F
SBR1
0U20
0P5
D10F
SBR1
0U20
0P5
213
R7B
18 1206
R7B
18 1206
Q10A
SiR8
82DP
Q10A
SiR8
82DP
6
4
23
18
5
7
C9C
100u
F
1210
6.3V
C9C
100u
F
1210
6.3V
D12C
CMOS
H-4E
D12C
CMOS
H-4E
21
C8T
2.2uF
1210
100VC8T
2.2uF
1210
100V
R11C 5.1R11C 5.1
R8G
20R8G
20
C11R
2.2uF
1210
100V
C11R
2.2uF
1210
100V
C10F
470p
F10
0V06
03
C10F
470p
F10
0V06
03
R7A
20 1206
R7A
20 1206
C8R
2.2uF
1210
100V
C8R
2.2uF
1210
100V
C12E 47
0pF
100V
0603
C12E 47
0pF
100V
0603
R7C
5.1R7C
5.1
R9B
18 1206
R9B
18 1206
D10B
DFLS
1100
D10B
DFLS
1100
21
C11T
2.2uF
1210
100V
C11T
2.2uF
1210
100V
D12A
DFLS
260
D12A
DFLS
260
21
R10F 5.1R10F 5.1
C11C
100u
F
1210
6.3V
C11C
100u
F
1210
6.3V
RS7A
0.008
RS7A
0.008
21
43R7
G 20R7G 20
C12B
100u
F
1210
6.3V
C12B
100u
F
1210
6.3V
R9C
5.1R9C
5.1
C12H
470p
FC1
2H47
0pF
C9F
470p
F10
0V06
03C9F
470p
F10
0V06
03
C11B
100u
F
1210
6.3V
C11B
100u
F
1210
6.3V
D9B
DFLS
1100
D9B
DFLS
1100
21
Q9B
SiS8
92DN
Q9B
SiS8
92DN
6
4
23
18
5
7
Q12B
SiS8
92DN
Q12B
SiS8
92DN
6
4
23
18
5
7
RS9B
0.016
RS9B
0.016
21
43
Q10B
SiS8
92DN
Q10B
SiS8
92DN
6
4
23
18
5
7
C9H
470p
FC9
H47
0pF
Q11A
SiR8
82DPQ11A
SiR8
82DP
6
4
23
18
5
7
R10C
5.1R10C
5.1
C7T
2.2uF
1210
100VC7
T2.2
uF
1210
100V
R12A 20 1206
R12A 20 1206
C11E
470p
F10
0V06
03
C11E
470p
F10
0V06
03
D8F
SBR1
0U20
0P5
D8F
SBR1
0U20
0P5
213
Q12A
SiR8
82DP
Q12A
SiR8
82DP
6
4
23
18
5
7
C7H
470p
FC7
H47
0pF
C10H
470p
FC1
0H47
0pF
C8E
470p
F
100V
0603
C8E
470p
F
100V
0603D9
ADF
LS26
0D9
ADF
LS26
0
21
D7A
DFLS
260
D7A
DFLS
260
21
R9H
20R9H
20
R10G 20R10G 20
R12C 5.1R12C 5.1
C12F
470p
F10
0V06
03
C12F
470p
F10
0V06
03
C10T
2.2uF
1210
100V
C10T
2.2uF
1210
100V
C9E
470p
F
100V
0603
C9E
470p
F
100V
0603
C7A
100u
F
1210
6.3V
C7A
100u
F
1210
6.3V
R10A
20 1206
R10A
20 1206
C7B
100u
F
1210
6.3V
C7B
100u
F
1210
6.3V
C8F
470p
F10
0V06
03C8F
470p
F10
0V06
03
C7C
100u
F
1210
6.3V
C7C
100u
F
1210
6.3V
R12F
5.1R12F
5.1
C10G
2.2nF
C10G
2.2nF
C10A
100u
F12
106.3
V
C10A
100u
F12
106.3
V
R12G 20R12G 20
T10
WUR
TH-7
5031
2504
T10
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
R11H 20R11H 20
C8B
100u
F
1210
6.3V
C8B
100u
F
1210
6.3V
D10A
DFLS
260
D10A
DFLS
260
21
D8B
DFLS
1100
D8B
DFLS
1100
21
C8H
470p
FC8
H47
0pF
C9T
2.2uF
1210
100V
C9T
2.2uF
1210
100V
T11
WUR
TH-7
5031
2504
T11
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
C11G
2.2nF
C11G
2.2nF
C7E
470p
F10
0V06
03
C7E
470p
F10
0V06
03
C11F
470p
F10
0V06
03C11F
470p
F10
0V06
03
RS10
B0.0
16RS
10B
0.016
21
43
R8A
20 1206
R8A
20 1206
D11F
SBR1
0U20
0P5
D11F
SBR1
0U20
0P5
213
D12B
DFLS
1100
D12B
DFLS
1100
21
C9R
2.2uF
1210
100V
C9R
2.2uF
1210
100V
T7
WUR
TH-7
5031
2504
T7
WUR
TH-7
5031
2504
101 2 9
6 7 4 5
R11G 20R11G 20
C8S
2.2uF
1210
100V
C8S
2.2uF
1210
100V
RS9A
0.008
RS9A
0.008
21
43
C7R
2.2uF
1210
100V
C7R
2.2uF
1210
100V
C9G
2.2nF
C9G
2.2nF
C10B
100u
F
1210
6.3V
C10B
100u
F
1210
6.3V
R7F
5.1R7F
5.1
C9A
100u
F
1210
6.3V
C9A
100u
F
1210
6.3V
R9A
20 1206
R9A
20 1206
27dc2064afa
DEMO MANUAL DC2064A
schematic Diagrams
Figu
re 4
0. S
chem
atic
Dia
gram
Pag
e 3
1 1
AA
0402
0402
OPT
OPT
2512
2512
2512
2512
2512
2512
2512
2512
OPT
OPT
OPT
*
*
*
*
Note
: The
se ca
pacit
ors a
re n
ot in
stall
ed o
n de
mo
boar
d
V-
WDTA
VREG
2
WDTCC6
V-
C6
C6
VREG
1
C6
V-
WDT
A
C7 C6
WDT
C
C5
C6
C5
G8S
C11
G10S
I5P
G1P
G11P
G6S
G3P
I4S
I6S
I11S
I1P
C1
V-
C12
I7S
I5S
G8P
I9P
C4
I8S
C6
I10S
G3S
I11P
SCKI
C8
G2S
I10P
G12P
SDO
I4P
C6
I8P
G6P
I1S
I3S
CSBI
G5S
G7P
G9S
I2P
I12S
C10
C5 C3
I3PG4P
I2S
C9I9S
I7PG5
P
C7
G12S
G2P
SDII
I12P
I6P
G11S
G10P
G4S
G1S
G7S
C2
G9P
TOP6
_TS
BOT6
_TS
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
35
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
35
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
35
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
D19
CMMS
H2-40
21
R13
845k
0805
C11K
1.0uF 16V
0603
C27
4.7uF 16
V12
10
Q16
CMPT
3904
E1
23
D6 RS07
J
1 2
R1 1M
C31
4.7uF
16V
1210
C29
4.7uF
16V
1210
C34
10uF
10V
0805
Q14
BSS1
23W
3
1
2
E19
WDT
A
D20
CMMS
H2-40
21
R5 1M
C32
4.7uF
16V
1210
C33
10uF
10V
0805
R45 0
D26
PDZ5
.6B
21
R53
100k
D21
CMHZ
4689
21
R46 0
Q15
CMPT
3906
E1
32
U1LT
C330
0ILXE
-1
G6S
1
I6S
2
G5S
3
I5S
4
G4S
5
I4S
6
G3S
7
I3S
8
G2S
9
I2S
10
G1S
11
I1S
12
RTONS 13
RTONP 14
CTRL 15
CSBI 16
SCKI 17
SDI 18
SDO 19
WDT 20
V- 21
I1P 22
G1P 23
C1 24
I2P
25G
2P26
C2
27I3
P28
G3P
29C
330
I4P
31G
4P32
C4
33I5
P34
G5P
35C
536
I6P37G6P38
C639BOOST+40BOOST-41BOOST42
SDOI43SCKO44CSBO45
VMODE46TOS47
VREG48
GN
D49
R43 0
R50 0
C30
4.7uF
16V
1210
R8 20.5k
C6K
1.0uF 16V
0603
C4K
1.0uF 16V
0603
D8 RS07
J
1 2
C7K
1.0uF
16V
0603
R42 0
D7 RS07
J
1 2
C24
4.7uF
16V
1210
C19
0.22u
F10
V06
03
D22
CMHZ
4689
21
C4 0.1uF
10V
C23
4.7uF
16V
1210
C10K
1.0uF
16V
0603
C26
4.7uF 16V
1210
R2 0
R10
20.5k
C9K
1.0uF 16V
0603
R41 0
R9 15.4k
Q17
CMPD
M800
2A
2
1
3
R7 15.4k
C1 4.7uF
16V
1210
R4 6.8
C3 4.7uF
16V
1210
R44 0
R55
20 0603
C12K
1.0uF 16
V06
03
C2 0.1uF
10V
C3K
1.0uF 16V
0603
D16
RS07
J
12
C28
4.7uF 16V
1210
D5 CMMS
H2-40
21
D25
PDZ5
.6B
21
R47 0
C25
4.7uF 16V
1210
Q13
BSS1
23W
3
1
2
R11
15.4k
R49 0
C2K
1.0uF 16V
0603
D23
CMOS
H-4E
2 1
C22
4.7uF
16V
1210
R3 0C2
01.0
uF16
V06
03
R14
845k
0805
C8K
1.0uF 16V
0603
R52
2.0k
R12
0
C21
1.0uF
16V
0603
R6 6.8
R48 0
C5K
1.0uF 16V
0603
D24
CMOS
H-4E
21
D1 CMMS
H2-40
21
C1K
1.0uF 16V
0603
U2LT
C330
0ILXE
-1
G6S
1
I6S
2
G5S
3
I5S
4
G4S
5
I4S
6
G3S
7
I3S
8
G2S
9
I2S
10
G1S
11
I1S
12
RTONS 13
RTONP 14
CTRL 15
CSBI 16
SCKI 17
SDI 18
SDO 19
WDT 20
V- 21
I1P 22
G1P 23
C1 24
I2P
25G
2P26
C2
27I3
P28
G3P
29C
330
I4P
31G
4P32
C4
33I5
P34
G5P
35C
536
I6P37G6P38
C639BOOST+40BOOST-41BOOST42
SDOI43SCKO44CSBO45
VMODE46TOS47
VREG48
GN
D49
R51
2.0k
C18
0.22u
F10
V06
03
E20
WDT
CR5
420 0603
28dc2064afa
DEMO MANUAL DC2064A
schematic Diagrams
Figu
re 4
1. S
chem
atic
Dia
gram
Pag
e 4
1 1
AA
C3_F
ILTE
R
C1
C2_F
ILTE
R
C11_
FILT
ER
C2
C7_F
ILTE
RC7
C12_
FILT
ER
C12
C8
C10_
FILT
ER
C6C10
C6_F
ILTE
R
C1_F
ILTE
R
C8_F
ILTE
R
C11
C12_
CLAM
PED
C12_
CLAM
PED
C3
C4_F
ilter
C5 C4
C9_F
ILTE
R
C5_F
ILTE
R
C9
V-
C1
C2C3
C4
C5
C7C8
C9
C10
C12
C6
C11
V-
V-V-V- V-V- V- V-V-V- V- V- V-
C11_
FILTE
R
C2C6
C4_F
ilter
C9 C8 C1
C9_F
ILTER
C7_F
ILTER
C5_F
ILTER
V-
C1_F
ILTER
C10_
FILTE
R
C3C5C7
C8_F
ILTER
C3_F
ILTER
C11
C6_F
ILTER
C4
C12_
CLAM
PED
C10
C12_
FILTE
R
C2_F
ILTER
C12
V-
C4C7C3
C10
C2 C6
C8C9C5C1
C11
G1P
G2P
G3P
G4P
G5P
G6P
G7P
G8P
G9P
G10P
G11P
G12P
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
45
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
45
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
45
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
D4D
GRN
LED-
LND4
DGR
NLE
D-LN
L1 1206L1 1206
J5 1793
1400
0_SC
J5 1793
1400
0_SC
C1S
+1
C1+
2C
2S-
3D1
0EPD
Z7.5B
D10E
PDZ7
.5B
21F2
7A
1210
F2
7A
1210
E5C4
E5C4
F10
7A
1210
F10
7A
1210
D1D
GRN
LED-
LND1
DGR
NLE
D-LN
R9J
2.00k
R9J
2.00k
R1J
2.00k
R1J
2.00k
R9K
100
0603
R9K
100
0603
C3L
0.1uF
100V
1206
C3L
0.1uF
100V
1206
R6K
100
0603
R6K
100
0603
D1E
PDZ7
.5BD1
EPD
Z7.5B
21
J13
1793
1400
0_SC
J13
1793
1400
0_SC
C9S
+1
C9+
2C
10S
-3
E14
C12
E14
C12
F3
7A
1210
F3
7A
1210
R5J
2.00k
R5J
2.00k
C5L
0.1uF
100V
1206
C5L
0.1uF
100V
1206
R8K
100
0603
R8K
100
0603
E10
C8E1
0C8
F11
7A
1210
F11
7A
1210
R3K
100
0603
R3K
100
0603
D5E
PDZ7
.5BD5
EPD
Z7.5B
21
D11D
GRN
LED-
LND1
1DGR
NLE
D-LN
J16
1793
1300
0_SC
J16
1793
1300
0_SC
C12
S+
1C
12+
2
C9L
0.1uF
100V
1206
C9L
0.1uF
100V
1206
D10D
GRN
LED-
LND1
0DGR
NLE
D-LN
E18
C6E1
8C6
D9E
PDZ7
.5BD9
EPD
Z7.5B
21
C10L
0.1uF
100V
1206
C10L
0.1uF
100V
1206 C2L
0.1uF
100V
1206
C2L
0.1uF
100V
1206
J9 1793
1400
0_SC
J9 1793
1400
0_SC
C5S
+1
C5+
2C
6S-
3
F4
7A
1210
F4
7A
1210
R7J
2.00k
R7J
2.00k
J7 1793
1400
0_SC
J7 1793
1400
0_SC
C3S
+1
C3+
2C
4S-
3
F12
7A
1210
F12
7A
1210
D8D
GRN
LED-
LND8
DGR
NLE
D-LN
R8J
2.00k
R8J
2.00k
R10K
100
0603
R10K
100
0603
F15 7A
1210
F15 7A
1210
R3J
2.00k
R3J
2.00k
C12L
0.1uF
100V
1206
C12L
0.1uF
100V
1206
D3D
GRN
LED-
LND3
DGR
NLE
D-LN
F5
7A
1210
F5
7A
1210
E13
C11
E13
C11
R7K
100
0603
R7K
100
0603
D4E
PDZ7
.5BD4
EPD
Z7.5B
21
D7D
GRN
LED-
LND7
DGR
NLE
D-LN
J4
1793
1300
0_SC
J4
1793
1300
0_SC
C1S
-1
C1-
2
J12
1793
1400
0_SC
J12
1793
1400
0_SC
C8S
+1
C8+
2C
9S-
3
J11
1793
1400
0_SC
J11
1793
1400
0_SC
C7S
+1
C7+
2C
8S-
3
D8E
PDZ7
.5BD8
EPD
Z7.5B
21
C4L
0.1uF
100V
1206
C4L
0.1uF
100V
1206
D5D
GRN
LED-
LND5
DGR
NLE
D-LN
E3C2
E3C2
F6 7A
1210
F6 7A
1210
E11
C9E1
1C9
R4K
100
0603
R4K
100
0603
E1V-
E1V-
R2J
2.00k
R2J
2.00k
E2C1
E2C1
R11J
2.00k
R11J
2.00k
R5K
100
0603
R5K
100
0603
D3E
PDZ7
.5BD3
EPD
Z7.5B
21
F7 7A
1210
F7 7A
1210
R1K
100
0603
R1K
100
0603
C8L
0.1uF
100V
1206
C8L
0.1uF
100V
1206
J15
1793
1400
0_SC
J15
1793
1400
0_SC
C11
S+
1C
11+
2C
12S
-3
E7C6
E7C6
R4J
2.00k
R4J
2.00k
R11K 100
0603
R11K 100
0603
D7E
PDZ7
.5BD7
EPD
Z7.5B
21
J8
1793
1400
0_SC
J8
1793
1400
0_SC
C4S
+1
C4+
2C
5S-
3
D2D
GRN
LED-
LND2
DGR
NLE
D-LN
D11E
PDZ7
.5BD1
1EPD
Z7.5B
21
E4C3
E4C3
R10J
2.00k
R10J
2.00k
F8 7A
1210
F8 7A
1210
J6 1793
1400
0_SC
J6 1793
1400
0_SC
C2S
+1
C2+
2C
3S-
3
C1L
0.1uF
100V
1206
C1L
0.1uF
100V
1206
R6J
2.00k
R6J
2.00k
E9C7
E9C7
C6L
0.1uF
100V
1206
C6L
0.1uF
100V
1206
J10
1793
1400
0_SC
J10
1793
1400
0_SC
C6S
+1
C6+
2C
7S-
3
R12K 100
0603
R12K 100
0603
R12J
2.00k
R12J
2.00k
E6C5
E6C5
D12D
GRN
LED-
LND1
2DGR
NLE
D-LN
J14
1793
1400
0_SC
J14
1793
1400
0_SC
C10
S+
1C
10+
2C
11S
-3
F1 7A
1210
F1 7A
1210
D2E
PDZ7
.5BD2
EPD
Z7.5B
21
C11L
0.1uF
100V
1206
C11L
0.1uF
100V
1206 C7L
0.1uF
100V
1206
C7L
0.1uF
100V
1206
F9 7A
1210
F9 7A
1210
E12
C10
E12
C10
D9D
GRN
LED-
LND9
DGR
NLE
D-LN
D6D
GRN
LED-
LND6
DGR
NLE
D-LN
R2K
100
0603
R2K
100
0603
D12E
PDZ7
.5BD1
2EPD
Z7.5B
21
D6E
PDZ7
.5BD6
EPD
Z7.5B
21
29dc2064afa
DEMO MANUAL DC2064A
schematic Diagrams
Figu
re 4
2. S
chem
atic
Dia
gram
Pag
e 5
1 1
AA
1 0
FROM
DC 59
0BOR BO
ARD
BELO
W
0
A1A3
TO DC 59
0BIN
PUT
ABOV
E
ISOL
ATED
GND
PLA
NE
0
PC IN
PUT
A2
BA
TTER
Y ST
AC
K
A0
11
ISO
LATI
ON
BO
UN
DA
RY
1 0
IF U7
IS N
OT IN
STAL
LED:
DO
NOT
INST
ALL U
6, R2
2 -R2
5. IN
STAL
L R31
-R3
4. RE
PLAC
E C5
AND
C13
WITH
ZERO
OHM
RESI
STOR
.OPT
OPT
TEMP
1
TEMP
2
GPIO
1
V-
V-
V-
V-
V-
V-
GND_
DC59
0
GND_
DC59
0 GND_
DC59
0
V-
V-
V-
V-V-
V-
V-
CSBI
C4_F
ILTER
SDII
C10_
FILTE
R
C9_F
ILTER
VREG
C8_F
ILTER
C2_F
ILTER
C3_F
ILTER
SCKI
C7_F
ILTER
VREG
C1_F
ILTER
VREG
VREG
C12_
FILTE
R
SDO
C6_F
ILTER
C12_
CLAM
PED
C5_F
ILTER
C11_
FILTE
R
V-
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
55
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
55
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
SIZE
DATE
:
IC N
O.RE
V.
SHEE
TOF
TITL
E:
APPR
OVAL
S
PCB
DES.
APP
ENG.
TEC
HN
OLO
GY
Fax:
(408
)434
-050
7
Milp
itas,
CA 95
035
Phon
e: (4
08)4
32-1
900
1630
McC
arth
y Blvd
.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S MA
DE A
BES
T EF
FORT
TO
DESI
GN A
CIRC
UIT
THAT
MEE
TS C
USTO
MER-
SUPP
LIED
SPE
CIFI
CATI
ONS;
HOW
EVER
, IT R
EMAI
NS T
HE C
USTO
MER'
S RE
SPON
SIBI
LITY
TO
VERI
FY P
ROPE
R AN
D RE
LIAB
LE O
PERA
TION
IN T
HE A
CTUA
LAP
PLIC
ATIO
N. C
OMPO
NENT
SUB
STIT
UTIO
N AN
D PR
INTE
DCI
RCUI
T BO
ARD
LAYO
UT M
AY S
IGNI
FICA
NTLY
AFF
ECT
CIRC
UIT
PERF
ORMA
NCE
OR R
ELIA
BILI
TY. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G FO
R AS
SIST
ANCE
.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MATI
C
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
www.
linea
r.com 1
DEM
O CI
RCUI
T 20
64A
55
HIGH
EFF
ICIE
NCY
BIDI
RECT
IONA
L
N/A
LTC3
300I
LXE-
1 / L
TC68
03IG
-2
NC J. DR
EW
1 - 11
- 13
MUL
TICE
LL B
ATTE
RY B
ALAN
CER
+C1
610
uF10
V
+C1
610
uF10
V
JP4
JP4
JP3
JP3
E17
ISOL
ATED
GND
E17
ISOL
ATED
GND
R33
OPT
2010
R33
OPT
2010
D14
CMHZ
5265
BD1
4CM
HZ52
65B
21
R25
3.3k
R25
3.3k
U5B
MM74
HC00
U5B
MM74
HC00
4 56
147
J1 DF3-3
P-2D
SA
J1 DF3-3
P-2D
SA
TEM
P1
1
PIN
2
TEM
P2
3
E23
GPIO
2
E23
GPIO
2
U5D
MM74
HC00
U5D
MM74
HC00
12 1311
147
R37
100
R37
100
+C1
710
uf10
V+
C17
10uf
10V
U7 LTM2
883C
Y - 5
SU7 LT
M288
3CY
- 5S
VC
CB
7
ON
A7
SD
OE
A6
GND B5
CS
A5
GND B4
SD
IA
4
GND B3SC
KA
3
GND B2
DO
2A
2
DO
1B
1
SD
OA
1
AV
-K
7V
-L7
AV
CC
2K
6V
CC
2L6
GND2 K5
CS
2L5
GND2 K4
SD
I2L4
GND2 K3
SC
K2
L3
GND2 K2
I2L2
I1K
1
SD
O2
L1
VL
A8
VC
CB
8
AV
+K
8V
+L8
GND B6
R29
10k
R29
10k
R22
3.3k
R22
3.3k
R19 0R19 0
JP1
JP1
R16
1MR16
1M
R39
5.1k
R39
5.1k
C6 0.1uF
100V
1206
C6 0.1uF
100V
1206
R24
3.3k
R24
3.3k
E21
WDT
B
E21
WDT
BJP
2JP
2
R32
OPT
2010
R32
OPT
2010
R20 0R20 0
R26
100
R26
100
U3 SERI
AL E
EPRO
M
U3 SERI
AL E
EPRO
M
A0
1
SC
LK6
A2
3
Vss
4S
DA
5A
12
WP
7
Vcc8
E22
GPIO
1
E22
GPIO
1
J18 HD
2X7
J18 HD
2X7
N/C
1
GN
D_D
C59
03
SD
O_5
905
SD
I_59
07
EE
SD
A9
EE
SC
LK11
GN
D_D
C59
013
VC
CA
2
SC
K_5
904
CS
_590
6
GN
D_D
C59
08
EE
VC
C10
EE
VS
S12
N/C
14
C7 0.1uF
25V
0603
C7 0.1uF
25V
0603
D15
CMSH
3-20M
AD1
5CM
SH3-2
0MA
21
D13
BAT4
6WD1
3BA
T46W
21
R21 0
R21 0
C12
06031uF
25V
C12
06031uF
25V
R15
1MR15
1M
U5C
MM74
HC00
U5C
MM74
HC00
9 108
147
C14
0.1uFC14
0.1uF
R28
10k
R28
10k
C15
1uF
0603
25V
C15
1uF
0603
25V
U4LT
6004
CMS8
U4LT
6004
CMS8
OU
T A
1
-IN A
2+I
N A
3
GND 4
+IN
B5
-IN B
6
OU
T B
7
V+
8
C9 OPT
25V
0603C9 OPT
25V
0603
C10
OPT
0603
25V
C10
OPT
0603
25V
R36
100
R36
100
R34
OPT
2010
R34
OPT
2010
D12
BAT4
6WD1
2BA
T46W
21
R31
OPT
2010
R31
OPT
2010
R17
1MR17
1M R27
100
R27
100
U5A
MM74
HC00
U5A
MM74
HC00
1 23
147
C8
0.1uF
C8
0.1uF
R18 0R18 0
U6 74LV
C3G0
7U6 74
LVC3
G07
1A1
3Y2
2A3
GND 4
2Y5
3A6
1Y7
VCC8
U8 LTC6
803IG
-2U8 LT
C680
3IG-2
V+
1
C12
2
S12
3
C11
4
S11
5
C10
6
S10
7
C9
8
S9
9
C8
10
S8
11
C7
12
S7
13
C6
14
S6
15
C5
16
S5
17
C4
18
S4
19
C3
20
S3
21
C2
22S
223
C1
24S
125
V-
26N
C27
VTE
MP
128
VTE
MP
229
VR
EF
30V
RE
G31
TOS
32N
C33
WD
TB34
GP
I01
35G
PI0
236
A0
37A
138
A2
39A
340
SC
KI
41S
DI
42S
DO
43C
SB
I44
J17
HD2X
7
J17
HD2X
7
N/C
1
GN
D_D
C59
03
SD
O_5
905
SD
I_59
07
EE
SD
A9
EE
SC
LK11
GN
D_D
C59
013
VC
CA
2
SC
K_5
904
CS
_590
6
GN
D_D
C59
08
EE
VC
C10
EE
VS
S12
N/C
14
R35
100
R35
100
C5 470p
F18
08C5 470p
F18
08
C13
470p
F18
08
C13
470p
F18
08
R23
3.3K
R23
3.3K
R38
100
R38
100
R30
100
R30
100
C11
1uF
25V
0603
C11
1uF
25V
0603
R40
5.1k
R40
5.1k
E16
ISOL
ATED
+5V
E16
ISOL
ATED
+5V
30dc2064afa
DEMO MANUAL DC2064A
pcB layout
Figure 43. Top Silk Screen
31dc2064afa
DEMO MANUAL DC2064A
pcB layout
Figure 44. Bottom Silk Screen
32dc2064afa
DEMO MANUAL DC2064A
pcB layout
Figure 45. Layer 1
33dc2064afa
DEMO MANUAL DC2064A
pcB layout
Figure 46. Layer 2
34dc2064afa
DEMO MANUAL DC2064A
pcB layout
Figure 47. Layer 3
35dc2064afa
DEMO MANUAL DC2064A
pcB layout
Figure 48. Layer 4
36dc2064afa
DEMO MANUAL DC2064A
parts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components1 24 C1A-C12A, C1B-C12B CAP.,X5R, 100µF, 6.3V,10%, 1210 MURATA, GRM32ER60J107ME20L2 12 C1G-C12G CAP.,X7R, 2200pF, 50V, 10% 0402 MURATA, GRM155R71H222KA01D3 12 C1H-C12H CAP.,X7R, 470pF, 50V, 10% 0402 MURATA, GRM155R71H471KA01D4 12 C1R-C12R CAP.,X7R, 2.2µF, 100V,10%, 1210 TDK, C3225X7R2A225K5 14 C1K-C12K, C20,C21 CAP.,X7R, 1.0µF, 16V,10%, 0603 MURATA, GRM188R71C105KA12D6 4 C2, C4, C8, C14 CAP, X7R, 0.1µF, 16V, 10% 0402 MURATA, GRM155R71C104KA88D 7 1 C7 CAP.,X7R, 0.1µF, 25V,10%, 0603 AVX, 06033C104KAT2A8 3 C11, C12, C15 CAP.,X5R, 1µF, 25V,10%, 0603 TDK, C1608X5R1E105K9 2 C18, C19 CAP.,X7R, 0.22µF, 10V,10%, 0603 MURATA, GRM188R71A224KA0110 2 D23, D24 SMD, SCHOTTKY, SOD523 CENTRAL SEMI, CMOSH-4E11 4 D1, D5, D19.D20 SMD, SCHOTTKY, SOD-123F CENTRAL SEMI, CMMSH2-4012 3 D6, D7, D8 SMD, SILICON SWITCHING DIODE VISHAY, RS07J13 12 D1E-D12E DIODE, ZENER, 7.5V, 400MW, SOD323 NXP, PDZ7.5B.11514 2 D12, D13 SMD, SCHOTTKY, 200MW, 100V, SOD-12 DIODES INC, BAT46W15 1 D14 SMD, SILICON ZENER, 62V CENTRAL SEMI, CMHZ5265B16 1 D15 SMD, SCHOTTKY CENTRAL SEMI, CMSH3-20MA17 2 D21, D22 DIODE, ZENER, 5.1V,SOD-123 CENTRAL SEMI, CMHZ468918 2 D25, D26 DIODE, ZENER, 5.6V, 400MW, SOD323 NXP, PDZ5.6B.11519 12 D1F-D12F DIODE, SUPER BARRIER RECTIFIER, 10A, POWERDI5 DIODES INC, SBR10U200P520 24 R1C-R12C, R1F-R12F RES,CHIP, 5.1Ω, 1/16W, 5%, 0402 VISHAY, CRCW04025R10JNED21 2 R4, R6 RES,CHIP, 6.8Ω, 1/16W, 5%, 0402 VISHAY, CRCW04026R80JNED22 24 R1G-R12G, R1H-R12H RES,CHIP,20Ω,1/16W,5%,0402 VISHAY, CRCW040220R0JNED23 7 R26, R27, R30, R35-R38 RES,CHIP,100Ω,1/16W,5%,0402 VISHAY, CRCW0402100RJNED24 5 R1, R5, R15-R17 RES,CHIP, 1.00M, 1/16W, 5%, 0402 VISHAY, CRCW04021M00JNED25 2 R13, R14 RES, CHIP, 845k, 1/8W, 1%, 0805 VISHAY, CRCW0805845KFKEA26 3 R7, R9, R11 RES, CHIP, 15.4k, 1/16W, 1%, 0402 VISHAY, CRCW040215K4FKED27 2 R8, R10 RES, CHIP, 20.5k, 1/16W, 1%, 0402 VISHAY, CRCW040220K5FKED28 2 R51, R52 RES,CHIP,2.0k,1/16W,5%,0402 VISHAY, CRCW04022K00JNED29 2 R39, R40 RES, CHIP, 5.1k, 1/16W, 5%, 0402 VISHAY, CRCW04025K10JNED30 2 R28, R29 RES, CHIP, 10.0k, 1/16W, 5%, 0402 VISHAY, CRCW040210K0JNED31 1 R53 RES, CHIP, 100k, 1/16W, 5%, 0402 VISHAY, CRCW0402100KJNED32 2 R54, R55 RES, CHIP, 20Ω, 1/16W, 5%, 0603 VISHAY, CRCW060320R0JNED33 12 RS1A-RS12A RES, CHIP, 8mΩ, 1W, 1%, 1206 SUSUMU, PRL1632-R008-F-T134 12 RS1B-RS12B RES, CHIP, 16mΩ, 1W, 1%, 1206 SUSUMU, PRL1632-R016-F-T135 12 Q1A-Q12A MOSFET, 100V, 0.0087Ω, 60A, POWERPAK-SO8 VISHAY, SiR882DP-T1-GE336 12 Q1B-Q12B MOSFET, 100V, 0.058Ω, 25A, POWERPAK-1212-8 VISHAY, SiS892DN-T1-GE337 2 Q13,Q14 MOSFET, 100V, 10Ω, SOT-323 DIODES INC, BSS123W-7-F38 1 Q15 TRANSISTOR,PNP, 60V SOT-23 CENTRAL SEMI, CMPT3906E39 1 Q16 TRANSISTOR, NPN, 60V SOT-23 CENTRAL SEMI, CMPT3904E40 1 Q17 MOSFET, P-CHAN, 50V, 4Ω,SOT-23 CENTRAL SEMI, CMPDM8002A41 12 T1-T12 TRANSFORMER, 1:1, 3.0µH, 10.8A WURTH, 75031250442 2 U1,U2 IC, SMT, BIDIRECTIONAL BATTERY BALANCER LINEAR, LTC3300ILXE-1#PBF43 1 U3 IC, EEPROM 2KBIT, 400KHZ, 8TSSOP MICROCHIP TECH. 24LC025-I/ST44 1 U4 IC, SMT, OP AMP LINEAR, LT6004IMS8#PBT45 1 U5 IC, GATE NAND QUAD 2-PIN 14-SO FAIRCHILD, MM74HC00M46 1 U8 IC, SMT, BATTERY MONITOR LINEAR, LTC6803IG-2#PBF
37dc2064afa
DEMO MANUAL DC2064A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
parts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Components and Hardware for Demo Board Only1 12 C1E-C12E CAP.,X7R, 470pF, 100V,10%, 0603 AVX, 06031C471KAT2A2 12 C1, C3, C22-C31 CAP.,X7R, 4.7µF, 16V,20%, 1210 TDK, C3225X7R1C475M3 13 C1L-C12L, C6 CAP., X7R, 0.1µF, 100V, 10%, 1206 AVX, 12061C104KAT2A4 2 C5, C13 CAP., X7R, 470pF, 250VAC, 10%, 1808 MURATA, GA342QR7GF471KW01L5 12 D1D-D12D LED,GREEN CLEAR 0603 SMD LITE-ON, LTST-C190KGKT6 15 F1-F15 FUSE, 7A, FAST, SMD, 1206 COOPER BUSSMANN, 3216FF7-R7 1 L1 IND, FERRITE CHIP 33Ω, 6A, 1206 MURATA, BLM31PG330SN1L8 12 R1A-R12A RES, CHIP, 20Ω, 1/4W, 5%, 1206 VISHAY, CRCW120620R0JNEA9 12 R1K-R12K RES, CHIP, 100Ω, 1/16W, 5%, 0603 VISHAY, CRCW0603100RJNED10 4 R22-R25 RES, CHIP, 3.3k, 1/16W, 5%, 0402 VISHAY, CRCW04023K30JNED11 8 R43-R50 RES, CHIP, 0Ω, 2512 VISHAY, CRCW25120000Z0EG12 12 R1J-R12J RES, CHIP, 2.0k, 1/16W, 5%, 0402 VISHAY, CRCW04022K00JNED13 18 E1-E18 TP, TURRET, 0.094", PBF MILL-MAX, 2501-2-00-80-00-00-07-014 5 E19-E23 TURRET, 0.061 DIA MILL-MAX, 2308-2-00-80-00-00-07-015 2 J17,J18 CONN, HEADER, 14POS 2mm VERT GOLD MOLEX 87831-142016 1 J1 CONN, HEADER, 3POS, 2.5mm STR TIN HIROSE, DF1EC-3P-2.5DSA(05)17 1 J1 (MATE) CONN, RECEPT HOUSING, 3POS 2.5mm HIROSE, DF1E-3S-2.5C18 3 J1 (MATE CONTACT) CONTACT, SOCKET, CRIMP 20-22AWG, TIN HIROSE, DF1E-2022SCF19 4 JP1-JP4 HEADER, 3PINS, 2mm SAMTEC, TMM-103-02-L-S20 4 JP1-JP4 SHUNT 2mm SAMTEC, 2SN-BK-G21 1 U6 IC,SMT, TRIPLE BUFFER TI, SN74LVC3G07DCTR22 1 U7 IC,SMT,5V, SPI ISOLATER _ODULE LINEAR, LTM2883CY-5S#PBF23 5 MH1-MH5 STAND-OFF, NYLON, 0.500" TALL (SNAP ON) KEYSTONE, 8833 (SNAP ON)
Optional Components1 0 C1C-C12C CAP., X5R, 100µF, 6.3V,10%, 1210 MURATA, GRM32ER60J107ME202 0 C1F(OPT)-C12F(OPT) CAP., X7R, 470pF, 100V,10%, 0603 AVX, 06031C471KAT2A3 0 C1S-C12S, C1T-C12T CAP., X7R, 2.2µF, 100V,10%, 1210 TDK, C3225X7R2A225K4 0 C5, C13 RES, CHIP, 0Ω, 2010 VISHAY, CRCW20100000Z0EF5 0 C9(OPT), C10(OPT) CAP, OPT, 25V, 06036 0 C16, C17 CAP., TANT, 10µF, 10V, 20%. 1206 AVX, TAJA106M010RNJ7 0 D1A-D12A SMD, SCHOTTKY BARRIER RECTIFIER 2A, 60V, PWRD123 DIODES INC, DFLS2608 0 D1B-D12B (OPT) SMD, SCHOTTKY BARRIER RECTIFIER, 1A, 100V, PWRD123 DIODES INC, DFLS1100-79 0 D1C-D12C (OPT) SMD, SCHOTTKY, SOD-523 CENTRAL SEMI, CMOSH-4E10 0 D16(OPT) SMD, SILICON SWITCHING DIODE VISHAY, RS07J11 0 R1B-R12B (OPT) RES, CHIP, 18Ω, 1/4W, 5%, 1206 VISHAY, CRCW120618R0JNEA12 0 R3, R12, R41, R42 (OPT) RES, CHIP, 0Ω, 0402 VISHAY, CRCW04020000Z0ED13 0 R31-R34 (OPT) RES, CHIP, 0Ω, 2010 VISHAY, CRCW20100000Z0EF14 0 J2-J4,J16 (OPT) HEADER, 1x2, 2-PIN, 3.81mm, 90 DEG WEIDMULLER, 179313000015 0 J2(OPT) (MATE) SOCKET, 1x2, 2-PIN, 3.81mm, 180 DEG WEIDMULLER, 179277000016 0 J5-J15 (OPT) HEADER, 1x3, 3-PIN, 3.81mm, 90 DEG WEIDMULLER, 179314000017 0 J5-J15 (OPT) SOCKET, 1x3, 3-PIN, 3.81mm, 180 DEG WEIDMULLER, 1792780000
38dc2064afa
DEMO MANUAL DC2064A
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2013
LT 0315 REV A • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation
