Delta–Sigma Modulator With a 50 MHz Sampling Rate Implemented in 0.18um CMOS Technology

ISSN 10637397, Russian Microelectronics, 2010, Vol. 39, No. 3, pp. 210219. Pleiades Publishing, Ltd., 2010.Original Russian Text A.S. Korotkov, M.M. Pilipko, D.V. Morozov, J. Hauer, 2010, published in Mikroelektronika, 2010, Vol. 39, No. 3, pp. 230240

210

1. INTRODUCTION

Tracking analogtodigital converters (ADCs)using deltasigma modulation compare favorablywith the other types of ADC in terms of power consumption and size [1, 2]. Deltasigma ADCs haverecently become popular in mobile phones. For example, singleconversion receivers with zero intermediate frequency employ a deltasigma ADC resolutionof 812 bits to convert constant signal levels in thecommunication channel.

Deltasigma ADCs are based on the concept ofdelta modulation, in which a continuous signal undergoes clocked conversion into a sequence of voltagepulses, whose height represents the sign of the increment of the original signal at each clock instant, relative to the preceding value of the signal. If a signal hasa uniform spectrum or contains a constant component, its conversion involves a deltasigma modulator,which operates in oversampling mode, i.e., well abovethe Nyquist rate, and therefore requires a decimationfilter. This tends to be implemented as a standarddesign, e.g., a finiteimpulseresponse filter. However,the performance of a deltasigma ADC is mainlydetermined by its deltasigma modulator, since thelatter is solely responsible for analogtodigital conversion, the decimation filter reducing output pulserate and doing serialtoparallel code conversion. Thisconsideration explains why designing a deltasigmamodulator plays such an important part in building adeltasigma ADC. Theoretical research on deltasigma modulators was reviewed by Korotkov andTelenkov [1]. Note that a deltasigma modulator canbe implemented from a programmable analog integrated circuit [3] or as an applicationspecific integrated circuit (ASIC).

This paper describes a newly designed deltasigmamodulator having a clock rate of 50 MHz, an oversam

pling index of 128, a dynamic range of 56 dB, and asupply voltage of 1.8 V. The device is fabricated as anASIC by the UMC 180 nm mixedmode/RF 1P6Mprocess.

The paper is organized as follows. Section 2describes the structure of the deltasigma modulator,designed as a balanced switchedcapacitor (SC) circuit; it also deals with the configurations of its mainunits. Section 3 presents simulation results for themodulator as a whole and for each of its main units,obtained at the circuit and the component level,respectively. Section 4 presents test results for theactual modulator. The conclusions are given in Section 5.

2. STRUCTURE OF THE DELTASIGMA MODULATOR

Secondorder deltasigma modulators are probably the most common category of the device, superiorin dynamic range to firstorder circuits. At the core ofany deltasigma modulator lie integrators; they areusually implemented in CMOS technology as SC circuits. An example of a circuit configuration proposedfor such an integrator can be found in a paper byRogatkin [4]. Its feasibility was substantiated by computer simulation using Cadence Design Systems software.

Figure 1 shows a block diagram of a secondorderbalanced deltasigma modulator [5, 6]. Its balancedinput port comprises an inverting and a noninvertingterminal, designated in+ and in, respectively; itsunbalanced output port is designated out. The modulator is made up of two integrators, a comparator I3,and feedback loops. These include switches s1 and s2for applying one of two reference node voltages, vref +and vref, depending on comparatoroutput polarity

DeltaSigma Modulator with a 50MHz Sampling Rate Implemented in 0.18m CMOS Technology

A. S. Korotkova, M. M. Pilipkoa, D. V. Morozova, and J. Hauerba St. Petersburg State Technical University, St. Petersburg, Russiab Fraunhofer Institute for Integrated Circuits, Erlangen, Germany

email: [email protected]: [email protected]

Received February 16, 2009

AbstractThe results are presented of a design effort concerned with a deltasigma modulator with a 50MHz clock rate and a 128 oversampling ratio. Its prototype is fabricated in 0.18m CMOS technology andis powered by a 1.8V unipolar supply. It provides a 9bit resolution, while consuming 33 mW of power.

DOI: 10.1134/S106373971003008X

CIRCUIT ANALYSIS AND SYNTHESIS

RUSSIAN MICROELECTRONICS Vol. 39 No. 3 2010

DELTASIGMA MODULATOR WITH A 50MHz SAMPLING RATE 211

and relevant arm. The integrators are based on amplifiers I1 and I2, respectively, and use twophase SC circuits, with the respective phases denoted by ph1 andph2. The node whose voltage corresponds to the dcoperating point is designated agnd.

When used as a part of a deltasigma modulator, anoperational amplifier (opamp) is not expected to haveresistive load, so its output impedance does not needto be small. Moreover, there is no output voltage follower in most opamps designed for the purpose, forwhich reason these do not belong to voltage sources,but rather fall in the category of voltagecontrolled

current sources, or operational transconductanceamplifiers (OTAs). (The categories and features of onchip amplifiers in current use are treated in detail in asurvey by Korotkov and Morozov [7].) It is importantthat an OTA intended for insertion into a deltasigmamodulator have an adequate bandwidth and a sufficiently high voltage gain at the lower frequencies,because the former property determines the modulator bandwidth, and the latter makes for lower quantization noise.

Figure 2 represents an OTA that makes a balancedcircuit with respect to both input and output, with the

ph2 ph1

ph2

ph2

ph1

ph1

ph2 ph1

C1

C2

in+

in

in+

in out+

out

I1

C3

C4

ph1

ph1

ph2

ph2

ph2

ph2

ph1

ph1

C5

C6

C8

C7ph1

ph1

ph2

ph2

in+

in out+

out

I2

C9

C10

in+

in

I3

out out

out

out vref

vref+

vref+vref

S2

S1

agn

dag

nd

agn

d

agn

d

agn

d

agn

d

Fig. 1. Structure of the secondorder balanced deltasigma modulator.

vss

vbn

M11

M5

M9

vbp

vdd

in+

vcmfb1

vb1M13

vcmfb1

vbn

in

M1 M2

M7

M3 M4

vbp

out out+

M6

M8

M10

M12

Fig. 2. Operational transconductance amplifier.

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KOROTKOV et al.

parts forming the reference voltages being omitted [5].In Fig. 2, vdd and vss designate supplyvoltage nodes;vb1, vbn, vbp, and vcmfb1 designate referencevoltagenodes; in+ and in refer to an inverting and a noninverting input terminal, respectively; and out+ andout to an inverting and a noninverting output terminal, respectively. The OTA contains two input transistors, M1 and M2; two current mirrors based on thetransistors M3 and M5 and the transistors M4 and M6,

respectively; two pairs of output transistors, M7M9and M8M10, respectively; two transistors, M11 andM12, for commonmode voltage rejection at the output; and a current source built around the transistorM13. The current mirrors provide the reference voltages at vb1, vbn, and vbp.

For the OTA in Fig. 2, the voltage gain AV is foundto be given by

where gmi is the transconductance of the ith and(i + 1)th transistors with i = 1, 3, 5, 7, 9; gDi is thechannel conductance of the ith and (i + 1)th transistors with i = 5, 7, 9, 11; CL = = are the loadcapacitances connected to the noninverting andinverting output nodes; and p is the complex frequency.

Figure 3 depicts a feedback loop that delivers a suitable signal to the vcmfb1 node in Fig. 2 [5, 8]. Thenodes out and out+ are respectively connected to aninverting and a noninverting output terminal of theOTA. The voltage at vcmfb1 is produced by a resistivedivider built around the SCs C1 and C2 (between out+and out). The capacitors C3 and C4 are introducedfor feedback smoothing; they are superior to C1 andC2 in value. When calculating the integrator, accountshould be taken of the contribution made by thecapacitor pairs C1, C3 and C2, C4 to the respectiveloads of the noninverting and the inverting output terminal. Current mirrors provide the reference voltageat vcm1.

SC circuits may suffer from clock feedthrough viathe parasitic capacitances of the switching MOSFETs.Adding appropriate MOSFETs to the integratorswitches has been proposed as a measure to reduce thephenomenon [9]. This approach is illustrated byFig. 4. It uses vc+ and vc to denote nodes to which

clock pulses of opposite polarity are applied; Wn andLn to denote the channel width and length, respectively, of an nMOSFET; and Wp and Lp to denotethose of a pMOSFET. The switch is built around thetransistors M1 and M2, with the M3, M5 and M4, M6pairs added to suppress clock feedthrough. Each additional transistor has its source and drain terminalsconnected together to form a capacitor made up of thegatesource and gatedrain parasitic capacitancesconnected in parallel. The respective parasitic capacitances of each main MOSFET and the appropriateadditional MOSFET cancel each other out to suppressclock feedthrough if the channel of the latter MOSFET is as long and half as wide as that of the former;the way clock pulses are applied is essential.

Figure 5 presents the circuit configuration of thecomparator, whose purpose is to produce outputbinary codes. It is a balanced circuit with respect to theinput. The comparator consists of the following units,connected in series: an input stage built around thetransistors M1M7, a bistable cell based on the transistors M8M17 and on a switch that is clocked by thephase ph2, CMOS inverters using the transistorsM18M25, and the Dtype flipflop I1.

The transistors M1M5 form a differential stagewith a balanced output port at n+ and n. The transis

AVgm1gm5gm7gm9

gm3 gm7gD9gD11 gm9gD5gD7 gm7gm9sCL+ +( ),=

CL

+ CL

ph2

ph1

C1

ph2

ph1 ph1

C3

C2

C4

ph2 ph2

vcm1

vcm

fb1

ou

t+

agn

d

ph1

ou

t

agn

d

Fig. 3. Feedback loop.



tors M6 and M7 are diodeconnected to make a limiter for the output. The nodes vcmfb2 and vb2 are usedto connect a feedback loop and a bias voltage source,respectively. The feedback is provided by a similar circuit to that in Fig. 3; however, the nodes out+ andout are connected to the nodes n+ and n in the comparator (Fig. 5), and the nodes vcm1 and vcmfb1 arereplaced with vcm2 and vcmfb2, respectively. Currentmirrors provide the reference voltages at vcm2 and vb2.

The circuit configuration of the bistable cell is as in[8]. In Fig. 5, n+ and n make up its input port, andnq+ and nq refer to its output port. Again, ph1 andph2 denote the respective phases of the clockingscheme. The phase ph1 is designed to produce appro

priate voltages at nq+ and nq. During the phase ph2,the switch closes to connect n+ and n together and tomake the cell change state; as a result, the voltages atnx+ and nx become equal to that at vdd. The switchconcerned is as in Fig. 4.

Each output terminal of the bistable cell is connected to two CMOS inverters in series, which providebuffering and ensure that the output terminals have thesame capacitive load. The inverter based on M22 andM23 has its output terminal connected to the datainput of the Dtype flipflop, which is edgetriggeredby the ph2 pulses. The flipflop is designed in a standard fashion.

Wn/Ln 2Wn/Ln Wn/Ln

Wp/Lp Wp/Lp2Wp/Lp

M2

M1

M6

M4

M5

M3

vc+

vdd

1

vss

vc

2

Fig. 4. CMOS switch with added MOSFETs.

vdd

in

M3

in+

M4

M8 M9 M10 M11

M8

M7

M1 M2 M12 M13

vcmfb2

ph2

ph2

ph1

M5

vss

vb2M14 M15 M16M17

n

n+

nx+nx

nqnq+

ph2

M18

M19 M23

M22

M21

M20

M25

M24

vdd

vss

D

C

Q out

I1

Fig. 5. Comparator.

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KOROTKOV et al.

3. SIMULATION OF THE DELTASIGMA MODULATOR

The performance of a deltasigma modulator ismainly evaluated in terms of its signaltonoise ratio(SNR). This property is calculated from the outputspectrum, which has to be simulated over tens of thousands of periods for the input signal. With oversampling, it is not feasible to simulate a deltasigma modulator at component level, the clock rate being morethan 100 times as high as the maximum input frequency. The reason for the considerable length ofcomputing time required in that case is that the differential equations employed have to be integrated with astepsize equal to the smallest time constant of the circuit components. This explains why circuitlevel(conductancematrix) simulations are so popularwhen dealing with deltasigma modulators [10, 11].They indeed take reasonable computing time.

A feature of circuitlevel simulations is that theyassume a particular signal being applied to the modulator. If s(t) = Umsint is selected, the outputsequence will show repeatability, reflecting the periodicity of the quantization noise. This implies more harmonic components in the output spectrum. The correlation between the quantization noise and the inputsignal in this case makes it impossible to attenuate theadditional harmonic components by averaging. Nevertheless, the noisesignal correlation can be reduced

by adding white noise to the input, a method calledrandomization [12]. It is recommended that the rmsvalue of the white noise lie between onethird and onetimes the value of the least significant bit of the ADC.Since a deltasigma modulator is merely the first unitin an ADC, the value of the least significant bit for theADC should be obtained from a wellknown equationfor the dynamic range DR of an Nbit ADC:

DR = 6.02N + 1.76 (dB)

With DR = 56 dB, this equation implies N = 9 forthe deltasigma modulator considered.

The circuitlevel simulation of the deltasigmamodulator (Fig. 1) involved the construction of a specific equivalent network for each of the two phases, asin [10, 11]. Each of the OTAs was represented by atwoterminal model based on voltagecontrolled voltage sources. It was described in terms of the respectivegains of the first and the second stage, the input andthe output conductances, and the capacitances andconductances that determined the frequencies associated with the first and the second pole. Each switchwas represented by a conductance whose value wassubject to change with state. Conductance and capacitance matrices were constructed from equivalent networks. The capacitances were assigned the followingvalues:

C1 = C2 = 2 pF; C3 = C4 = 8 pF; C5 = C6 = 1.6 pF; C7 = C8 = 0.8 pF; C9 = C10 = 4.8 pF.

subject to the condition C1/C3 = 1/4 and C5/C7 =2/1 [13].

The reference voltages at vref + and vref were 1.8and 0 V, respectively, and 0.9 V relative to agnd. Thevoltage at agnd was half as high as the supply voltage,and so was equal to 0.9 V. The output spectrum wascomputed by a 220point discrete Fourier transform.

Figure 6 displays the simulated output spectrum ofthe deltasigma modulator at Um = 0.45 V and /2=200 kHz. As noted above, the quantization noise iscorrelated with the input in this case. Accordingly,white noise was then added to the same sinusoidal signal, with its rms value set to the value of the least significant bit, namely, 1.8 mV. The latter was calculatedas the ratio of 2Um to the total number of quantizationlevels, which was 29. Figures 7 and 8 represent theinput and output spectra, respectively.

Figure 9 shows output SNR against input signalstrength for the deltasigma modulator, its dynamicrange being 66 dB.

The circuitlevel simulation yielded the followingvalues for the OTA model parameters. The respectivegains of the first and the second stage were 25 and 40.The input and output conductances were 10 nS and 2mS, respectively. The capacitance and conductanceassociated with the first pole were 0.3 pF and 940 nS,

respectively. Those associated with the second polewere 0.3 pF and 700 S, respectively. The switcheswere found to have a conductance of 2.5 mS or 10 nSwhen closed or open, respectively.

The OTA (Fig. 2) and the comparator (Fig. 5) weresimulated with Cadence Design Systems software.Figure 10 presents the magnitude response and thephase response for the OTA, which was found to havea 60dB gain, a 500MHz unitygain frequency, and a50degree phase margin. Its current consumption wasestimated at 8 mA. The MOSFET channel widths andlengths (Fig. 2) in micrometers were taken to be as follows: W1/L1 = W2/L2 = 400/0.4; W3/L3 = W4/L4 =75/0.4; W5/L5 = W6/L6 = 150/0.4; W7/L7 = W8/L8 =450/0.4; W9/L9 = W10/L10 = 450/1; W11/L11 = W12/L12 =50/0.4; W13/L13 = 30/2. The fabrication processselected was such as to produce the transistors M1M12 with reduced threshold voltages. The feedbackloop (Fig. 3) had C1 = C2 = 0.2 pF and C3 = C4 =1 pF. The switches were as in Fig. 4, with Wn = 1 m,Ln = 0.35 [mu]m, Wp = 4 m, and Lp = 0.35 m.

In the comparator (Fig. 5), the MOSFET channelwidths and lengths in micrometers were taken to be asfollows: W1/L1 = W2/L2 = 50/1; W3/L3 = W4/L4 = 40/1;W5/L5 = 16/2; W6/L6 = W7/L7 = 10/0.24; W8/L8 =W11/L11 = 3/0.4; W9/L9 = W10/L10 = W12/L12 = W13/L13



= 0.9/0.4; W14/L14 = W17/L17 = 1.8/0.4; W15/L15 =W16/L16 = 0.54/0.4; W18/L18 = W20/L20 = 1.6/0.24;W19/L19 = W21/L21 = 0.8/0.24; W22/L22 = W24/L24 =3.2/0.24; W23/L23 = W25/L25 = 1.6/0.24. The fabrica

tion process selected was such as to produce the transistors M1M4 and M6M25 with reduced thresholdvoltages. The capacitor values of the feedback loopwere set as with the OTA.

0

103 104 105 106 107102

20

40

60

80

100

120

Frequency, Hz

dB

Fig. 6. Simulated output spectrum of the deltasigma modulator with a sinusoidal input.

103 104 105 106 107102120

Frequency, Hz

100

80

60

40

20

0

Fig. 7. Input spectrum of the deltasigma modulator in the case of the sinusoidal signal of Fig. 6 with additive white noise.

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KOROTKOV et al.

4. TESTING A PROTOTYPEOF THE DELTASIGMA MODULATOR

Figure 11 presents a photograph of a prototype chiplayout for the deltasigma modulator, implemented in0.18m CMOS technology. The prototype was testedin the arrangement shown in Fig. 12 (the contact padsare designated as in Fig. 11). The contact pads vddd

and vssd were used to connect the power supply of a50MHz onchip digital clock, which was connectedto the clock pad with the pd pad grounded. In producing appropriate reference voltages for the OTAs andthe comparator, it was possible to set the currentthrough the currentmirrorbased circuits by means ofan on or offchip current source, with the cib padconnected to the ground or the positive rail, respectively (the offchip source was connected to ib). At theoutput the logic 1 voltage level, 1.8 V, was set by a voltage source connected to v3io.

The output bit stream was recorded with an Agilent16702A digital logic analyzer, and was processed withMATLAB. Testing was performed at a 50MHz clockrate on a 200kHz balanced sinusoidal signal withamplitude variable between 0.05 and 0.45 V. Figure 13shows the output spectrum for a 0.45V input, computed by a 220point discrete Fourier transform. Notethe close agreement with the simulated spectrum inFig. 8. The second harmonic should be caused by theinput generator. The inferior performance of the prototype compared with its simulation model is mainlyattributable to the internal noise of the modulatorcomponents, clock feedthrough, instrumentationnoise, and fabricationprocess spread.

A measured relationship of output SNR to inputamplitude yielded a dynamic range of 56 dB, implyinga 9bit resolution. The prototype was found to consume 33 mW of power.

120

100

80

60

40

20

0

dB

103 104 105 106 107102

Frequency, Hz

Fig. 8. Simulated output spectrum of the deltasigma modulator in response to the input displayed in Fig. 7.

70

70

60

20

50

40

30

10

0

1060 2050 40 30 0Input signal strength, dB

10

Out

put

SN

R,

dB.

Fig. 9. Simulated output SNR vs. input signal strength forthe deltasigma modulator.



30

101 102 103 104 105 106 107 108 109100

120

60

90

150

180

210

0

10

0

10

40

20

30

50

60

70

Hz

Deg

rees

dB

Fig. 10. Simulated magnitude response and phase response for the OTA.

Fig. 11. Prototype chip layout for the deltasigma modulator.

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KOROTKOV et al.

5. CONCLUSIONS

The results are presented of a design effort concerned with a switchedcapacitor balanced deltasigma modulator with a 50MHz clock rate and a 128

oversampling index. Its prototype is fabricated in a0.18[mu]m CMOS technology, powered by a 1.8Vunidirectional supply. When tested on balanced sinusoidal signals with amplitude reaching 0.45 V, the prototype shows a 56dB dynamic range, implying 9bit

out

vss vssdib cib pd clock

v3ioin+

in

+

+

vdd agndvref+ vref vddd

1.8 V 1.8 V 1.8 V0.9 V+ + ++

+1.8 V

Agilent 16702ALogic AnalysisSystem

Fig. 12. Test setup for the prototype deltasigma modulator.

120

100

80

60

40

20

0

dB

103 104 105 106 107102

Frequency, Hz

Fig. 13. Example of a measured output spectrum from the prototype deltasigma modulator.



resolution. It consumes 33 mW of power. The testshave substantiated its computer simulations and provided evidence for the feasibility of the design.

REFERENCES1. Korotkov, A.S. and Telenkov, M.V., AnalogtoDigital

Converters Based on DeltaSigma Modulators, Zarubezh.Radioelektron. Usp. Sovremennoi Radioelektron., 2002, no.12, pp. 5372.

2. Shakhov, E.K., ADCs: Oversampling, QuantizationNoise Shaping, and Decimation, Datchiki Sist., 2006, no.11, pp. 5057.

3. Barkanov, A.V. and Korotkov, A.S., DeltaSigma Modulator Implemented in a Programmable Analog IntegratedCircuit, in Materialy 3ei NTK Novye metodologii proektirovaniya izdelii mikroelektroniki (Proc. 3rd Tech. Conf.on Novel Microelectronic Design Methodologies),Vladimir State Univ., 2004, pp. 4346.

4. Rogatkin, Yu.B., CMOS SwitchedCapacitor Integrator,Mikroelektronika, 2003, vol. 32, no. 6, pp. 414420 [Russ.Microelectron. (Engl. Transl.), vol. 32, no. 6, pp. 333338].

5. Carrillo, J.M., Montecelo, M.A., Neubauer, H., Hauer,H., and DuqueCarrillo, J.F., 1.8V SecondOrder Modulator in 0.18m CMOS Technology, in Proc. European Conf. on Circuit Theory and Design, 2005, vol. 1,pp. 197200.

6. Korotkov, A.S. and Pilipko, M.M., ExpandedBandwidthDeltaSigma Modulator for Use in ADCs, in Trudy SPb

GPU (Proceedings of St. Petersburg State Technical University), 2006, no. 500, pp. 7378.

7. Korotkov, A.S. and Morozov, D.V., CircuitDesign Solutions for Advanced Onchip Amplifiers, Zarubezh. Radioelektron., 1998, no. 6, pp. 4175.

8. Medeiro, F., PerezVerdu, B., and RodriguezVazquez, A.,A 13Bit, 2.2MS/s, 55mW Multibit Cascade Modulator in CMOS 0.7[mu]m SinglePoly Technology, IEEEJ. SolidState Circuits, 1999, vol. 34, no. 6, pp. 748760.

9. Korotkov, A.S., Morozov, D.V., and Tutyshkin, A.A., LowPower CMOS SwitchedCapacitor Lowpass Filter UsingCurrent Conveyors, Mikroelektronika, 2006, vol. 35, no. 6,pp. 471480 [Russ. Microelectron. (Engl. Transl.), vol. 35,no. 6, pp. 405413].

10. Korotkov, A. and Telenkov, M., Simulation of Linear andNonlinear Effects in SwitchedCapacitor DeltaSigmaModulators, in Proc. 7th IEEE Emerging TechnologiesWorkshop, St. Petersburg, Russia, 2005, pp. 5863.

11. Korotkov, A.S. and Telenkov, M.V., Linear and NonlinearModeling of SwitchedCapacitor Modulators, Mikroelektronika, 2007, vol. 36, no. 1, pp. 6677 [Russ. Microelectron. (Engl. Transl.), vol. 36, no. 1, pp. 5666].

12. Lyons, R.G., Understanding Digital Signal Processing,Upper Saddle River, NJ: Prentice Hall, 2004, 2nd ed.

13. Medeiro, F., PerezVerdu, B., de la Rosa, J.M., and RodriguezVazquez, A., FourthOrder Cascade SC Modulators: A Comparative Study, IEEE Trans. Circuits Syst.I, 1998, vol. 45, no. 10, pp. 10411051.

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Delta–Sigma Modulator With a 50 MHz Sampling Rate Implemented in 0.18um CMOS Technology

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