Delay-time Suppression Technique for DC/DC Buck Converter Using Voltage Mode … · 2017. 11....

Delay-time Suppression Technique

for DC/DC Buck Converter

Using Voltage Mode PWM Control

M. W. D. SAHAN *

N.Tsukiji, Y.Kobori, K. Asaishi, N.Takai, H. Kobayashi

Faculty of Science and Technology

Kobayashi laboratory

Gunma University

Paper 13ISPACS2017

XIAMEN CHINA（2017/11/09）

Outline

1. Purpose of This work

2. Research Background

3. Approach

4. Delay time suppression

5. Measurements results & Comparisons

6. Conclusion

ISPACS – XIAMEN 7-9 November 2017

Purpose of This work

Lower output undershoot/overshoot

voltage of the DC/DC buck converter


Output voltage

undershoot

Load current

Outline



3. Approach



6. Conclusion


Proposed product

Research background

Research

「Fast Response」ISPACS – XIAMEN 7-9 November 2017

Miniaturization

NoiseReduction

Fast Response

High performance

Outline



3. Approach



6. Conclusion


Approach


Micro chip

DC/DC

converter

Sudden

Load current

Conventional

method

proposed

methodundershoot

undershoot

Load current

Load current

iPod Charger

Ex :-

Delay time Suppression


Sudden load

current change

Transistor

power switch

ON

Delay time

Detect with

High-pass filter

Immediately

Undershoot

Undershoot

Load current

Load current

Outline



3. Approach



6. Conclusion


Delay time

Delay time Suppression

Conventional

circuit

Proposed

circuit

Delay time

Advantages

• Decrease output

voltage

• Fast response

sudden load

current

Disadvantages

• Large output

undershoot

voltage

• Worse load

current response

Inductor current

Output voltage

Load current

Inductor current

Output voltage

Load current

Proposed Converter Architecture

-

+

SR

Q

clkON

PowerStage

OFF

-

+ Vref

sawtooth

Vin

CS

EAcomp

VoVswSW

Cd

Rd

Detection circuit

Control

circuit

-

+-

+

clk

D Q

QN

CS

Vref1

Vref2

ON

OFF

Flip flop

latchOFF

CLK ON

Q

R

S

saw-tooth

Error amp1

OR２

OR１

Amplification

circuit

CS

CS

Error amp2

comparator2

Output

voltage

-

+

Comparator1

+

-


Io

Output voltage

Detection circuit

High-pass filterload current has

differentiated by

high-pass filter

50%

Generated a smalldetection voltage (mV)

Load current

Detection signal

Amplification circuit & Control circuit

VA

VB

Amplification

circuit

Control

circuit

Output voltage

CS amplified

ON OFF signals

converted to

Control circuit

Outline



3. Approach



6. Conclusion


Simulation setup


Parameter Value

Vin 12 V

Vo 5 VFrequency 350 kHz

L 10 μH

Co 20 μF

Rd 10 kΩ

Cd 100 pF

12 V

= 5 V

= 10 kΩ

= 100 pF

Simulation results

191mV

Conventional method

Proposed method Delay time

Delay time

Inductor current

Output voltage

Load current

Inductor current

Output voltage

Load current

Undershoot

191mV

Undershoot

38mV 38mV

Time [ms]

Time [ms]

Curr

ent

[A]

Curr

ent

[A]

Voltage [

V]

Voltage [

V]

Reduce 80%

Simulation Results

Detective

Amplification

Control


Sudden

load current

Detective circuit

output signal

Error amp 2

Output signal

Comparator 2

Output signal

Flip flop

output signal

Time [ms] Time [ms]

Vo

ltage [

V]

Voltage [

V]

Voltage [

V]

Voltage [

V]

Curr

ent

[A]

Curr

ent

[A]

Voltage [

V]

Voltage [

V]

Logical calculation(1)

Conventional method（include delay time）

𝑄 = 𝑖𝑡Total area= Capacity = 3.890 × 10−6C

𝑉0 =𝑄

𝐶𝑜

=3.890×10−6c20×10−6c

=194mV

𝑉0 : Voltage change𝑄 : Capacity𝑖 : Load current𝑡 ∶ Time𝐶𝑜 ∶ capacitor

Simulation result

191mV

Calculation result

194mV

area


Inductor current IL

Output voltage Vo

Load current Io

Curr

ent

[A]

Voltage [

V]

Time [ms]

194mV

Transistor power switch

Logical calculation (2)

Proposed circuit（without delay time）

𝑄 = 𝑖𝑡Total area = 8.84 × 10−7𝐶

𝑉0 =𝑄

𝐶

=0.884×10−6c20×10−6c

= 44.2mV

𝑉0 : Voltage change𝑄 : Capacity𝑖 : Load current𝑡 ∶ Time𝐶𝑜 ∶ 𝑐𝑎𝑝𝑎𝑠𝑖𝑡𝑜𝑟

Conventional : 194mV

Proposed : 44.2mV

Simulation result

38mVCalculation result

44.2mV

area


Inductor current IL

Output voltage Vo

Load current Io

Curr

ent

[A]

Voltage [

V]

Time [ms]

t

undershoot

44.2mV

Transistor power switch

Comparison with Undershoot

Phase[deg]

Und

ers

hoot vo

lta

ge

[mV

]

phase

phase

-180°

-180° 180°

180°0°

0°

proposed

conventional

Phase Between

-180° to 0°

Conventional method

Inductance current does not

change even if load current is

generated

proposed method

When load current occur,

Inductance current rises up at

moment

Undershoot

Clock

Io

IL

𝑇𝑂𝑁

𝑇× 360° = Phase

Comparison with Undershoot

Phase[deg]

Und

ers

hoot vo

lta

ge

[mV

]

phase-180° 180°0°

Phase Between

0° to 180°

NO effects in

Conventional method &

proposed method

Undershoot

Comparison with Overshoot

Phase[deg]

Ove

rsho

ot vo

lta

ge

[mV

]

phase

-180° 180°0°

Phase Between

-180° to 0°

NO effects in

Conventional method

and proposed method

Overshoot

Comparison with Overshoot

Phase[deg]

Ove

rsho

ot vo

lta

ge

[mV

]

phase

phase

-180°

-180° 180°

180°0°

0°

proposed

conventional

Phase Between

0° to 180°

Conventional method



occurred

proposed method


Inductance current rises down

at moment

Overshoot

Comparison with Clock Frequency(1)

Phase[deg]

Un

de

rsh

oot vo

lta

ge

[mV

]

phase

phase

-180°

-180° 180°

180°0°

0°

Undershoot

proposed

proposed

Phase -100°

When the load current occur,

inductance current rises up at

moment

Phase 90°



occurred

Phase Between 0° to 180°

No effect

Comparison with Clock Frequency(2)

Phase[deg]

Ove

rsh

oo

t vo

lta

ge

[mV

]

phase

phase

-180°

-180° 180°

180°0°

0°

Overshoot

proposed

proposed

Phase Between -180° to 0°

No effect

Phase -90°



moment

Phase 90°



occurred

Comparison with Load current(1)

phase

phase

-180°

-180° 180°

180°0°

0°

Undershoot

proposed

proposed

Phase[deg]

Und

ers

hoot vo

lta

ge

[mV

]

Phase Between 0° to 180°

No effect

Phase -100°



moment

Phase 90°



occurred

Comparison with Load current(2)

phase

phase

-180°

-180° 180°

180°0°

0°

Overshoot

proposed

proposed

Phase[deg]

Ove

rsho

ot vo

lta

ge

[mV

]Phase Between -180° to 0°

No effect

Phase -90°



moment

Phase 90°



occurred

Result of conventional & proposed

89% 87%

■ Conventional ■ proposed

Voltage [

V]

Results with frequencies

88% 80% 73% 88% 82% 79%

■ Conventional ■ proposedUndershoot Overshoot

Voltage [

V]

Results with load currents

90% 71% 88% 79%

■ Conventional ■ proposed

Voltage [

V]

Outline



3. Approach



6. Conclusion


Summary

• Delay time suppression

when load current occur, high-pass filter

differentiates signal, amplifies, turns on

transistor power switch immediately

• Proposed Buck DC/DC converter output voltage

- undershoot/overshoot decreases approximately 80%

- verification of calculations & simulations results

• Results Confirmed also in following

- regulate clock frequency

- undershoot/overshoot voltage with phase

- load current range


Thanks for your attendance

of my speech


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Delay-time Suppression Technique for DC/DC Buck Converter Using Voltage Mode … · 2017. 11....

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Transcript of Delay-time Suppression Technique for DC/DC Buck Converter Using Voltage Mode … · 2017. 11....