Degradation Effects in A-Si:H Thin Film Transistors and Their Impact on Circuit Performance D.R....
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Transcript of Degradation Effects in A-Si:H Thin Film Transistors and Their Impact on Circuit Performance D.R....
Degradation Effects in A-Si:H Thin Film Transistors and Their Impact on
Circuit Performance
D.R. Allee, L.T. Clark, R. Shringarpure, S.M. Venugopal, Z.P. Li, and E.J. Bawolek
Flexible Display CenterArizona State University
FDC
2
Purpose
• Review Degradation Mechanisms of a-Si:H TFTs in Light of Recent Experiments
• Highlight Similarities to NBTI
• Determine Impact of Degradation on Active Matrix Backplanes
• Determine Impact of Degradation on General Digital a-Si:H Circuitry
• Potential Applications of Flexible a-Si:H Systems
3
Outline
• Introduction
• A-Si:H Thin Film Transistors
• Degradation of A-Si:H TFTs– Localization of Degradation– Threshold Voltage Recovery
• Impact on Circuit Performance– Degradation of Displays & Digital Logic– Circuit Simulator Incorporating Vth Shift
• Similarities to NBTI
• Conclusions
4
Introduction
• Flexible Displays– Provide Situational
Awareness– Lightweight– Rugged– Portable– Low Power– Daylight Readable
SilverGirl_SS_3_16x9.wmv
5
A-Si:H TFT Performance180C Process
Parameter Value
Yield 100%
Saturation Mobility
0.8 cm2/V-s
ON/OFF
Ratio2 x 108
Threshold Voltage
1.3 V
Hysteresis 1.1 V
Subthreshold Slope
0.58
Typical Vdd 20VVGS(V)
6
A-Si:H TFT Density of States
• Band Tail States– Weak Si-Si Bonds
• Deep States– Dangling Bonds– Amphoteric - 0,1,2
electrons– Mapped to Single Electron
Density of States• Trap States Must Fill Before
Significant Drain Current
Deep StatesAcceptors Donors
Exte
nded
Val
ence
Ban
d St
ates
Exte
nded
Con
duct
ion
Ban
d St
ates
Band Tail States
Energy Band-gap
Ev Ec
VG > VT0≤ VG ≤ VT
VG = VFB
Full Donors
Empty Acceptors
EF EF EFFm
Fm
Fm
Trapped Carriers (QT)
Free Carriers (Qn)
EV
EC EC EC
EVEV
SiNx SiNx SiNxA-Si:H A-Si:H A-Si:H
qΦsΦ
ms
Al Al Al
7
Degradation of A-Si:H TFTs
• A-Si:H TFTs Age with Voltage on the Gate
• Mechanisms– Creation of Defect States– Charge Injection into
Gate Insulator• Threshold Voltage Rise is
Proportional to– Inversion Charge– Time to ~0.3 Power
• Effect is Not Small!• Shift Common to all a-
Si:H Processes• Shift More Severe for
Low Temperature Processes
-3
-2
-1
0
1
2
3
4
5
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time (seconds)
Thr
esho
ld V
olta
ge S
hift
(V
) _
VGS=20V,VDS=0V
VGS=20V,VDS=10V
VGD= –40V,VDS=10V
VGD= –30V,VDS=0V
b
.nβA
GS DS th,0thE
ΔV t A exp t V ηV -VkT
8
Localization of Degradation
• Channel Charge Induces Defect Creation
• Linear Mode Stress Damages Entire Channel
• Saturation Mode Stress Does Not Damage Near Drain
• After Saturation Mode Stress– Reverse Linear IDS
‘Sees’ More Damage– Reverse Saturation IDS
‘Sees’ Less Damage
Nit
Nit
Gate
Source
Drain
Gate
Source
Drain
(a) Linear mode stress affects channel length L
(b) Saturation mode stress extent limited to L -∆L
∆L
a-Si:H Channel
a-Si:H Channel
Gate
Drain
Drain
Gate
Source
Source
Drain
(a) Reverse linear IDS sees all of Vth degradation
(b) Reverse saturation IDS increases with VDS screening the damage at pinch-off (L-∆L)
a-Si:H Channel
a-Si:H Channel∆L
9
Localization of Degradation
• After Linear Mode Stress IDS is Identical– In Both Linear
and Saturation Regimes
– For Both Forward and Reverse Configurations.
• Damage is Uniform Throughout Channel
0.E+00
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
7.E-06
0 5 10 15 20VDS (V)
I DS (
A)
Unstressed
Stressed 100 s (Reverse)
Stressed 100 s (Forward)
Stressed 5000 s(Reverse/Forward)
10
Localization of Degradation
0.E+00
1.E-06
2.E-06
3.E-06
4.E-06
5.E-06
6.E-06
0 5 10 15 20VDS (V)
I DS (
A)
Unstressed
Stressed 100 s(Reverse)
Stressed 100 s (Forward)
Stressed 5000 s (Reverse)
Stressed 5000 s (Forward)
• After Saturation Mode Stress IDS is NOT Identical– IDS Increases
Only in Saturation Regime for Reverse Configuration
• Damage Must be Confined to Channel Interface.
11
Threshold Voltage Recovery• There is an
apparent recovery of threshold voltage with several hours of no applied voltages.
12
Threshold Voltage Recovery
• However, the threshold voltage quickly collapses to where it would have been without rest.
13
Threshold Voltage Recovery• However, the
threshold voltage quickly collapses to where it would have been without rest.
• This plot removes rest time.
• Degradation of 5 latches are indistinguishable.
14
Impact on Circuit Performance
• Lifetime of Display Backplanes– ~10,000 hours
• Lifetime of Digital Logic– ~ a few days!
Source Drivers
Source Drivers
Heat Seal connector
Heat Seal connector
16x8 EPD
16x8 EPD
Integrated a-Si:H Source Driver
15
Degradation of Digital Logic
• Digital circuits must have positive static noise margin to operate.
• Static noise margin eventually drops to zero with increasing threshold voltage.
IN
OUT
VDD
ML
MD
16
Degradation of Digital Logic
• Evolution of Noise Margin with Time Under Constant Gate Voltage Stress
• Measurements (dot), Simulations (asterix) and Analytical Equations (circle) Agree Reasonably Well
• Digital Circuit Lifetime Can Be Simply Expressed:
1
2 1
2DD TO
GSL GSD TO
V VT
V V V
17
Circuit Simulator Incorporating Vth Shift
• Can Now Model Circuit Performance Where Each TFT ‘Ages’ Differently– Effect of
threshold voltage shift on a 10-transistor digital latch.
– NGSpice simulation results match experiment reasonably well.
A2
A1 A3
A4 A6 A8
A5 A7
VD D VD D VD DVD D
O 1
O 2
VIN
O 1
A1 0
A9
O 2
VO UT
0
2
4
6
8
10
12
14
16
18
20
1 101 201 301 401 501Time Samples (1 sample=10us)
Lat
ch O
utpu
t (V
)
0
5
10
15
20
25
30
Vin
(V
)
VinVth degradation model tracks measured output of latch stressedfor 0,1,2 and 3 hrs respectively
dtVVVtKT
EAtAge n
tDSGSA
i
i
1-i
t
t
exp /0,
stopstop
ageaget tAge
t
ttV
18
Similarities to NBTI
• Increased Vth (magnitude) with Gate Voltage Stress
• Power Law Time Dependence, ~0.25
• Mechanism: Stress Induced Interface Traps
– Breaking of H Passivated Dangling Si Bonds
– Both H+ and H2O Proposed As Attacking Species
• Some Recovery Possible with High T Anneals
– But Recovery Not Thought to be Permanent
• Deuterium Passivated Bonds Reduce NBTI
Figure from D.K. Schroder, with permission
19
Conclusions
• Degradation of a-Si:H Rooted in Fundamental Physics
• Strong Similarities to NBTI• Degradation Does Not Limit Practical
Lifetimes of Active Matrix Backplanes• Viability of Other Digital a-Si:H Circuits
Will Depend on Specifications– Integrated Source Drivers for Displays– Flexible Active Medical Bandage
• Need for Accurate Models and Simulation Tools