Digital Systems Design - EL 3242

Chapter 3

Arithmetic Circuit Design: Adder

Prepared by Mamush Tekle

Defence University, College of Engineering

Department of Electronics Engineering

Contents

• Design of serial adder with accumulator,

• BCD adder,

• BCD adder VHDL code,

• 32 bit adder,

• 32-bit adder VHDL code.

Design of serial adder with accumulator • The following figure shows a block diagram of serial adder with accumulator.

Fig. Block diagram of serial adder with accumulator

Cont’d

• The two shift registers are used to hold the 4-bit numbers to be added, X and Y.

• The X register serves as an accumulator and the Y register serves as an addend register.

• When the addition is completed, the contents of the X register are replaced with the sum of X and Y.

• The addend register is connected as a cyclic shift register so that after shifting four times it is back in its original state, and the number Y is not lost.

• The box at the left end of each shift register shows the inputs: Sh (shift signal), SI (serial input), and Clock. When Sh = 1 and an active clock edge occurs, SI is entered into x3 (or y3) at the same time as the contents of the register are shifted one place to the right.

Cont’d

• The additional connections required for initially loading the X and Y registers and clearing the carry flip-flop are not shown in the block diagram.

• At each clock time, one pair of bits is added.

• Because the full adder is a combinational circuit, the sum and carry appear at the full adder output after the propagation delay.

• When Sh = 1, the falling clock edge shifts the sum bit into the accumulator, stores the carry bit in the carry flip-flop, and rotates the addend register one place to the right.

• Because Sh is connected to CE on the flip-flop, the carry is only updated when shifting occurs.

Operation of Serial Adder • Shifting occurs on the falling clock edge when Sh = 1.

• In the next figure, t0 is the time before the first shift, t1 is the time after the first shift, t2 is the time after the second shift, etc.

• Initially, at time t0, the accumulator contains X and the addend register contains Y.

• Because the full adder is a combinational circuit, x0, y0, and c0 are added independently of the clock to form the sum s0 and carry c1.

• When the first falling clock edge occurs, s0 is shifted into the accumulator and the remaining accumulator digits are shifted one position to the right.

• The same clock edge stores c1 in the carry flip-flop and rotates the addend register right.

• The next pair of bits, x1 and y1, are now at the full adder input, and the adder generates the sum and carry, s1 and c2, as seen in the Figure (b).

• The second falling edge shifts s1 into the accumulator, stores c2 in the carry flip-flop, and cycles the addend register right. Bits x2 and y2 are now at the adder input, as seen in Figure (c), and the process continues until all bit pairs have been added, as shown in Figure (e).

• The table shows a numerical example of the serial adder operation. Initially, the accumulator contains 0101 and the addend register contains 0111.

Cont’d

Design of control circuit • A control circuit for a digital system is a sequential network that outputs a

sequence of control signals.

• These signals cause operations such as addition and shifting to take place at appropriate times.

• The control circuit for the adder must now be designed so that after receiving a start signal, the control circuit will put out four shift signals and then stop.

• The next figure shows the state graph and table for the control circuit.

• The circuit remains in S0 until a start signal is received, at which time the circuit outputs Sh = 1 and goes to S1.

• Then, at successive clock times, three more shift signals are put out. It will be assumed that the start signal (St) is terminated before the circuit returns to state S0 so that no further output occurs until another start signal is received.

• Dashes appear on the graph because once S1 is reached, the circuit operation continues regardless of the value of St.

• Starting with the state table and using a straight binary state assignment, the control circuit equations are derived.

Cont’d

Half Adder and Full Adder Half Adder

A B Sum Carr

y

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Sum AB AB A B

Carry AB

Full Adder

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

VHDL Code for Full Adder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity FullAdder is Port ( A : in bit; B : in bit; Cin : in bit; S : out bit; Cout : out bit); end FullAdder;

Cont’d

architecture behavioral of FullAdder is

begin

S <= A XOR B XOR Cin ;

Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

end behavioral;

Implementation of a Full adder using two half adders

• It is possible to implement a full adder using 2 full adders and 1 OR gate by connecting as shown below in the figure.

4-bit Binary Adder using Full Adder

VHDL Code for structural description of 4-bit Adder

library IEEE; use IEEE.STD_LOGIC_1164.ALL entity adder4 is port(A, B: in bit_vector(3 downto 0); Ci: in bit; -- inputs S: out bit_vector(3 downto 0); Co: out bit); -- outputs end adder4; architecture structure of adder4 is component FullAdder port(X, Y, Cin: bit; -- inputs Cout, Sum: out bit); -- outputs end component; signal C: bit_vector(3 downto 1);

Cont’d

begin

FA0: FullAdder port map(A(0), B(0), Ci, C(1), S(0));

FA1: FullAdder port map(A(1), B(1), C(1), C(2), S(1));

FA2: FullAdder port map(A(2), B(2), C(2), C(3), S(2));

FA3: FullAdder port map(A(3), B(3), C(3), Co, S(3));

end structure;

4-bit Parallel Adder

BCD Adder • When the sum of two digits is less than or equal to 9 then the ordinary 4-

bit adder can be used. • But if the sum of two digits is greater than 9 then a correction must be

added “I.e. adding 0110” • We need to design a circuit that is capable of doing the correct addition.

• The cases where the sum of two 4-bit numbers is greater than 9 are shown in the above table.

Cont’d

• The condition for a correction can be expressed by the Boolean function.

• Whenever S4=1 (sums greater than 15)

• Whenever S3=1 and either S2 or S1 or both are 1 (sums 10 to 15)

• The table can be expressed as:

X = S4 + S3 ( S2 + S1)

So, whenever X = 1 we should add a correction of 0110 to the sum.

0011

0101

0 1 0 0 0

0

0 0

1000

0000

Inputs:[A]=0101, [B]= 0011, Co=0

1 0 0 0

1

0110

0111

0 1 1 0 1

1

1 1

1101

0110

Inputs:[A]=0111, [B]= 0110, Co=0

0 0 1 1

1

Example

• Determine the inputs and the outputs when the above circuit is used to add 538 to 247. Assume a CARRY IN = 0

• Solution: • Represent the decimal numbers in BCD

247 = 0010 0100 0111

538 = 0101 0011 1000

Put these numbers in registers [A] and [B]

[A] = 0010 0100 0111

[B] = 0101 0011 1000

BCD Adder VHDL Code library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

entity BCDadder is

Port ( bcd1 : in std_logic_vector(3 downto 0);

bcd2 : in std_logic_vector(3 downto 0);

bcdcarryin : in std_logic;

bcdsum : out std_logic_vector(3 downto 0);

bcdcarryout : out std_logic);

end BCDadder;

Cont’d architecture Behavioral of BCDadder is

component adder4bit is

Port ( a : in std_logic_vector(3 downto 0);

b : in std_logic_vector(3 downto 0);

carryin : in std_logic;

sum : out std_logic_vector(3 downto 0);

carryout : out std_logic);

end component adder4bit;

signal s,x: std_logic_vector(3 Downto 0);

signal c,K : std_logic;

Cont’d begin

u1:adder4bit port map(a(3)=>bcd1(3),a(2)=>bcd1(2),a(1)=>bcd1(1),a(0)=>bcd1(0),

b(3)=>bcd2(3),b(2)=>bcd2(2),b(1)=>bcd2(1),b(0)=>bcd2(0),

carryin=>bcdcarryin,sum(3)=>s(3),sum(2)=>s(2),sum(1)=>s(1),sum(0)=>s(0),carryout=>c);

K <= (s(3)and s(2))or(s(3)and s(1))or(c);

x <= "0110" when k ='1' else

"0000";

u2 :adder4bit port map(a(3)=>s(3),a(2)=>s(2),a(1)=>s(1),a(0)=>s(0),b(3)=>x(3),b(2)=>x(2),b(1)=>x(1),b(0)=>x(0),carryin=>'0',

sum(3)=>bcdsum(3),sum(2)=>bcdsum(2),sum(1)=>bcdsum(1),sum(0)=>bcdsum(0),

carryout=>bcdcarryout);

end Behavioral;

32 bit adder • 32 bit adder can be constructed by connecting 32 full adders together in series as

shown below in the figure.

• The resulting circuit is called ripple-carry adder for adding two 32 bit operands.

• Since a full adder adds the three bits, xi, yi and ci, together, we need to set the first carry-in bit, co, to 0 in order to perform the addition correctly.

• Moreover, the output signal, cout, is a 1 whenever there is an overflow in the addition. The carry ripples from the least significant bit to the most significant bit.

• The delay of an N-bit ripple-carry adder is:

tripple = NtFA where tFA is the delay of a full adder. So, this method is slow.

Cont’d

• N-bit adders can also be constructed by connecting N full adders in series.

• Alternatively, 32 bit adder can be constructed by connecting 8 blocks of 4-bit parallel adder IC (74HC283) in series.

32-bit adder VHDL code

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity adder32 is port ( a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); sum : out std_logic_vector(31 downto 0); carry : out std_logic); end entity adder32;

Cont’d architecture behavioral of adder32 is signal temp : std_logic_vector(32 downto 0); begin process(a,b) begin temp <= ('0' & a) + ('0' & b); end process; sum <= temp(31 downto 0); carry <= temp(32); end behavioral;

Test bench wave form for the previous 32 bit adder VHDL Code

End of Chapter 3

Thank You