ST. ANNE’S COLLEGE OF ENGINEERING AND TECHNOLOGY

ANGUCHETTYPALAYAM, PANRUTI – 607 110

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERINGODD SEMESTER (JAN 2014 to MAY 2014)

LESSON PLAN

STAFF NAME : N.VENANCIA PUSHPARANI

SUBJECT : LINEAR INTEGRATED CIRCUITS

SUBJECT CODE : EC2254

YEAR/SEMESTER : II/IV

1. OBJECTIVES:

To enable the students to understand the fundamental concepts of of ICFabrication techniques,

OP-AMP, special IC’s and their applications, waveform generator, A/D and D/A converters

2. TEXT AND REFERENCES:

2.1. TEXT BOOKS:

1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.2. S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition.,Vikas Publishing House Pvt. Ltd, New Delhi, 20062.2. REFERENCES:3. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 20064. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002.5. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003.6. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6th Edition, TMH, 2003.7. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.8. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi, 20039. Donald D.Givone, Digital Principles and Design, TMH, 2003.10. Samir Palnitkar , Verilog HDL, Second edition , Pearson Education.

3. LESSON PLAN

S.NO. DATE TOPIC NAMEBOOKS TO BE

REFERRED

NO. OF PERIODS

UNIT – I MINIMIZATION TECHNIQUES AND LOGIC GATES

1.Boolean postulates and laws –De-Morgan’s Theorem- Principle of Duality

T1 1

2. Boolean expression –Minimization of Boolean T1 1

3. Minterm – Maxterm - Sum of Products (SOP) Product of Sums T1 1

4. Karnaugh map Minimization, Don’t care conditions T1 1

5. Quine-McCluskey method of minimization T1 1

6.AND, OR, NOT, NAND, NOR, Exclusive – OR and Exclusive – NOR

T1 1

7. Implementations of Logic Functions using gates, NAND, T1 1

8. Multi level gate implementations, Multi output gate T1 1

9. TTL and CMOS Logic and their characteristics – Tristate gates. T1 1

UNIT-II COMBINATIONAL CIRCUITS

1. Design procedure – Half adder – Full Adder T1 1

2. Design procedure –Halfsubtractor –Full T1 1

3. Parallel binary adder, parallel binary Subtractor T1 1

4. Fast Adder Carry Look Ahead adder T1 1

5. Serial Adder/Subtractor. BCD adder T1 1

6. Binary Multiplier – Binary Divider T1 1

7.Multiplexer/ Demultiplexer, Encoder / decoder T1 1

8.Parity checker, Parity generator

T1 1

9. Code converters T1 1

UNIT – III ANALOG MULTIPLIER AND PLL

1. Emitter coupled transistor pair T1 1

2. Gilbert multiplier cell T1 1

3. Variable transconductance technique T1 1

4. Analog multiplier IC’s and their applications T1 1

5. Operation of the basic PLL, Voltage controlled oscillator R1 1

6. Closed loop analysis T1 1

7. Monolithic PLL IC 565 T2 1

8. Voltage controlled oscillator

9. Application of PLL for AM detection, FM detection T2 1

10.FSK Modulation, demodulation and frequency synthesizing T2 1

UNIT – IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS

1. Analog and digital data conversions T1 1

2. D/A converter T1 1

3. D/A converter Types T1 1

4. High speed sample-and-hold circuits T1 1

5. D/A converter T1 1

6. A/D converters, D/A converter types T1 1

7. A/D conversion T1 1

8. Over-sampling A/D converters. T1 1

UNIT-V WAVEFORM GENERATORS AND SPECIAL FUNCTION ICs

1. Sine-wave generators, Saw-tooth wave generator T2 1

2. Multivibrators and triangular wave generator T2 1

3. ICL8038 function generator T2 1

4. Timer IC 555 R2 1

5. IC voltage regulators and types T1 1

6. Switched capacitor filter IC MF10 T1 1

7. Frequency to voltage and voltage to frequency converters T1 1

8. Audio, Video power amplifier R3 1

9. Isolation,Opto-couplers and Fibre optic IC R4 1

4. TEST PORTIONS:S.NO TEST NO PORTIONS

1 CIA I UNIT I & II

2 CIA II UNIT III & IV

3 MODEL ALL UNITS

STAFF IN-CHARGE HOD