EXPERIMENT NO.4

Aim

To implement VHDL code for 1X2,2X4 and 3X8 decoder.

Tool required

Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

Theory

A decoder is a device which does the reverse of an encoder, undoing the encoding so that the

original information can be retrieved. The same method used to encode is usually just reversed in

order to decode.

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic

circuit that converts coded inputs into coded outputs, where the input and output codes are

different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder

to function, otherwise its outputs assume a single "disabled" output code word. Decoding is

necessary in applications such as data multiplexing, 7 segment display and memory address

decoding.

Fig.(4.1)

1X2 decoder

A 1X2 decoder consists of 1 input and 2 outputs.

Truth Table

Input

(A)

Outputs

D0 D1

0 1 0

1 0 1

Table(4.1a)

Logic Equation

D0=A

D1=A’

2X4 decoder

A 2X4 decoder consists of 2 inputs and 4 outputs.

Truth Table

Input

(AB)

Outputs

D0 D1 D2 D3

00 1 0 0 0

01 0 1 0 0

10 0 0 1 0

11 0 0 0 1

Table(4.2b)

Logic Equation

D0=A’.B’

D1=A’.B

D2=A.B’

D3=A.B

3X8 decoder

A 3X8 decoder consists of 3 inputs and 8 outputs.

Truth Table

Inputs (ABC)

Outputs

D0 D1 D2 D3 D4 D5 D6 D7

000 1 0 0 0 0 0 0 0

001 0 1 0 0 0 0 0 0

010 0 0 1 0 0 0 0 0

011 0 0 0 1 0 0 0 0

100 0 0 0 0 1 0 0 0

101 0 0 0 0 0 1 0 0

110 0 0 0 0 0 0 1 0

111 0 0 0 0 0 0 0 1

Table.(4.3c)

Logic Equation

D0=A’.B’.C’ D1=A’.B’.C D2=A’.B.C’ D3=A’.B.C D4=A.B’.C’ D5=A.B’.C D6=A.B.C’ D7=A.B.C

VHDL code for 1X2 decoder

Using data flow modelling

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY onex2decoder IS port(a:in std_logic; d0,d1:out std_logic);END ENTITY onex2decoder;

--ARCHITECTURE dec_data OF onex2decoder ISBEGIN d0<=not(a); d1<=a;END ARCHITECTURE dec_data;

Using behavioural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY 1x2decoder IS port(a:in std_logic; d0,d1:out std_logic);

END ENTITY 1x2decoder; ARCHITECTURE beh_dec OF 1x2decoder IS BEGIN process(a) begin d0<=a’; d1<=a; end process; END ARCHITECTURE beh_dec;

Using structural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY 1x2decoder IS port(a:in std_logic; d0,d1:out std_logic); END ENTITY 1x2decoder; -- ARCHITECTURE struc_dec OF 1x2decoder IS component not2 port(a:in std_logic; y:out std_logic); end component not2; signal s1:std_logic; begin x1:not2 port map(a,s1); x2:port map(s1,d0);x3:port map(a,d1); END ARCHITECTURE struc_dec;

Output

VHDL code for 2X4 decoder

Using data flow modelling

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY 2x4decoder IS port(a,b:in std_logic; d0,d1,d2,d3:out std_logic);END ENTITY 2x4decoder;

--ARCHITECTURE dec_data OF 2x4decoder ISBEGIN d0<=not(a) and not(b); d1<=not(a) and b; d2<=a and not(b); d3<=a and b;END ARCHITECTURE dec_data;

Using behavioural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY 2x4decoder IS port(a,b:in std_logic; d0,d1,d2,d3:out std_logic); END ENTITY 2x4decoder;

-- ARCHITECTURE beh_dec OF 2x4decoder IS BEGIN process(a,b) variable v1,v2,v3,v4:std_logic begin v1:=not(a) and not(b);v2:=not(a) and b;v3:=a and not(b);v4:=a and b; d0<=v1; d1<=v2;d2<=v3;d3<=v4; end process; END ARCHITECTURE beh_dec;

Using structural modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY 2x4decoder IS port(a,b:in std_logic; d0,d1,d2,d3:out std_logic); END ENTITY 2x4decoder;

-- ARCHITECTURE struc_dec OF 2x4decoder IS component and2 port(a,b:in std_logic;

y:out std_logic); end component and2; component not2 port(a:in std_logic; y:out std_logic); end component not2; signal s1,s2:std_logic; begin x1:not2 port map(a,s1); x2:not2 port map(b,s2); x3:and2 port map(s1,s2,d0); x4:and2 port map(s1,b,d1); x5:and2 port map(a,s2,d2); x6:and2 port map(a,b,d3); END ARCHITECTURE struc_dec;

Output:

VHDL code for 3X8 decoder

Using data flow modelling

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY twox4decoder IS port(a,b,c:in std_logic; d0,d1,d2,d3,d4,d5,d6,d7:out std_logic); END ENTITY twox4decoder;

-- ARCHITECTURE dec_data OF twox4decoder IS BEGIN d0<=not(a) and not(b) and not(c); d1<=not(a) and not(b) and c; d2<=not(a) and b and not(c); d3<=not(a) and b and c; d4<=a and not(b) and not(c); d5<=a and not(b) and c; d6<=a and b and not(c); d7<=a and b and c; END ARCHITECTURE dec_data;

Using behavioural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;

ENTITY threex8decoder IS port(a,b,c:in std_logic; d0,d1,d2,d3,d4,d5,d6,d7:out std_logic); END ENTITY threex8decoder;

-- ARCHITECTURE beh_dec OF threex8decoder IS BEGIN process(a,b,c) variable v1,v2,v3,v4,v5,v6,v7,v8:std_logic; begin

v1:=not(a) and not(b)and not(c); v2:=not(a) and not(b)and c; v3:=not(a) and b and not(c); v4:=not(a) and b and c; v5:=a and not(b) and not(c); v6:=a and not(b) and (c); v7:=a and b and not(c); v8:=a and b and c; d0<=v1; d1<=v2; d2<=v3; d3<=v4; d4<=v5; d5<=v6; d6<=v7; d7<=v8; end process; END ARCHITECTURE beh_dec;

Using structural modelling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY threex8decoder IS port(a,b,c:in std_logic; d0,d1,d2,d3,d4,d5,d6,d7:out std_logic); END ENTITY threex8decoder; --

ARCHITECTURE struc_dec OF threex8decoder IS component and3 port(a,b,c:in std_logic; y:out std_logic); end component and3; component not2 port(a:in std_logic; y:out std_logic); end component not2;

signal s1,s2,s3:std_logic;

begin x1:not2 port map(a,s1); x2:not2 port map(b,s2); x3:not2 port map(c,s3); x4:and3 port map(s1,s2,s3,d0); x5:and3 port map(s1,s2,c,d1); x6:and3 port map(s1,b,s2,d2); x7:and3 port map(s1,b,c,d3); x8:and3 port map(a,s2,s3,d4); x9:and3 port map(a,s2,c,d5); x10:and3 port map(a,b,s3,d6); x11:and3 port map(a,b,c,d7); END ARCHITECTURE struc_dec;

Output:

Result- The VHDL code for 1x2,2x4 and 3x8 Decoders were implemented and simulated

successfully