DD 2 Features and benefits NXH5104 - NXP Semiconductors · – VDD(IO) supply range: VDD to 2.6 V...

NXH51044 Mbit Serial SPI EEPROMRev. 6.3 — 3 July 2019 Product data sheet

1 General description

The NXP Semiconductors NXH5104 is a 4 Mbit serial electrically erasable andprogrammable read-only memory (EEPROM). It provides byte level and page level serialEEPROM functions, sector level protection and power-down functions. The device hasbeen developed for low-power low-voltage applications and is provided with a serialperipheral interface (SPI) compatible interface.

2 Features and benefits

• Compact wafer-level chip-scale package (WLCSP) package• – 7.8 mm2, 380 μm thick

– 13 bumps with 400 μm pitch• Integrated power management unit (PMU)• – VDD supply range 1.0 V to 2.0 V

– VDD(IO) supply range: VDD to 2.6 V– Direct operation from ZnAir, NiMH, Silver-Zinc batteries– Active peak current limiting

• Low current consumption• – Average power down current < 5 μA

– Average read current 0.6 mA (VDD = VDD(IO) = 1.8 V, FSPI =5 MHz)– Average write current 0.7 mA (VDD = VDD(IO) = 1.8 V, FSPI = 5 MHz)

• Low-power CMOS technology• Auxiliary supply voltage enabling direct LED drive• Self-timed program cycle• – 256 byte page write buffer

– Partial page write allowed• Write protect• – Quarter, half or entire memory array• Serial peripheral interface (SPI)• – Speed up to 5 MHz for 1.2 V signaling level

– Speed up to 10 MHz for 1.8 V signaling level– SPI mode 0 (0,0) and 3 (1,1) support– SPI 3-wire support for SPI mode 0

• Fixed high supply mode for faster start-up• Space-saving 2.80 mm × 2.74 mm wafer-level chip-scale package (WLCSP)• Highly integrated: 1 external cap• High reliability• – 10-year data retention

– 500 000 program cycles– Wear-out management

NXP Semiconductors NXH51044 Mbit Serial SPI EEPROM

NXH5104 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved.

Product data sheet Rev. 6.3 — 3 July 20192 / 37

• Operating temperature −20 °C to +85 °C• Support for different supply configurations• Device ID and Unique ID• Pb-free and RoHS compliant

3 Ordering informationTable 1. Ordering information

PackageType number

Name Description Version

NXH5104UK/A1 WLCSP13 wafer level chip-scale package; 13 bumps;2.74 mm × 2.80 mm × 0.38 mm

SOT1461-1

4 Block diagram

WRS aaa-010722

CS

SPISLAVE

DC-to-DCCONVERTERS

I/O supply

VDD(IO) VDD

VSS

internalsupplies

+ 8 x 4 kB RESERVED AREA: REDUNDANCY,UNIQUE ID, TYPE ID, NON-VOLATILE SETTINGS

NXH5104

SCK WAKE(I/O at VDD)

VAUX

VDD(EE)

EEPROMCONTROLLERWP

SI

SO

HOLD 64 kB SECTOR 64 kB SECTOR

64 kB SECTOR 64 kB SECTOR



4M

bitu

sera

rea

Figure 1. Block diagram




5 Pinning information

5.1 Pinning

aaa-010723

VAUX

VDD(IO)

VSS

VDD(EE)

VDD

WAKE

1

A

B

C

D

E

F

2 3 4 5 6

SI

SO

WP

HOLD

SCK

CS WRS

Figure 2. NXH5104 13 bump SPI package configuration (bottom view)

5.2 Pin description

Table 2. Bump allocation tableBump Symbol Type Description

Supply

B6 VDD PWR primary supply input. The VDD pin is used to supply thesource voltage to the device. Operations at invalid VDDvoltages may produce spurious results and should not beattempted.

E6 VDD(IO) PWR input/output supply input. The VDD(IO) pin is used tosupply the IO voltage to the device and hence defines thesignaling voltage of the SPI slave interface. The voltagelevel of VDD(IO) must be equal or higher than VDD.

C6 VDD(EE) PWR EEPROM array supply output. In wide range supply mode,this pin requires a 470 nF decoupling capacitor. In fixedhigh supply (FHS) mode, this pin must be pulled HIGH witha 1 MΩ resistor to VDD.

F6 VAUX PWR auxiliary supply output. This pin provides a configurablevoltage source for supplying other devices. Section 6.3describes this functionality. A separate application note(Ref. 2) provides more detailed usage information.

Ground

D6 VSS GND analog/digital ground. Connect to the system GND.




Bump Symbol Type Description

Configuration

D1 WP DI write-protect pin. This pin is used to prevent inadvertentwrites to the EEPROM array. When connected to GND, thedevice is write protected. When connected to VDD(IO), thedevice is not write protected.

A2 WRS DI wide-range supply pin. This pin configures the supplymode of the device. When connected to VDD(IO), thechosen supply mode is the wide range supply mode. Whenconnected to GND, the chosen supply mode is the fixedhigh supply mode. In this latter mode, a higher minimumvoltage is required on VDD, as described in Section 6.4.

Control

A6 WAKE DI wake-up/power-down control input. To disable thisfunctionality, the WAKE pin must be connected to GND.The SPI slave chip select input can then be used towake up the device. To enable the WAKE functionality,the WAKE pin must be actively driven and may not beleft unconnected nor floating. The input voltage level isreferenced to VDD.

SPI

A1 CS DI SPI slave chip select.• When the device is active, asserting the CS pin enables

the device SPI interface. A HIGH-to-LOW transitionon the CS pin initiates an SPI transaction. A LOW-to-HIGH transition ends the transaction. When the CSsignal is deasserted, the SPI SO output pin is in a HIGHimpedance state and commands issued to the device arenot accepted. When the device is active, the signalinglevel is referenced to VDD(IO).

• When the device is in power down, asserting the CS pinwakes up the device. Keeping the CS pin asserted whilethe device is waking-up, can stall the booting process.So, deassert the pin after minimum 200 ns.

see Section 6.2 for more information.To wake up the device, the input level is referenced to VDD.

E1 SO DO SPI slave serial data output. The SO pin is used to shiftdata out from the device. Data on the SO pin is alwaysclocked out on the falling edge of SCK. The SO pin is in ahigh impedance state whenever the device is not selected.The signaling level is referenced to VDD(IO).For EMI, it isrequired to pull up the SO line at some place in the system:either the SPI master has an internal weak pull-up, eitheran external pull-up resistor is required.

F1 SI DI SPI slave serial data input. The SI pin is used the shiftopcodes, addresses, and data into the device and latchedon the rising edge of SCK. The signaling level is referencedto VDD(IO).

B1 SCK DI SPI clock input.




Bump Symbol Type Description

C1 HOLD DI SPI HOLD. The HOLD pin can be used to pause an on-going SPI transaction. More information on usage can befound in Section 6.1.1. The signaling level is referencedto VDD(IO). To disable this functionality, the HOLD pin mustbe connected to VDD(IO).

6 Functional description

6.1 SPI interface

The NXP Semiconductors NXH5104 acts as a slave device on the serial peripheralinterface (SPI) bus. It supports mode 0 (0,0) and mode 3 (1,1) transfers at standardclock speeds up to 5 MHz. It also supports high-speed operation up to 10 MHz whenVDD(IO) exceeds 1.8 V. Incoming data on the SI pin is latched on the rising edge of SCK.Outgoing data output on the SO pin is output on the falling edge of SCK. A leading ortrailing falling edge of SCK is discarded.

aaa-010725

0SI 123 X4567

SCK

CS

LSBMSB

7SO 6 5high impedance 4 3 2 1 0 X

X

Figure 3. SPI mode 0/3

Transactions are byte-oriented, counting an integer multiple of 8-bit words, whereby themost significant bit (MSB) is transmitted first, least significant bit (LSB) last. The masterinitiates a transaction by asserting CS low and terminates it by de-asserting CS high,even if it is a single-byte command.

The command byte is the first byte transmitted by the master and received by the slaveon the SI line after asserting low the CS pin.

6.1.1 SPI transaction hold

A HOLD input is provided as an extension to the SPI interface. It enables the host tosuspend an ongoing transaction such as performing a high priority transaction withanother slave device.

While HOLD is asserted low, the device releases the SO line to a high impedance stateand discards any transitions on SCK and SI lines. The CS line however, must remainasserted. When the HOLD input is deasserted high, the suspended transaction resumes.




aaa-010726

0SI 1234567

SCK

HOLD

7SO 6 5 4 3 2 1 0 X7 6 5 4 3 2 1 0 7

0 0

0

1234567X X

CS

X

ongoing transaction suspended 2nd part of transaction

Figure 4. SPI transaction hold

When SCK is stable, the HOLD input must be asserted low. It must be deasserted duringthe same clock phase as it was asserted.

The HOLD input must be asserted after the last bit of a byte has been asserted on SI(see Figure 4).

If this feature is not used, the HOLD input must be tied to VDD(IO).

6.1.2 Overview commands

The NXP Semiconductors NXH5104 uses 8-bit commands. For some of thesecommands, the device needs time to execute the action during which no new commandscan be serviced. These commands are referred to as extended operation commands(EOC). For instance, the WRITE command is an EOC. The WRITE command triggers anerase-program cycle during which other commands are not serviced.

The host must poll readiness by issuing RDSR commands and must observe if the RDYbit is asserted low.

If an invalid command byte is received, the command is ignored and the SO line remainsin a high impedance state.

There are two types of write accesses: volatile and persistent. When a setting is writtenvolatile, the change takes effect, but this setting reinitializes with its default value after adevice power cycle. When a setting is written persistent, the change takes effect and theupdated value is automatically loaded after a device power cycle.

Table 3. SPI command set overviewCommand Value Description EOC Reference

WRSR 01h write status register yes Table 12

WRITE 02h write data bytes to memory array yes Table 7

READ 03h read data bytes from memory array no Table 4

WRDI 04h disable write operations no Table 9

RDSR 05h read status register no Table 17

WREN 06h enable write operations no Table 8

RDID 83h read device ID and unique ID no Table 18

RDR F9h read response no Table 20

STBY E0h standby command yes Table 26




Command Value Description EOC Reference

SLEEP E1h sleep command yes Table 25

PWDN E2h power-down command yes Table 24

VWXSR E3h volatile write of extended status register yes Table 15

PWXSR E4h persistent write of extended statusregister

yes Table 16

VAUXVW E5h volatile write of auxiliary supplyconfiguration register (VAUXCFG)

yes Table 27

VAUXPW E6h persistent write of auxiliary supplyconfiguration register (VAUXCFG)

yes Table 28

VAUXR E7h prepares a read auxiliary supplyconfiguration register (VAUXCFG). Toread the auxiliary supply configurationregister value, use the RDR (ReadResponse) command.

yes Table 29

WOIR E8h prepares a read of wear out statusregister. To read the wear-out statusregister value, use the RDR (ReadResponse) command.

yes Table 21

RVDD E9h prepares a read of the VDD supplyvoltage level. To read back the prepareddata, use the RDR (Read Response)command.

yes Table 23

6.1.3 SPI read operation (READ)

A read operation of the memory array is initiated when the SPI master issues a READcommand, followed by the sector byte and the 16-bit address. The latter defines theoffset within the chosen sector.

The NXP Semiconductor NXH5104 contains eight sectors; hence the SA field contains 3bits. The remaining most-significant bits of the sector byte must be zero!

aaa-010727

SI SA address high byte address low byte

MSB LSB

MSB LSB

0

select sector set start address read data bytesREAD command

0 0 0 0 0 0 0 0 00 1 1

SO

X X

first data byte last data byte

Figure 5. SPI read operation

Immediately following the last address byte (READ command), the device starts drivingthe SO line. It transmits consecutive data bytes read from the memory array, starting atthe selected memory location, until the CS input is asserted HIGH.

During read operations, the internal address counter auto-increments. What happens ata sector boundary depends on the setting of the RAWMODE field of the extended statusregister (see Table 14). When RAWSEC is chosen, the address automatically wraps atthe sector boundary. When RAWFULL is chosen, the address automatically incrementsbeyond the sector boundary to the next sector.




If a previous program operation is in progress, the memory read/write operation isprohibited (treated as an invalid command).

A READ command is only allowed on sectors which are in power-up mode.

Table 4. SPI READ commandByte Access Command Value Description

0 W READ 03h read data bytes from memory

1:3 W SPI_AR - address register

4:... R DATA - data bytes

6.1.4 SPI write protection

To prevent inadvertent writes to the memory array and status register, software andhardware protection mechanisms are included in the device.

The following protection is available for writing to the EEPROM memory array:

• The write enable bit (WEN) must be first set by issuing a write enable (WREN)command. It is cleared by issuing a write disable (WRDI) command. The write enablebit is also automatically cleared at power-up, after each WRITE command, and whenthe status register is written (WRSR or PWXSR).

• The corresponding sector protection bit SP(n) must be disabled.• If a program operation is still in progress (RDY = 1), writes are prohibited.

Table 5. SPI memory array write protectionRDY WEN WREN WP SP(n) WRITE command [1]

1 X X X X prohibited

X 0 X X X prohibited

X X X X 1 prohibited

0 1 X X 0 allowed

[1] When prohibited, the WRITE command is treated as an invalid command.

The following protection is available for writing to the status register:

• The write enable bit (WEN) must be set by issuing a write enable (WREN) command. Itis cleared by issuing a write disable (WRDI) command. It is also automatically clearedat power-up, after each WRITE instruction and when the status register is written(WRSR or PWXSR).

• If the nonvolatile WPEN bit is set and the WP input is asserted low, hardware writeprotection is enabled.

• If a program operation is still in progress (RDY = 1), writes are discarded.

Table 6. SPI Status register write protectionRDY WEN WPEN WP SP(n) WRSR or PWXSR commands [1]

1 X X X X prohibited

X 0 X X X prohibited

0 1 1 0 X prohibited

0 1 0 X X allowed




RDY WEN WPEN WP SP(n) WRSR or PWXSR commands [1]

0 1 X 1 X allowed

[1] When prohibited, the WRSR and PWXSR commands are treated as invalid commands.

Because the granularity of the write protection mechanisms is sector-based, it isrecommended to store different types of data (e.g. firmware instructions versus datalogging) in separate sectors.

6.1.5 SPI write operation (WRITE)

Since the write enable bit (WEN) is cleared after each write operation, a write enable(WREN) command must precede each WRITE command. The write enable (WREN)command and write disable command (WRDI) are single-byte commands.

A write operation is initiated when the master issues a WRITE command followed by 3bytes. The first byte selects the sector, and the remaining 2 bytes set the 16-bit addresspointer (offset within the sector).

aaa-010728

SI SA address high byte address low byte0

select sector set start address write data bytesWRITE command

WREN command

0 0 0 0 0 0 0 0 00 1 0

SO

first data byte last data byte

SI 0 0 0 0 0 1 1 0

WRDI command

SI 0 0 0 0 0 1 0 0

Figure 6. SPI write operation

Following the address bytes, any number of data bytes between 1 and 256 transmittedby the master, are written to the page write buffer. The write transfer is completed byasserting CS high, upon which an internal self-timed program cycle is started.

The eight lower bits of the address counter, corresponding to the offset within the pagebuffer, auto-increment after each byte is written via SPI. Hence, the current addresswraps at page boundary. If more than 256 data bytes are transferred via SPI, all bytesfrom byte 256 are discarded.

A write operation must be preceded by setting the write enable bit (see Section 6.1.4).

A write operation is initiated when the master issues a WRITE command byte followedby the sector byte and the 16 bit (2 bytes) address. The latter defines the offset within thechosen sector.

The NXP Semiconductors NXH5104 contains eight sectors; hence the SA field contains3 bit. The remaining most significant bits of the sector byte must be logic 0!

If more than 256 data bytes are transferred through the SPI slave interface, theseadditional bytes are discarded.




Table 7. SPI WRITE command: write data bytes to memoryByte Access Command/Data Value Description

0 W WRITE 02h write data bytes to memory.

1:3 W SPI_AR - address register.

4:... R DATA - data bytes.

Table 8. SPI WREN command: enable write operationsByte Access Command/Data Value Description

0 W WREN 06h enable write operations

Table 9. SPI WRDI command: disable write operationsByte Access Command/Data Value Description

0 W WRDI 04h disable write operations

Table 10. SPI address register (SPI_AR)Bits Access [1] Field Value Description

23:19 W - 00000b fixed SPI prefix. These bits should bewritten as zeros

SA_0 000b sector address bits. Sector 0







18:16 W


15:8 W AH - high address bit

7:0 W AL - low address bit

[1] W = volatile writable.

A write operation consists of an erase cycle followed by a programming cycle. To ensurethe endurance, an adaptive trimming algorithm checks if the erase cycle was successful.If not, another erase cycle is started at a higher (internal) supply level. This process leadsto a programming time, which can be considerably longer than the typical programmingtime (see Table 36). It is highly recommended to poll completion through the RDSRcommand. As soon as the write operation is completed, the host can continue and issuenew commands.




6.1.6 SPI status register

The status register (SR) is accessible through the RDSR and WRSR instructions. It canbe read at any time to poll the device RDY status bit. The other bits of the status registerare not updated when the RDY is indicating busy state. They can be overwritten usingthe WRSR instruction. Under applicable write protection conditions (see Section 6.1.4),the WRSR command initiates a write of the status register

The status register can be accessed as part of the extended status register (XSR).

Table 11. SPI status registerBits Access [1] Field Value [2] Description

- R/P SR (00h) status register.

7 R/P WPEN (0b) write protect enable bit.

6:4 R - (000b) (reserved).

SP (00b) sector protection.

SPNONE 00b sector protection disabled.

SPQUART 01b protect sector 6 and 7 (upper quarter).

SPHALF 10b protect sectors 4 to 7 (upper half).

3:2 R/P

SPALL 11b protect all sectors.

1 R [3] WEN (0b) write enable bit.

0 R RDY (0b) ready status bit.

[1] R = readable, P = persistent writable.[2] Default manufacturing values between brackets.[3] The WREN/WRDI commands set/clear the WEN bit.

Table 12. SPI write status registerByte Access Command/Data Value Description

0 W WRSR 01h write status register.

1 P SR - status register.

Table 13. SPI read status registerByte Access Command/Data Value Description

0 W RDSR 05h read status register.

1 R SR - status register.




6.1.7 SPI extended status register

An extended, 32-bit status register (XSR) can be read using the same RDSR command.The upper (first) byte corresponds to the 8-bit status register (SR). Reading beyond thisfirst byte provides access to extended features/settings of the device.

Two functions support writing to the extended status register:

• VWXSR: Volatile write of the XSR. Only the fields indicated with W are writing.• PWXSR: Persistent write of the XSR. Only the fields indicated with P are writing.

Manufacturing default R/W/P fields are indicated (between brackets). A persistent writecan configure the device in a mode which is unrecoverable. It is recommended that thehost programs the preferred settings once at initial start-up.

Table 14. SPI XSR: extended status registerBits Access [1] Field Value [2] Description

- R/W/P XSR (0010h) extended status register

31:24 R/P SR (00h) status register

SPD (00h) sector power-down

bit 23 1b power-down sector 7







23:16 R/W/P


PMI (00b) power mode indicator

PMSB 00b standby.

15:14 W

PMS 01b sleep

(00b) select VDD(IO) mode

0xb VDD(IO) = VDD.

10b VDD(IO) is fixed, > 1.5 V

13:12 R/W/P IOMODE

11b VDD(IO) is fixed, < 1.5 V

11:8 R - (00b) (reserved).

WOI (0b) wear-out indication

WOIOK 0b no wear-out, indication OK

7 R

WOINOK 1b wear-out, indication not OK

PSTAT (00b) result of last program operation

PNONE 00b no program cycle has been started

PSUCCESS 01b program cycle succeeded

PABORT 10b program cycle aborted

6:5 R

PWORN 11b page is worn out




Bits Access [1] Field Value [2] Description

RAWMODE (1b) read address wrapping mode

RAWSEC 0b wrap address at sector boundary

4 R/W/P

RAWFULL 1b read across sector boundary

WPPOL (0b) write protect input polarity

PLOW 0b active low polarity

3 R/W/P

PHIGH 1b active high polarity

2:0 R - (000b) (reserved)

[1] R = readable, W = volatile writable, P = persistent writable.[2] Default manufacturing values between brackets.

Table 15. SPI VWXSR command: volatile write extended status registerByte Access Command/Data Value Description

0 W VWXSR E3h volatile write extended status register.

1:4 W XSR - extended status register.

Table 16. SPI PWXSR command: persistent write extended status registerByte Access Command/Data Value Description

0 W PWXSR E4h persistent write extended status register.

1:4 W XSR - extended status register.

Table 17. SPI read status registerByte Access Command/Data Value Description

0 W RDSR 05h read status register.

1:4 R XSR - extended status register.

6.1.8 SPI device identification

Device identification data comprises a fixed device ID as well as a unique ID. Theidentifiers can be retrieved using the RDID command. This command can only be appliedif sector 0 is powered-up.

aaa-010729

SI

MSB LSB

1

read ID bytesRDID command

0 0 0 0 0 1 1

SO

X X

ID byte 1 ID byte n

Figure 7. Device identification




Table 18. SPI RDID command: read device ID and unique IDByte Access Command/Data Value Description

0 W RDID 83h read device ID and unique ID

1:3 R DEVID (001010h) device ID

4:15 R UID - unique ID.

Table 19. SPI device IDBits Access Field Value Description

- R DEVID (001010h) device ID

23:12 R MFG (001h) manufacturing identification

11:3 R PART (000000010b) part identification

2:0 R REV (000b) revision number

6.1.9 SPI read response (RDR)

Reads a 32-bit register after the extended commands: VAUXR or WOIR.

aaa-010730

SI

MSB LSB

1

read EXTREG bytesRDR command

1 1 1 1 0 0 1

SO

X X

byte 1 byte 4

Figure 8. Read response

Table 20. SPI RDR command: read responseByte Access Command/Data Value Description

0 W RDR F9h read extended register.

1:4 R EXTREG - extended register.

6.1.10 SPI wear-out status register (WOIR)

If the bit WOI in the XSR is set, a part of the EEPROM has reached its maximalendurance level. The host can request more details by consulting the wear-out statusregister (WOSR).

The register gives details informing which sector has reached the maximal endurancelevel.

The command WOIR prepares the wear-out status register.

The host must poll readiness by issuing RDSR commands and observing that the RDYbit is asserted low. To read the wear-out status register value, use RDR.




aaa-010731

SI

MSB

1

read WOSR registerRDR command

1 1 1 1 0 0 1

SO

X X

byte 1 byte 4

LSB

WOIR command

SI 1 1 1 0 1 0 0 0

Figure 9. SPI wear-out status read sequence

Table 21. SPI wear-out status registerBits Access Field Value Description

- R WOSR - wear-out status register.

SPD (00h) wear-out indicator.

bit 31 1b wear-out of sector 7 when set to 1.







31:24 R


23:0 R - undefined (reserved).

Table 22. SPI RDR command: read responseByte Access Command/Data Value Description

0 W WOIR E8h Prepares a read of the wear-out statusregister. To read the wear-out status registervalue, use RDR.

When writing a single byte, the full 32-bit data word containing this byte is cycled (erasedand programmed) and eventually wears out. However, the internal adaptive algorithm forguaranteeing the endurance works on pages. So, when a user wears out a word by onlyrepeatedly writing to only this location, it effectively wears out the full 128 bytes page.




6.1.11 SPI read of the VDD supply (RVDD)

After the device receives the SPI read of the VDD supply command, a response can beeventually read in the response register.

The command RVDD prepares the read of the VDD supply.

The host must poll readiness by issuing RDSR commands and observing whether theRDY bit is asserted low.

To read the value of the VDD supply, use RDR.

Table 23. SPI read of the VDD supplyBits Access Field Value Description

(0h) VDD supply voltage level

0h 0.850 V to 0.950 V

1h 0.925 V to 1.025 V

2h 1.000 V to 1.100 V

3h 1.050 V to 1.150 V

4h 1.150 V to 1.250 V

5h 1.200 V to 1.300 V

6h 1.250 V to 1.350 V

7h 1.350 V to 1.450 V

8h 1.400 V to 1.500 V

9h 1.500 V to 1.600 V

Ah 1.550 V to 1.650 V

Bh 1.650 V to 1.750 V

Ch 1.700 V to 1.800 V

Dh 1.800 V to 1.900 V

Eh 1.850 V to 1.950 V

7:4 R RVDD

Fh 1.900 V to 2.000 V

3:0 - (reserved) (0h) -




6.2 Power modes

To conserve power, the NXH5104 features scalable power modes as illustrated below.

aaa-010732

POWERDOWN

WAKE=1 orCSN: 1->0

(tWAKE, PD)

WRITECSN: 0->1

STBY(tWAKE, SLP)

tcy(prog)

STANDBY(READ/WRITE)

PROGRAM

SLEEP

PWDN

Power-up supplies

SLEEP

PWDN

1. PDWN, SLEEP, STBY, WRITE are host commands.2. WAKE and CS are input pins.3. WAKE signal should be = 1 during at least twake(pd) to transition cleanly from POWER DOWN

state to STANDBY state.4. In SLEEP state, the device is only responding to a limited number of host commands (STBY,

PWDN, and RDSR). The Vaux supply is not available in this mode.5. Transition to PROGRAM state occurs after the host reverts CS to high and the device is

presented with the complete page or word to be written.6. Program cycle time tprog depends on whether a full 256 bytes sector or half sector is being

written.

Figure 10. Power modes

6.2.1 Boot

When VDD is supplied, the device boots in the standby mode by default.

Keeping the CS pin asserted during that phase can stall the booting process. So, as soonas Vbat and VIO are supplied and stable, deassert the CS pin.

When the CS pin is deasserted, and after the wake-up time twake(pd) has elapsed, thedevice is active and ready to process requests. To test if the device is ready, poll theRDY bit.

To move the device to sleep mode or power-down mode, give the sleep command orpower-down command over the SPI interface.




aaa-034350

twake(pd)device is READY

(0 V)

VDD/VDD(IO)

CSn

keeping CSn low stalls booting

Figure 11. External supply ramp-up and CSn handling

6.2.2 Power-down

When the CS pin is asserted low, the device starts ramping-up its (internal) supplies.

Keeping the CS pin asserted while the device is waking up can stall the booting process.So, deassert the pin after minimum 200 ns.

When the CS pin is deasserted, and after the wake-up time twake(pd) has elapsed, thedevice is active and ready to process requests. To test if the device is ready, poll theRDY bit.

Wake up using the CS pin

When the CS pin is asserted low, the device starts to ramp up its (internal) supplies.Keeping the CS pin asserted while the device is waking up can stall the bootingprocess. So, deassert the pin after minimum 200 ns. When the CS pin is deassertedand after the wake-up time twake(pd) has elapsed, the device is active and ready toprocess requests. To test if the device is active and ready, poll the RDY bit. Thisdetection mechanism becomes active 1 ms after applying VDD.

Wake-up using the WAKE pin

If the WAKE pin is de-asserted (low) at start-up, the device remains in power-downmode until the WAKE pin is asserted high.

When the WAKE pin is asserted high, the device ramps-up its supplies. After wake-up time twake(pd), the supplies are stable and the device becomes active and ready toprocess requests. The RDY bit can be used to test that it is ready.

Note: The wake must be asserted low again before reverting to the power-down mode.




aaa-034351

twake(pd)device is READY

(lower supply level)

VDD/VDD(IO)

CSn

keeping CSn low stalls booting

bringing low wakes the device

Figure 12. Wake-up CSn handling

When a PDWN command is issued, the device enters power-down mode.

It takes tpd for the device to finalize the shut-down sequence. Do not to disturb thisprocess and keep CS deasserted.

If a program cycle is still in progress, the PDWN command is ignored. The RDY bit canfirst be polled to check if the command is valid.

Table 24. SPI PDWN: power-down commandByte Access Command Value Description

0 W PWDN E2h power-down command.

6.2.3 Sleep

Sleep mode is a power-saving mode in which the EEPROM array is powered down.However, internally generated supplies are maintained and the serial interfaces remainresponsive to a limited set of host commands. The auxiliary supply voltage (Vaux) cannotbe maintained. For more information, see the application note: VAUX - Auxiliary voltagesupply (Ref. 2). This mode enables faster activation (twake(sleep)) compared to sleep modeand power-down mode. When a SLEEP command is issued, the device enters sleepmode. If a program cycle is still in progress, the SLEEP command is ignored. The RDYbit can first be polled to check if the command is valid.

When in sleep mode, the device only responds to STBY, RDSR, and PDWN commands.The Vaux supply is not available in sleep mode.

Table 25. SPI SLEEP: Sleep commandByte Access Command Value Description

0 W SLEEP E1h sleep command.

6.2.4 Standby

In standby mode, the EEPROM remains powered and ready to process read/writerequests.

When an STBY command is issued in sleep mode, the device ramps-up its internalsupplies. After wake-up time twake(sleep), the supplies are stable and the enabledEEPROM array sectors are switched to power-on state. The enabled EEPROM arraysectors are configured in the XSR register (non-user area).The device becomes activeand ready to process read/write requests. Polling the RDY bit can be used to test it.




Wake-up from sleep mode is faster (twake(sleep)) as it does not involve ramp-up of thesupplies. It does involve switching the enabled EEPROM sectors to the Power-on state.

In standby mode, the EEPROM array can be read and written with READ and WRITEcommands.

Table 26. SPI STBY: standby commandByte Access Command Value Description

0 W STBY E0h standby command.

6.3 Auxiliary supply

The auxiliary supply voltage (Vaux) is a configurable DC-to-DC supply, generated fromthe primary supply voltage (VDD) for supplying an external auxiliary component. It isconfigured using the VAUXVW, VAUXPW, and VAUXR commands that configure theVAUXCFG register.

For performing a volatile write (VAUXVW) of the VAUX configuration register, nopreceding WREN command is required. If there is a persistent write (VAUXPW), apreceding WREN command is required.

Table 27. SPI VAUXVW command: volatile write auxiliary supply configurationByte Access Command/Data Value Description

0 W VAUXVW E5h volatile write auxiliary supplyconfiguration.

1:4 W VAUXCFG - auxiliary supply configuration register.

Table 28. SPI VAUXPW command: persistent write auxiliary supply configurationByte Access Command/Data Value Description

0 W VAUXPW E6h persistent write auxiliary supplyconfiguration register; persistent write ofthe configuration register which is usedfor initialization after reset.

1:4 P VAUXCFG - auxiliary supply configuration register.

Table 29. SPI VAUXR command: read auxiliary supply configurationByte Access Command/Data Value Description

0 W VAUXR E7h prepares a read auxiliary supply register;to read the auxiliary supply configurationregister value, use RDR.




Table 30. SPI auxiliary supply configurationBits Access Field Value Description

31:17 - - - (reserved)

VAUXEN (0b) auxiliary supply enable

VAUXEN_DIS 0b disabled

16 R/W/P

VAUXEN_EN 1b enabled.

VAUXBY (0b) auxiliary supply bypass mode

VAUXBY_DIS 0b disabled

15 R/W/P

VAUXBY_EN 1b enabled

(0b) auxiliary supply ratio setting

0b ratio 2

14 R/W/P VAUXRATIO

1b ratio 3

13 - - - (reserved)

(00b) auxiliary supply drive strength

00b 1/4 of drive strength



12:11 R/W/P VAUXDS


(000b) auxiliary supply clock divider

000b maximum clock speed

001b clock divided by 2






10:8 R/W/P VAUXDF


(0b) auxiliary supply enable voltageregulation

0b disabled (open loop).

7 R/W/P VAUXREG

1b enabled (closed loop).

(0b) auxiliary supply comparator mode

00h minimum (1.5 V)

6:0 R/W/P VAUXV

7Fh maximum (3.3 V)

Note: Details of the Vaux principle and operation can be found in the separate applicationnote: VAUX - Auxiliary voltage supply (Ref. 2).




6.4 Supply mode

There are two VDD supply modes available. The wide range supply pin (WRS) selects thesupply mode.

If the supplied VDD of the device is a regulated voltage always above 1.65 V, it is possibleto use the fixed high supply (FHS) mode. In this mode, the DC-to-DC converter that isused to generate the EEPROM array voltage (VDD(EE)) is bypassed. The rise time of thissupply is hence almost instantaneous, reducing the overall start-up time of the device byapproximately 1.5 ms. See Section 9 for the actual values. To select the fixed high supplymode, the WRS pin must be connected to GND.

If the minimum supplied VDD of the device cannot be guaranteed to be above 1.65 V, thewide range supply mode can be used. To select the wide range supply mode, the WRSpin must be connected to VDD(IO).

6.5 Error-correcting code ECC)

The NXH5104 features an ECC to improve reliability. It provides six parity bits for every32 data bits so that a 38-bit word in memory represents four data bytes internally. Singlebit read errors within a word are corrected.

Since the NXP Semiconductors NXH5104 supports byte level access, it is only allowedto write part of the four data bytes that make up a word. However, if a partial word ismodified, the entire word is updated and endures a program cycle. To benefit from thequalified endurance optimally (500 000 program cycles), write entire words (multiples of4 bytes at word boundaries) within a single transaction.

6.6 Current measurements

The most interesting modes impacting the current consumption of the NXPSemiconductors NXH5104 are the READ and the WRITE mode. Measurementsperformed for these modes are shown in this section. The current has been measuredusing a differential voltage amplifier across the 10 Ω resistor, as shown in the schematic.The scale for all following graphs is 1 mA/division.

aaa-023165

NxH5104

CSn SI SOSCLK

Cload

470 nF470 nF

10 Ω VDD

VDD(IO) VDD(EE)

GND

Figure 13. Current measurement configuration




6.6.1 Read

The following graphs depict a READ operation, with varying levels of supply. Take notethat the capacitive load (Cload) on the SO line dominates IDD(IO).

VDD = VDD(IO) = 1.2 V, FSPI = 5 MHz, pink = CSn, yellow = IDD + IDD(IO), purple = VDD(EE)

Figure 14. Read operation with 1.2 V supply


Figure 15. Read operation with 1.8 V supply




6.6.2 Write

The following graphs depict a WRITE operation, with varying levels of supply.


Figure 16. Write operation with 1.2 V supply

VDD = VDD(IO) = 1.8 V, FSPI = 5 MHz, pink = CSn, yellow = IDD + IDD(IO), purple= VDD(EE)

Figure 17. Write operation with 1.8 V supply




7 Limiting valuesTable 31. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

Tstg storage temperature −50 +150 °C

VDD supply voltage [1] -0.5 +2.4 V

VDD(IO) input/output supplyvoltage

−0.5 +5.2 V

Vaux auxiliary voltage −0.5 +5.2 V

human body model [2] - 2 kVVESD electrostatic dischargevoltage

charged device model [3] - 500 V

Ilu latch-up current [4] - ±100 μA

[1] Maximum voltage for a lifetime of 1 hour at 60 °C, with 0.01 % failure rate and 95 % confidence bound.[2] In accordance with JESD22-A114.[3] In accordance with JESD22-C101.[4] In accordance with JESD78.

7.1 Recommended operating conditions

Table 32. Operating conditionsSymbol Parameter Conditions Min Typ Max Unit

Toper operating temperature −20 +25 +85 °C

VDD supply voltage [1] 1.0 1.2 2.0 V

VDD(IO) input/output supply voltage 1.0 VDD 2.6 V

VDD(IO)(1V2) input/output supply voltage(1.2 V)

1.2 V signaling 1.08 1.2 1.9 V

VDD(IO)(1V8) input/output supply voltage(1.8 V)

1.8 V signaling 1.62 1.8 2.6 V

[1] During the READ and WRITE command execution the VDD is allowed to dip to 0.9 V.




8 Static characteristicsTable 33. Static characteristics-1Symbol Parameter Conditions Min Typ Max Unit

Auxiliary supply

regulation range 1.5 1.8 3.3 VVaux auxiliary voltage

regulation step - 3.75 - mV

standby/active mode - 0.75 2.0 mAIaux(ext) external auxiliary current

pass-through mode - - 2.0 mA

Table 34. Static characteristics-2Current from VDD, excluding external current sourced through supply or I/O pads.

1.2 V 1.8 V UnitSymbol Parameter Conditions

Typ Max Typ Max

IDD(pd) average power-down supplycurrent

- 5 - 5 μA

IDD(sleep) average sleep supply current 80 - 70 - μA

all sectors powered down [1] 400 - 350 - μA

4 sectors active [1] 635 - 475 - μA

IDD(stb) average standby supply current

all sectors active [1] 870 - 600 - μA

IDD(RW) average read supply current 4 sectors active and 5 MHz SPI [1] 800 - 600 - μA

IDD(prog) average write supply current 4 sectors active and 5 MHz SPI [1] 1.1 - 0.7 - mA

[1] Sectors powered down according to the SPD field in the External Status Register (XSR).

Table 35. Static characteristics-3Symbol Parameter Conditions Min Typ Max Unit

Supply voltages and currents

VDD(EEPROM) EEPROM supply voltage 1.5 1.6 2.0 V

Input characteristics[1]

VIH HIGH-level input voltage 0.7 × VS - 2.6 V

VIL LOW-level input voltage −0.5 - +0.3 × VS V

Vhys hysteresis voltage 0.1 × VS - - V

Output characteristics 1.2 V signaling

IOH HIGH-level output current current sourcing capability;VOH = 0.8 × VDD(IO)(1V2)

2.0 - - mA

IOL LOW-level output current current sinking capability;VOL = 0.2 × VDD(IO)(1V2)

2.0 - - mA




Symbol Parameter Conditions Min Typ Max Unit


IOH HIGH-level output current current sourcing capability;VOH = 0.8 × VDD(IO)(1V8)

4.0 - - mA

IOL LOW-level output current current sinking capability;VOL = 0.2 × VDD(IO)(1V8)

4.0 - - mA

[1] For WAKE pin and WRS pin, VS = VDD. For all other I/Os, VS = VDD(IO).

9 Dynamic characteristicsTable 36. Dynamic characteristicsSymbol Parameter Conditions Min Typ Max Unit

Output characteristics – 1.2 V signaling

tr(io) input/output rise time [1] 1.0 - 10 ns

tf(io) input/output fall time [1] 1.0 - 10 ns


tr(io) input/output rise time [1] 1.0 - 10 ns

tf(io) input/output fall time [1] 1.0 - 10 ns

Input characteristics

1.2 V signaling [2] 5 - - MHzfSPI SPI frequency

1.8 V signaling [2] 10 - - MHz

Reliability

Nendu(W) write endurance number of program cycles [3] 500 000 - - cycles

tret(data) data retention time 10 - - years

Input characteristics

full 256 Byte sector [4] - 6.4 - mstprog programming time

half sector - 3.7 - ms

Wide Range Supply mode - 5 - mstwake(pd) power-down mode wake-up time

Fixed High Supply mode - 3.5 - ms

tpd power-down time - - 750 μs

twake(sleep) sleep mode wake-up time - 500 - μs

[1] 5 nH bond wire inductance and 15 pF external capacitive load.[2] VDD > 1.0 V.[3] Endurance qualified at page level.[4] The programming time is consisting out of an erase cycle followed by a program cycle. To guarantee the endurance, an adaptive trimming algorithm could

retry erasing, which leads to a longer programming time. The typical value given is for a programming time without erase retry. Very rarely (on averageonce in 200,000 write operations) such an additional erase/program cycle is performed, which increases the programming time to 11.3 ms. The user isstrongly advised to use the available control flow. This control flow always provides the shortest access time by polling completion of the programmingoperation by using the RDSR command.




aaa-019985

I

I

I

I

I

O

D0

D0

D1

D1

D2

D2

I

O

D0

CPHA = 1

tcy tclk(H) tclk(L)

tsu(MOSI)

tsu(MISO)

tsu(MISO)

th(o)(MISO)

tsu(MOSI)

tCXSH

tSLCX

th(o)(MOSl)

CPHA = 0

D0

D1

D1

D3

D3

SCLK (cpol=0)

SCLK (cpol=1)

CSn

CSn

MOSI

MISO

MOSI

MISO

Figure 18. SPI slave timing

Table 37. SPI slave timing - 1.8 V signaling levelSymbol Parameter Conditions Min Typ Max Unit

Tcy cycle time VDD(IO) = 1.8 V, CLOAD = 4 pF 100 - - ns

tclk(H) clock HIGH time 50 - - ns

tclk(L) clock LOW time 50 - - ns

tsu set-up time To the rising edge of PCLK. MOSI 20 - - ns

th(o) output hold time MOSI 20 - - ns

td(o) output delay time MISO - - 22.5 ns

tSLCX chip select LOW to clock changing 50 - - ns

tCXSH clock changing to chip select HIGH 50 - - ns

Table 38. SPI slave timing - 1.2 V signaling levelSymbol Parameter Conditions Min Typ Max Unit

Tcy cycle time VDD(IO)= 1.2 V, CLOAD = 4 pF 200 - - ns

tclk(H) clock HIGH time 100 - - ns

tclk(L) clock LOW time 100 - - ns

tsu set-up time To the rising edge of PCLK. MOSI 20 - - ns

th(o) output hold time MOSI 20 - - ns

td(o) output delay time MISO - - 64.0 ns




Symbol Parameter Conditions Min Typ Max Unit

tSLCX chip select LOW to clock changing 100 - - ns

tCXSH clock changing to chip select HIGH 100 - - ns

10 Application information

The primary supply input (VDD) accepts a voltage in range 1.0 V to 2.0 V and supportsbattery powered operation with various battery chemistries. Three configurations aredemonstrated to connect the input/output supply (VDD(IO)).

The auxiliary supply (Vaux) is available as an independent, configurable supply forauxiliary components.

In the following application diagrams, a 470 nF decoupling capacitor is proposed fordecoupling VDD and VDD(IO). This value is not strictly mandatory, another value may bechosen depending on the system integration.

10.1 Configuration 1 - Wide range single supply

aaa-010733

VDD

HOST I/F

1.0 V to 2.0 VVDD(IO)

VDD(EE) 470 nF

470 nF

VSS

NXH5104

Figure 19. Single supply

According to application configuration 1 (Figure 19), the input/output signaling voltage(VDD(IO)) can equal the primary supply. It enables single supply operation according tothe specified voltage range.

10.2 Configuration 2 - Wide range dual supply

aaa-013945

VDD

HOST I/F

1.0 V to 2.6 V

VDD(IO)

VDD(EE) 470 nF

470 nF

VSS

NXH5104

1.0 V to 2.0 V

VDD(IO) ≥ VDD

470 nF

Figure 20. Dual supply

For configuration 2 (Figure 20), the input/output supply is different from the primarysupply. The primary supply is typically connected to the battery. The input/output supplycan be disabled while the primary supply stays powered. As long as the device is notpowered down, the input/output supply must be valid.




10.3 Configuration 3 - Fixed high supply mode

If the VDD is > 1.65 V in the WRS mode, configurations 1 (Figure 19) and 2 (Figure 20)can be used. In this case, capacitor C1 is not required.

If VDD is a regulated voltage always above 1.65 V, it is possible to use the WRS mode.In this mode. In this mode, the DC-to-DC converter used to generate the VEE voltage isbypassed. For this reason, the rise of this supply is almost instantaneous, reducing theoverall start-up time of the device by approximately 1.5 ms. See Section 9 for the actualvalues.

aaa-013947

VDD1 MΩ

HOST I/F


VDD(EE)

WRS

VSS

NXH5104

470 nF

Figure 21. General-purpose 1.8 V supply

10.4 Configuration 4 - Auxiliary supply feeding VDD(IO)

aaa-013948

VDD

HOST I/F


VAUX

VDD(EE)

470 nF

VSS

NXH5104

1.5 V to 2.5 V

470 nF

470 nF

VDD(IO) ≥ VDD

Figure 22. Auxiliary I/O supply

In this configuration, the auxiliary output Vaux can be used to feed VDD(IO). The Vauxoutput requires a 470 nF decoupling capacitor.

10.5 Application diagram - driving an LED

Figure 23 shows the application diagram for driving an LED. An additional capacitor maybe required between Vaux and ground, depending on the application.

NxH5104

VAUX

470 nF

aaa-019849

control

Figure 23. Application diagram for driving an LED




11 Packing information

Default packing for the WLCSP devices is tape and reel according to T1 tapingorientation as depicted below.

aaa-010736direction of feed

Figure 24. Tape and reel product orientation

Table 39. Die markingLine Description Example

A Device NxH5104A1

B Lot number - Wafer number P6T659-03

C Fab - year - week E TDyyww

D X-Y coordinates 03 xxx yyyy

11.1 Physical specification

Table 40. Physical specificationItem Specification Remark

Solder bump Material Plating: SnAg1.8 Lead-free




12 Package outline

ReferencesOutlineversion

Europeanprojection Issue date

IEC JEDEC

- - -

JEITA

SOT1461-1

sot1461-1_po

15-09-2916-08-08

Unit

mmmaxnommin

0.140 2.83 2.772.0

A

Dimensions (mm are the original dimensions)

WLCSP13: wafer level chip-scale package; 13 bumps; 2.74 x 2.80 x 0.38 mm SOT1461-1

A1 A2

0.305

0.2550.125 2.80 2.74 0.4

b D E e e1

2.0

e2 v

0.15

w

0.05

y

0.020.110 2.77 2.71

0.2800.115

0.0850.100

0.42

0.340.38

0

scale

3 mm

X

ball A1index area

ball A1index area

BD A

E

A

1 2 3 4 5 6

C

ybAC BØ v

CØ we

e1

AA2

A1

detail X

e

e2

B

C

D

E

F

Figure 25. Package outline SOT1461-1 (WLCSP13)




13 Handling information

See the Flip chip application note (Ref. 1) for detailed instructions on handling, solderingand mounting WLCSP packaged devices.

14 AbbreviationsTable 41. AbbreviationsAcronym Description

EEPROM electrically erasable and programmable read-only memory.

EOC extended operation command

LDO low dropout regulator.

RoHS restriction of hazardous substances (directive 2002/95/EC).

SPI serial peripheral interface.

SR status register

WLCSP wafer-level chip-scale Package.

WOSR wear-out status register

XSR extended status register

15 References

[1] AN11761 application note — Flip chip; 2016, NXP SemiconductorsAvailable on: http://www.nxp.com/documents/application_note/AN11761.pdf

[2] AN11660 application note — VAUX - Auxiliary voltage supply; 2016, NXP Semiconductors

http://www.nxp.com/documents/application_note/AN11761.pdf




16 Revision historyTable 42. Revision historyDocument ID Release date Data sheet status Change notice Supersedes

NXH5104 v.6.3 20190703 Product data sheet - NXH5104 v.6.2

Modifications: • Section 5.2 "Pin description" has been updated.• Section 6.2.1 "Power modes → Boot" has been updated.• Section 6.2.2 "Power modes → Power down" has been updated.• Section 9 "Dynamic characteristics" has been updated.

NXH5104 v.6.2 20170516 Product data sheet - NXH5104 v.6.1

Modifications: • The title of the data sheet has changed from "4 Mbit Serial EEPROM" to "4 Mbit Serial SPIEEPROM".

• Section 6.1.10 has been updated.

NXH5104 v.6.1 20170308 Product data sheet - NXH5104 v.6

Modifications: • Section 3 has been updated.• Section 12 has been updated.• Section 15 has been updated.

NXH5104 v.6 20170111 Product data sheet - NXH5104 v.5

Modifications • Addition to section describing SPI write protection• Data sheet promoted to Product

NXH5104 v.5 201609289 Objective data sheet - NXH5104 v.4

Modifications • Reference [1] changed• POD updated• Security status changed to Company Public



NXH5104 v.2 20141211 Objective data sheet - -




17 Legal information

17.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for productdevelopment.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.[2] The term 'short data sheet' is explained in section "Definitions".[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

17.2 DefinitionsDraft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequencesof use of such information.

Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet isintended for quick reference only and should not be relied upon to containdetailed and full information. For detailed and full information see therelevant full data sheet, which is available on request via the local NXPSemiconductors sales office. In case of any inconsistency or conflict with theshort data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed betweenNXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors productis deemed to offer functions and qualities beyond those described in theProduct data sheet.

17.3 DisclaimersLimited warranty and liability — Information in this document is believedto be accurate and reliable. However, NXP Semiconductors does notgive any representations or warranties, expressed or implied, as to theaccuracy or completeness of such information and shall have no liabilityfor the consequences of use of such information. NXP Semiconductorstakes no responsibility for the content in this document if provided by aninformation source outside of NXP Semiconductors. In no event shall NXPSemiconductors be liable for any indirect, incidental, punitive, special orconsequential damages (including - without limitation - lost profits, lostsavings, business interruption, costs related to the removal or replacementof any products or rework charges) whether or not such damages are basedon tort (including negligence), warranty, breach of contract or any otherlegal theory. Notwithstanding any damages that customer might incur forany reason whatsoever, NXP Semiconductors’ aggregate and cumulativeliability towards customer for the products described herein shall be limitedin accordance with the Terms and conditions of commercial sale of NXPSemiconductors.

Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied priorto the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s ownrisk.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makesno representation or warranty that such applications will be suitablefor the specified use without further testing or modification. Customersare responsible for the design and operation of their applications andproducts using NXP Semiconductors products, and NXP Semiconductorsaccepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXPSemiconductors product is suitable and fit for the customer’s applicationsand products planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriatedesign and operating safeguards to minimize the risks associated withtheir applications and products. NXP Semiconductors does not accept anyliability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, orthe application or use by customer’s third party customer(s). Customer isresponsible for doing all necessary testing for the customer’s applicationsand products using NXP Semiconductors products in order to avoid adefault of the applications and the products or of the application or use bycustomer’s third party customer(s). NXP does not accept any liability in thisrespect.

Limiting values — Stress above one or more limiting values (as defined inthe Absolute Maximum Ratings System of IEC 60134) will cause permanentdamage to the device. Limiting values are stress ratings only and (proper)operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant orrepeated exposure to limiting values will permanently and irreversibly affectthe quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductorsproducts are sold subject to the general terms and conditions of commercialsale, as published at http://www.nxp.com/profile/terms, unless otherwiseagreed in a valid written individual agreement. In case an individualagreement is concluded only the terms and conditions of the respectiveagreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.




No offer to sell or license — Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance orthe grant, conveyance or implication of any license under any copyrights,patents or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described hereinmay be subject to export control regulations. Export might require a priorauthorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expresslystates that this specific NXP Semiconductors product is automotive qualified,the product is not suitable for automotive use. It is neither qualified nortested in accordance with automotive testing or application requirements.NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Inthe event that customer uses the product for design-in and use in automotiveapplications to automotive specifications and standards, customer (a) shalluse the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenevercustomer uses the product for automotive applications beyond NXPSemiconductors’ specifications such use shall be solely at customer’s ownrisk, and (c) customer fully indemnifies NXP Semiconductors for any liability,damages or failed product claims resulting from customer design and useof the product for automotive applications beyond NXP Semiconductors’standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancybetween the translated and English versions.

17.4 TrademarksNotice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.


Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

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Date of release: 3 July 2019Document identifier: NXH5104

Contents1 General description ............................................ 12 Features and benefits .........................................13 Ordering information .......................................... 24 Block diagram ..................................................... 25 Pinning information ............................................ 35.1 Pinning ...............................................................35.2 Pin description ................................................... 36 Functional description ........................................56.1 SPI interface ...................................................... 56.1.1 SPI transaction hold .......................................... 56.1.2 Overview commands ......................................... 66.1.3 SPI read operation (READ) ............................... 76.1.4 SPI write protection ........................................... 86.1.5 SPI write operation (WRITE) ............................. 96.1.6 SPI status register ........................................... 116.1.7 SPI extended status register ........................... 126.1.8 SPI device identification .................................. 136.1.9 SPI read response (RDR) ............................... 146.1.10 SPI wear-out status register (WOIR) ............... 146.1.11 SPI read of the VDD supply (RVDD) ............... 166.2 Power modes ...................................................176.2.1 Boot ..................................................................176.2.2 Power-down ..................................................... 186.2.3 Sleep ................................................................196.2.4 Standby ............................................................196.3 Auxiliary supply ................................................206.4 Supply mode ....................................................226.5 Error-correcting code ECC) ............................. 226.6 Current measurements .................................... 226.6.1 Read ................................................................ 236.6.2 Write .................................................................247 Limiting values ..................................................257.1 Recommended operating conditions ............... 258 Static characteristics ........................................ 269 Dynamic characteristics ...................................2710 Application information ....................................2910.1 Configuration 1 - Wide range single supply ..... 2910.2 Configuration 2 - Wide range dual supply ........2910.3 Configuration 3 - Fixed high supply mode ....... 3010.4 Configuration 4 - Auxiliary supply feeding

VDD(IO) ........................................................... 3010.5 Application diagram - driving an LED .............. 3011 Packing information ..........................................3111.1 Physical specification .......................................3112 Package outline .................................................3213 Handling information ........................................ 3314 Abbreviations .................................................... 3315 References ......................................................... 3316 Revision history ................................................ 3417 Legal information ..............................................35

DD 2 Features and benefits NXH5104 - NXP Semiconductors · – VDD(IO) supply range: VDD to 2.6 V...

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Transcript of DD 2 Features and benefits NXH5104 - NXP Semiconductors · – VDD(IO) supply range: VDD to 2.6 V...