Dct 6000 09 Qpsk Manual

EDU-LABS DIDACTIC

QPSK Modulator Experiment Module

Chapter 17 : DCT17

User Manual

17－2

Digital and Analog Communication Systems

1. To understand the operation theory of the bit splitter.

2. To understand the operation theory of the balanced modulator.

3. To design the balanced modulator by using MC1496.

4. To understand the methods of measuring and adjusting the

balanced modulator circuit.

In the communication systems, besides PSK modulation that we have

mentioned before, there is another type of modulation, which we called

quadrature phase shift keying (QPSK) modulation. Both PSK and QPSK

modulations use the variation of phase of the carrier to modulate the data

signal. However, the main difference between PSK and QPSK modulations

is PSK modulation uses binary system, which means the phase difference of

the carrier signal is 180° that represents “1” or “0” for the data signal. If the

data signal is not binary system, but M-ary level, then we can use QPSK,

17-1: Curriculum Objectives

17-2: Curriculum Theory

Chapter 17 QPSK Modulator

17－3

8PSK and so on to transmit the data signal more effectively. These types of

modulations just use the phase shift within 360° to represent the M-ary

levels. Therefore, N-bits of data signal can be transmitted at the same time.

This will reduce the transmitted bandwidth and a high transmission rate can

be achieved.

QPSK modulated signal is a system with M = 4 levels, which means 2

bits data will be transmitted at the same time. From the equation (15-1) in

chapter 15, we know that the QPSK modulated signal can be expressed as

]4

)1m2(t[cosA)t(x cQPSKπ

−+ω= ; m = 1, 2, 3, 4 (17-1)

From the above equation, we know that the phase of carrier of the

QPSK modulated signal is distributed to 4/π , 4/3π , 4/5π and 4/7π .

Each phase represents 2 bits data signal as shown in table 17-1. The signal

constellation diagram is shown in figure 17-1.

Expanding equation (17-1), we get

)tsin(]4

)1m2([sinA

)t(cos]4

)1m2([cosA)t(x

c

cQPSK

ωπ

−−

ωπ

−=

(17-2)

17－4


Table 17-1 The signal constellation characteristics of quadrature phase shift keying

Phases of QPSK 2 bits inputs

π/4 11

3π/4 10

5π/4 00

7π/4 01

Region 1 Region 2

Region 3 Region 4 Signal Point(10) Signal Point

(11)

Signal Point(00)

Signal Point(01)

)(1 tΦ

)(2 tΦ

Figure 17-1 The signal constellation diagram of QPSK modulation

From equation (17-2), it exits a group of orthogonal functions, which are

t)(cosA)t( c1 ω=Φ (17-3a)

)t(sinA)t( c2 ω=Φ (17-3b)

So, from equation (17-1), QPSK modulated signal can be simplified as

21QPSK ]4

)1m2([sin]4

)1m2([cos)t(x Φ⋅π

−−Φ⋅π

−= (17-4)


17－5

From the above equation, QPSK modulated signal can be assumed as a

combination of two BPSK modulation signal.

Figure 17-2 is the basic block diagram of the QPSK modulator. From

the block diagram, the input data signal has to be converted to parallel

output by the multiplexer.

BalancedModulator

)(1 tΦ

)(2 tΦ

Multiplexer Σ

I-data

Q-data

I-BPSK

Q-BPSK

DataSignalInput

QPSKModulated

SignalOutput

BalancedModulator

Figure 17-2 The basic block diagram of QPSK modulator

The outputs of the multiplexer are the I-data and Q-data, which will match

with the orthogonal functions and the balanced modulators to obtain the

I-data of BPSK modulation signal (I-BPSK) and Q-data of BPSK

modulation signal (Q-BPSK). These two groups of data will be summed to

produce the QPSK modulated signal.

Figure 17-3 shows the circuit block diagram of QPSK modulator. 2 bits

data (2 bits in a group) is sent to the bit splitter at the same time. These two

groups of data will be split to parallel data. One of them will lead to I

17－6


channel to become I-data and the other will lead to Q channel to become

Q-data. The phase of I-data is similar to the carrier of the reference

oscillator, which will be modulated to become I-BPSK. However, the phase

difference between Q-data and the carrier of the reference oscillator is 90°,

which will be modulated to become Q-BPSK. We know that the QPSK

modulator is the combination of two BPSK modulators. Thus, at the output

terminal of the I balanced modulator (I-BPSK), there are two types of

phases will be produced, which are tcos cω+ and tcos cω− . Similarly, at

the output terminal of the Q balanced modulator (Q-BPSK), there are also

two types of phases will be produced, which are tsin cω+ and tsin cω− .

2 bits DataSignal Input

Bit Clock

Q

I

Q Channel

Buffer

BalancedModulator 1

ReferenceCarrier

Oscillator LinearAdder BPF

QPSKOutput

I Channel

Bit Splitter

bf

2/fb

2/fb

2/fb

o90tcos cω

tcos cω

tsin cωV11 +=V10 −=

V11 +=V10 −=

tcos cω±

tsin cω±

1/2

BalancedModulator 2

Phase ShiftLogicLogic

LogicLogic

Figure 17-3 The circuit block diagram of QPSK modulator

When the summer combines these two groups of orthogonal BPSK

modulated signal, there will be four possible phases which are

,tcostsin cc ω+ω+ ,tcostsin cc ω−ω+ tcostsin cc ω+ω− and

tcostsin cc ω−ω− .


17－7

Figure 17-4(a) is the truth table of the phase output of QPSK

modulation and figure 17-4(b) is the constellation diagram of QPSK

modulation. From figure 17-4 (b), QPSK has four possible signal

constellations with same amplitude and the phase difference is o90 .

Therefore, although the QPSK signal has a o45± deviation during

transmission, the receiver still can demodulate the signal correctly.

Figure 17-5 to figure 17-9 are the details circuit diagrams of each block

of QPSK modulator in figure 17-3. Figure 17-5 shows the bit splitter, which

is comprised by four D-flip flops and one JK flip flop. D-flip flop 1 (DFF1)

and D-flip flop 2 (DFF2) comprise a shift register which its transmission

rate is the same as the data rate. JK flip flop 1 (JKFF1) and XOR gate

comprise an inverter. The objective is to invert the CLK signal, then it will

pass through the capacitor to delay the signal so that the D-flip flop 3 (DFF3)

and D-flip flop 4 (DFF4) are able to convert the serial input to parallel

output, which are I-data and Q-data. The duty cycle of I-data and Q-data are

the double the original data signal, bT2 .

Binary Input

Q I

Phase Output of QPSKModulation Signal

0 00 11 01 1

o135−o45−

o135+o45+

Q Q

Q Q

I I

I I

1 1 1

1

0

0 0 0

tt cc ω+ω+ cossintt cc ω−ω+ cossin

tt cc ω+ω− cossintt cc ω−ω− cossin

tcω− cos

tcω+ sin

tcω+ cos

tcω−sin (a) The truth table of phase output (b) The constellation diagram

Figure 17-4 The truth table and the constellation diagram of QPSK modulator

17－8


D Q

CK

CLR

PR

J Q

CK

CLR

PRK

D Q

CK

CLR

PR

D Q

CK

CLR

PR

D Q

CK

CLR

PR

I-Data

Q-Data

+5V

DFF1 DFF2

DFF4JKFF1

DFF3

100 nF

Q Q Q

Q

1C

Q

Data P/I

CLK P/I

Figure 17-5 Bit splitter

Figure 17-6 shows the unipolar to bipolar converter, which is

comprised by 74HCU04, 74HC126, 3904, 3906, DZ1, DZ2, DZ3 and R1 to

R8. The objective of this circuit is to convert the unipolar I-data and

unipolar Q-data to bipolar I-data and bipolar Q-data. After that these

signals will be inputted to pin 1 of MC1496. The operation theory is to

invert the digital signal by inverter (74HCU04) and then pass through two

followers to split the signal into two. These two signals will pass through

the switch, which is comprised by 3904, 3906, DZ1, DZ2, DZ3 and R1 to R8

to convert the unipolar signal to bipolar signal.


17－9

+5V

10k

10k 1k

1k

1k

1.5k

50

50

U1 U2

U3

Q13906

Q23904

UnipolarData Input

BipolarData

Output

V5−

1R2R 3R

4R

5R 7R

6R 8R

1ZD

2ZD

3ZD

7404 74126

74126

Figure 17-6 The circuit diagram of unipolar to bipolar converter

810

4

1

6

12

514

2 3

+12V

+12V

MC1496

Carrier Signal Input

DataSignalInput

PSKOutput

100

10k10k6.8k

10k2.7k

1k 1k100 3.9k

3.9k

10nF

5.6k

200

10k

10k

0.01uF

0.1uF100 100

10k100k 10nF

100k

500k

1R

2R

4R

3R

6R

5R7R

8R

9R 10R

11R

12R

14R

15R

16R

18R

17R

19R

1VR

2VR

1C

2C

10nF3C

4C

5C

13R

V12−

V12−

741Aµ

Figure 17-7 The circuit diagram of balanced modulator

17－10


Figure 17-7 shows the details circuit diagram of balanced modulator.

The balanced modulator is comprised by MC1496. Both the carrier signal

and data signal are single-ended inputs. The carrier signal is inputted at pin

10 and the data signal is inputted at pin 1. The R13 and R14 determine the

gain and the bias current of the circuit, respectively. If we adjust VR1 or the

amplitude of digital signal, we may prevent the modulated signal from

distortion. Then this signal will pass through the filter, which is comprised

by 741Aµ , C3, C5, R17, R18 and R19. The objective is to remove the high

frequency signal in order to obtain the optimum PSK signal.

Figure 17-8 shows the phase shifter, which is used to shift the phase of

carrier signal. This situation will produce a group of orthogonal carrier

signal, which will supply to the balanced modulators of I-channel and

Q-channel. The phase angle (θ ) is related to iR , iC and the frequency of

carrier. The expression is

ii Cf2

)2

(tanR

π

θ

= (17-5)

Figure 17-9 shows the circuit diagram of linear summer. The objective

of the linear summer is to combine the two groups of the orthogonal BPSK

modulation signals to become a QPSK signal.


17－11

100k

100k

10nF

iC

CarrierInput

Terminal

CarrierOutput

Terminal1C

PhaseAdjustment

1nF

20k uA741iR

1R

2R

Figure 17-8 The circuit diagram of phase shifter

I-BPSK

Q-BPSK

1k

1k

1k

1R

2R

4R

3R330

QPSKOutputuA741

Figure 17-9 The circuit diagram of linear summer

17－12


Experiment 1: Bit splitter

1. Refer to figure 17-5 or ETEK DA-2000-09 module.

2. At input terminal of data signal (Data P/I ), input 2.5 V amplitude, 2.5

V offset (i.e. high is 5 V, low is 0 V), 100 Hz frequency and square wave

with 33% duty cycle, i.e. a serial input data streams signal with “100”.

3. At the input terminal of clock signal (CLK P/I ), input 2.5 V amplitude,

2.5 V offset (i.e. high is 5 V, low is 0 V), 300 Hz square wave

frequency.

4. By using oscilloscope, observe on the I-Data output terminal and Q-Data

output terminal of bit splitter, then record the measured results in table

17-1.

5. Change the frequency of data signal to 1 kHz and the frequency of clock

signal to 3 kHz, the others remain the same. By using oscilloscope,

observe on the I-Data output terminal and Q-Data output terminal of bit

splitter, then record the measured results in table 17-1.

6. Change the duty cycle of data signal to 66 %, i.e. a serial input data

streams signal with “110” and the others remain the same. Repeat steps

2 to 5, then record the measured results in table 17-2.

17-3: Experiment Items


17－13

Experiment 2: QPSK modulator

1. Refer to the circuit block diagram of QPSK modulator in figure 17-3,

then by using the detail circuit diagrams of the each circuit block

diagram from figure 17-5 to figure 17-9, construct the QPSK modulator

or ETEK DA-2000-09 module.

2. At the input terminal of data signal (Data P/I ), input 2.5 V amplitude,

2.5 V offset (i.e. high is 5 V and low is 0 V), 100 Hz frequency, square

wave with 33% duty cycle, i.e. a serial input data streams signal with

“100”.

3. At the input terminal of clock signal (CLK P/I ), input 2.5 V amplitude

and 2.5 V offset (i.e. high is 5 V and low is 0 V) and 300 Hz square

wave frequency.

4. By using oscilloscope, observe on the I-Data output terminal and Q-Data

output terminal of bit splitter, and also the output terminal T1 and T2 of

unipolar to bipolar converter. Then records the measured results in table

17-3. Let kHz1fData = , kHz3fCLK = , repeat the above steps and record

the measured results in table 17-3.

5. At the carrier signal input terminal (Carrier P/I ), input a 500 mV

amplitude and 20 kHz sine wave frequency.

6. By using oscilloscope, observe on the output terminals of I-Carrier and

Q-Carrier of phase shifter, then adjust the variable resistor iVR (or

the “Phase Adjust” of ETEK DA-2000-09 module), so that the phase

difference between I-Carrier and Q-Carrier is 90°, then record the

measured results in table 17-4.

17－14


7. By using oscilloscope, observe on the signal output terminal of balanced

modulator 1 (T3), adjust VR1 (or BMR1 of ETEK DA-2000-09 module),

until the waveform without occurring distortion. Then slightly adjust

VR2 (or BMR2 of ETEK DA-2000-09 module) to avoid the asymmetry

of the waveform. Finally record the output signal waveform of the

balanced modulator in table 17-4, which is the I-BPSK modulated

signal.

8. By using oscilloscope, observe on the signal output terminal of balanced

modulator 2 (T4), adjust VR1 (or BMR3 of ETEK DA-2000-09 module),

until the waveform without occurring distortion. Then slightly adjust

VR2 (or BMR4 of ETEK DA-2000-09 module) to avoid the asymmetry

of the waveform. Finally record the output signal waveform of the

balanced modulator in table 17-4, which is the Q-BPSK modulated

signal.

9. By using oscilloscope, observe on the output terminal of linear summer,

which is the combination of I-BPSK and Q-BPSK modulation signals.

Then record the measured results in table 17-4, which is the QPSK

modulated signal.

10. Let kHz1fData = , kHz3fCLK = , repeat step 7 to step 9, then record the



streams signal with “110” and the others remain the same. Repeat steps

1 to 10 and by using oscilloscope, observe on the waveform of each

signal output terminal, then record the measured results in table 17-5 and

table 17-6.


17－15

Table 17-1 Observe on the output signal of bit splitter by changing the frequency of

data signal (The duty cycle of data signal is 33 %).

Data Signal Frequencies 100 Hz 1 kHz

Clock Signal Frequencies 300 Hz 3 kHz

Data Signal

Waveforms

I-Data Output

Terminal of Bit

Splitter

Q-Data Output

Terminal of Bit

Splitter

17-4: Measured Results

17－16


Table 17-2 Observe on the output signal of bit splitter by changing the frequency of data signal (The duty cycle of data signal is 66 %).



Data Signal

Waveforms

I-Data Output

Terminal of Bit

Splitter

Q-Data Output

Terminal of Bit

Splitter


17－17

Table 17-3 Observe on the output signal of QPSK modulator by changing the frequency of data signal ( mV500Vc = , kHz20fc = , Duty cycle of data signal is 33 %).



Data Signal

Waveforms

I-Data Output

Terminal of Bit

Splitter

Q-Data Output

Terminal of Bit

Splitter

17－18


Table 17-3 Observe on the output signal of QPSK modulator by changing the frequency of data signal (Continue) ( mV500Vc = , kHz20fc = , Duty cycle of data signal is 33 %).



I-Data Output

Terminal T1 of

Unipolar to

Bipolar Converter

Q-Data Output

Terminal T1 of

Unipolar to

Bipolar Converter


17－19




I-Carrier Output

Terminal of Phase

Shifter

Q-Carrier Output

Terminal of Phase

Shifter

Output Terminal

T3 of Balanced

Modulator 1

(I-BPSK)

17－20



Output Terminal

T4 of Balanced

Modulator 2

(Q-BPSK)

Output Terminal

of Linear Summer

(QPSK P/O )


17－21




Data Signal

Waveforms

I-Data Output

Terminal of Bit

Splitter

Q-Data Output

Terminal of Bit

Splitter

17－22





I-Data Output

Terminal T1 of

Unipolar to

Bipolar Converter

Q-Data Output

Terminal T1 of

Unipolar to

Bipolar Converter


17－23


Data Signal Frequency 100 Hz 1 kHz

Clock Signal Frequency 300 Hz 3 kHz

I-Carrier Output

Terminal of Phase

Shifter

Q-Carrier Output

Terminal of Phase

Shifter

Output Terminal

T3 of Balanced

Modulator 1

(I-BPSK)

17－24



Output Terminal

T4 of Balanced

Modulator 2

(Q-BPSK)

Output Terminal

of Linear Summer

(QPSK P/O )


17－25

1. What are the basic circuit structures of QPSK modulator and also

explain its operation theory?

2. What is the operation theory of bit splitter?

3. If the data input of bit splitter is 50% duty cycle, what are the output

signals of I-Data output terminal and Q-Data output terminal of bit

splitter?

4. If we need the input phase and output phase to be 90° phase difference,

then what are the values for iR and iC as shown in figure 17-8?

(assume the carrier frequency is 100 kHz)

17-5: Problems Discussion

Table 17-1 Observe on the output of bit splitter by changing the frequency of data signal (The duty cycle of data signal is 33 %) Data Signal Frequencies

100Hz 1kHz

Clock Signal Frequencies

300Hz 3kHz

Data Signal Waveform

I-Data Output Terminal of Bit

Splitter

Q-Data Output Terminal of Bit

Splitter

Table 17-2 Observe on the output signal of bit splitter by changing the frequency of the data signal (The duty cycle of data signal is 66%) Data Signal Frequencies

100Hz 1kHz


300Hz 3kHz



Splitter


Splitter

Table 17-3 Observe on the output signal of QPSK modulator by changing the frequency of data Signal (Vc=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies

100Hz 1kHz


300Hz 3kHz



Splitter


Splitter

Table 17-3 Observe on the output signal of QPSK modulator by changing the frequency of data signal (Vc=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies

100Hz 1kHz


300Hz 3kHz

I-Data Output

Terminal T2 of Unipolar to Bipolar Converter

r

Q-Data Output

Terminal T2 of Unipolar to Bipolar Converter


100Hz 1kHz


300Hz 3kHz

I-Carrier Output Terminal of Phase Shifter

Q-Carrier Output Terminal of Phase Shifter

Output Terminal T3 of Balanced Modulator 1 (I-BPSK)


100Hz 1kHz


300Hz 3kHz

Output Terminal T4 of Balanced Modulator 2 (Q-BPSK)

Output Terminal of Linear Summer (QPSK- O/P)

Table 17-5 Observe on the output signal of QPSK modulator by changing the frequency of data Signal (Vc=500mV, fc=20kHz, Duty cycle of data signal is 66%) Data Signal Frequencies

100Hz 1kHz


300Hz 3kHz



Splitter


Splitter


100Hz 1kHz


300Hz 3kHz

I-Data Output

Terminal T2 of Unipolar to

Bipolar Converter

Q-Data Output

Terminal T2 of Unipolar to

Bipolar Converter


100Hz 1kHz


300Hz 3kHz

I-Carrier Output Terminal of Phase Shifter

Q-Carrier Output Terminal of Phase Shifter

Output Terminal T3 of Balanced Modulator 1 (I-BPSK)


100Hz 1kHz


300Hz 3kHz

Output Terminal T4 of Balanced Modulator 2 (Q-BPSK)

Output Terminal of Linear Summer (QPSK- O/P)

EDU-LABS DIDACTIC

QPSK Demodulator Experiment Module

Chapter 18 : DCT18

User Manual

18－2

Digital Communication Systems

1. To understand the operation theory of QPSK demodulation.

2. To design the signal squarer by using MC1496.

3. To understand the methods of measuring and adjusting the

QPSK demodulation circuit.

Figure 18-1 shows the circuit block diagram of QPSK demodulator.

From the diagram, we know that the operation of QPSK demodulator is

similar to PSK demodulation in chapter 16. Both of them use the structure

of the Squaring loop detector, the main difference is just the QPSK

demodulator needs two groups of signal squarer. If let )t(xQPSK as the PSK

modulated signal, then

]4

)1m2(t[cosA)t(x cQPSKπ

−+ω= ; m = 1, 2, 3, 4 (18-1)

Where the corner frequency ( cω ) is constant. When we let this modulation

signal input into the signal squarer 1, then the output signal of signal squarer

2 can be expressed as

18-1: Curriculum Objectives

18-2: Curriculum Theory

Chapter 18 QPSK Demodulator

18－3

PLLSignal

Squarer1

FrequencyDivider

(1/4)

AnalogSwitch

Data SignalOutput

Terminal

QPSK SignalInput

Terminal

Parallel toSerial

Converter

LPFand

Comparator

I O/P

Q O/P

I-Data

Q-Data

PhaseDetector

SignalSquarer

2

Figure 18-1 The circuit block diagram of QPSK demodulation

)t4(cos8Ak

]2

)1m2(t2[cos2AkAk

83

])1m2(t4[cos8Ak

]2

)1m2(t2[cos2AkAk

83

]4

)1m2(t[cosAk

}])t(x)t(x[k{k)t(x

c

43

c

4343

c

43

c

4343

c443

2QPSKQPSKout

ω−

π−+ω+=

π−+ω+

π−+ω+=

π−+ω=

=

(18-2)

From the equation (18-2), k represents the gain of the signal squarer. The

first term is the DC signal, the second term is the output of 2nd harmonic of

the carrier signal ( c2ω ) and the third term is the output of 4th harmonic of the

carrier signal ( c4ω ). From the third term above, we know that the two groups

of signal squarers can remove all the four phases variation of QPSK and the

output of the signal squarer 2 is the four times frequency of the carrier signal.

18－4


Let the output signal of signal squarer as equation (18-2). Then this

signal will pass through a filter to block the DC signal and the 2nd

harmonic signal. After that by using the PLL, the 4th harmonic sine wave

signal will be converted to square wave and the square wave signal will

pass through a frequency divider to reduce the frequency which equals to

the frequency of carrier signal ( cω ). Then, this signal will pass through the

phase detector, which is used to adjust the phase shift of the QPSK signal.

The objective of phase detector is to control the analog switch for the I

P/O and Q P/O of parallel signal outputs. Then the parallel signals

will pass through the rectifier and comparator, which the parallel I-Data

and Q-Data outputs will be recovered. Finally by using the parallel to

serial converter, the output signals will be recovered to the original data

signal.

Figure 18-2 to figure 18-7 are the details circuit diagram of each block

in figure 18-1. Figure 18-2 is the signal squarer, which is designed by using

MC1496. The input signal passes through R1 and U1, which is the buffer

amplifier. This signal will be inputted to pin 1 and pin 10 of MC1496. The

magnitude of the input signal is controlled by VR1, then adjusting VR1 so

that the output signal of pin 12 will double the frequency of the input signal.

The U3, C4, R15, R16 and R17 comprise a filter. The objective of the filter is to

remove the DC signal and the harmonic signal of the signal squarer. The R11

and R12 determine the gain and the bias current of the circuit, respectively.


18－5

Figure 18-3 shows the details circuit diagram of the PLL. The objective

is to convert the output signal of signal squarer 2 to square wave. The phase

of the square wave signal is similar to the phase of the carrier of QPSK. In

figure 18-3, we know that the PLL circuit is comprised by 74HC4046, R1,

R2, R3, C1, C2 and VR1. Then we can control the frequency of voltage

controlled oscillator by adjusting VR1. The free-running frequency is the

output frequency of the square wave signal in figure 18-3.

Figure 18-4 is the frequency divider, which is implemented by using

74HC393. From the circuit, we know that this frequency divider has two

divisors, which are 2 and 4. Pin 3 is used to divide the clock signal by 2. Pin

10 is used to divide the output signal of PLL signal by 4.

1

2 3

45

68

1012

14

U2MC14963

26

7

4

U1

+12V

R1

10k

R2

2k R5

10k

R4

2.7k

R5

100

R6

10k

R7

100

R11

100

R3

1k

R10

1k R13

3.9k

R14

3.9k

R12

10k

R15

10k

R16

680

R17

1k

R19

1k

R18

1k

C1

10nF

C2

100nF

C3

100nF

C4

10nF

C6

10nF

VR1

100k

3

26

7

4

U3

+12V

C5

100nF

+12V

SignalOutput

TerminalSignalInput

Terminal R8 100R9

100

V12−

V12−

V12−

uA741

uA741

Figure 18-2 The circuit diagram of signal squarer

18－6


VR1

30k

C1

10n

C2

1nF

PCPout1

PC1out2

PCinB3

VCOout45

C1A6

C1B7

GND8VCOin

9SFout10

R1 11R2

12PC2out13PCinA14

Zener 15Vcc 16

74HC4046

R1

3.3K

R2

680

R3

22k

+5V

Sine WaveSignalInput

Square WaveSignalOutput

EN

Figure 18-3 The circuit diagram of PLL

1A1

1CLEAR2

1QA3

1QB4

1QC5

1QD6

GND7

2QD8

2QC9

2QB10

2QA11

2CLEAR12

2A13

Vcc 14U1:74HC393

+5V

Signal InputTerminal

(1/4) SignalOutput

Terminal

Clock SignalInput

Terminal

(1/2) SignalOutput Terminal

Figure 18-4 The circuit diagram frequency divider

Figure 18-5 is the details circuit diagram of phase shifter. This circuit

is used to adjust the phase shift the square wave from frequency divider.

Then the phase shifted square wave is used to detect the phase variation of

the QPSK signal, which will be used to control the analog switch for

parallel I P/O and Q P/O signals. The phase shifter is comprised by

using two 26S02 to adjust the phase of the square wave. Then the two


18－7

output square waves will be outputted through port 2 and port 4 of U2,

which is used to detect the phase variation of the QPSK signal. After that

this signal is used to control the analog switch, 74HC4053 for the two

parallel signal outputs, i.e. I P/O and Q P/O .

Figure 18-6 shows the low-pass filter, which is comprised by RC

circuit and the voltage comparator, which is comprised by using 741Aµ

and diode. The objective of this circuit is to recover the parallel output

signals I P/O and Q P/O to parallel output signals of I-Data and

Q-Data.

Figure 18-7 is the circuit diagram of parallel to serial converter. This

circuit is used to convert and recover the parallel I-Data and Q-Data signals

to serial data signals. From figure 18-7, we know that this converter is

comprised by using 74165. The parallel input signal I-Data and Q-Data are

inputted through pin 5 and pin 6. The output serial data signal can be

obtained at pin 9. The required clock signal of this converter is similar to the

clock signal of QPSK modulator. Therefore, we just need to input the clock

signal of the QPSK modulator to the input terminal (pin 2) of the converter.

At this moment the clock signal will pass through a 1/2 frequency divider

and convert to pulse signal which will be sent to pin 1 of 74165.

18－8


C1 100pF

C2100pF

R1

4.7kR2

100k

Cx1

Rx2

C/D3

I14

/IO56

/Q7

GND8 /Q 9

Q 1011

I1 12C/D 13Rx 14Cx 15Vcc 16

U1:26S02

Signal I/P+5V

+5V

+5V

VR1500k

+5V

+5V

Port1

C3

100pF C4

100pFR3100k

R4

100k

R61k

Cx1

Rx2

C/D3

I14

/IO5

Q6

/Q7

GND8

/Q 9Q 10

/IO 11I1 12

C/D 13Rx 14Cx 15

Vcc 16

U2:26S02

Port1

+5V

+5V

+5V

+5V

Port3

Port3Port4

Port2

R5

1k

+5V

Yo1

Y22

Y3

Y34

Y15

Inhibit6

VEE7

GND8 B 9

A 10X3

11X0

12X 13

X114

X2 15Vcc 16

U3:74HC4053

+5V

Port4Port2

R12

680

R8

680

R7

3.3k

R92.7k

C5

100nF

R11680

R10

680

QPSK I/P

I O/PQ O/P

V12−

Q /IO

Figure 18-5 The circuit diagram of phase shifter


18－9

R1

100kC1

10nF

3

26

7

4

U1

+5V

R3

1kC2

10nR2

1k

D1

1N4004Signal Output

Port

Signal InputPort

V5−

uA741

Figure 18-6 The circuit diagram of low-pass filter and voltage comparator

Shift/Load1

CLK2

E3

F4

G5

H6

QH7

GND8

QH9Serial/IP10A11B12C13D14CLK Inhibit15Vcc16

U2:74165

R1

10k C1

1nF

1/2

I-DataQ-Data

+5V

Serial O/P

74HC04C2

1nF

R2

4.7k

Serial SignalOutput Port

Parallel SignalInput Port

Clock SignalInput Port

U1

Figure 18-7 The circuit diagram of parallel to serial converter

18－10


Experiment 1: Signal squarer and PLL

1. Refer to the circuit block diagram of QPSK demodulator in figure 18-1,

then by using the circuit diagram of signal squarer and PLL in figures

18-2 and 18-3, construct the QPSK demodulator or EDU-LABS DCT-6000-09

module.

2. Adjust VR1 of PLL or PLLR1 of EDU-LABS DCT-6000-09 module until the

free running frequency (fo) of the output terminal (T3) of 74HC4046 is

80 kHz.

3. At the input terminal of QPSK demodulator (QPSK P/I ), input a

carrier signal with 500 mV amplitude and 20 kHz frequency.

4. Adjust VR1 of signal squarer 1 or SSR1 of EDU-LABS DCT-6000-09 module

until the output signal frequency of the output terminal (T1) of signal

squarer 1 is double the carrier frequency, which is 40 kHz. Adjust VR2

of signal squarer 2 or SSR2 of EDU-LABS DCT-6000-09 module until the

output signal frequency of output terminal (T2) of the signal squarer 2 is

four times of the carrier frequency, which is 80 kHz.

5. By using oscilloscope, observe on the output signal waveforms T1 of

signal squarer 1, T2 of signal squarer 2 and T3 of PLL. Then record the


18-3: Experiment Items


18－11

Experiment 2: QPSK demodulator

1. Refer to the circuit block diagram of QPSK demodulator in figure 18-1,

then by using the detail circuit diagrams of the each circuit block

diagram from figure 18-2 to figure 18-7, construct the QPSK

demodulator or EDU-LABS DCT-6000-09 module.

2. Using the QPSK modulator in figure 17-3 of chapter 17 or EDU-LABS

DCT-6000-09 module, to produce the PSK modulation signal as the

signal source for this experiment.

3. At the data signal input terminal of QPSK modulator (Data P/I ), input

a signal with 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V),

100 Hz frequency and square wave with 33 % duty cycle, i.e. a serial

input data streams signal with “100”.

4. At the clock signal input terminal of QPSK modulator (CLK P/I ),

input 2.5 V amplitude, 2.5 V offset (i.e. high is 5 V, low is 0 V ) and 300

Hz square wave frequency.

5. At the carrier signal input terminal of QPSK modulator (Carrier P/I ),

input 500 mV amplitude and 20 kHz square wave frequency.

6. Adjust QPSK modulator to obtain the optimum output waveform of

QPSK modulation signal.

7. Adjust VR1 of PLL of QPSK demodulator or PLLR1 of EDU-LABS

DCT-6000-09 module until the free-running frequency of output terminal

(T3) of 74HC4046 is 80 kHz.

18－12


8. Connect the output signal of QPSK modulator to the input terminal of

QPSK demodulator (QPSK P/I ).

9. Follow the steps in experiment 1 to adjust the signal squarer 1 and

signal squarer 2, so that the output signal T1 is the two times of the

carrier frequency (40 kHz) and the output signal T2 is the four times of

the carrier frequency (80 kHz).

10. Adjust VR1 in figure 18-5 or “Phase Adjust” in EDU-LABS DCT-6000-09

module, until the I-Data and Q-Data can be obtained correctly.

11. By using oscilloscope, observe on the input signal of QPSK, output

signal T1 of signal squarer 1, output signal T2 signal squarer 2, output

signal T3 of PLL 74HC4046, output signal T4 of frequency divider

74HC393, output signal of I-Data, output signal of Q-Data and the

output signal waveform of QPSK demodulator. Then record the


12. Change the frequency of data signal to 1 kHz and the frequency of

clock signal to 3 kHz, the others remain the same. Then record the



streams signal with “110”, and the others remain the same. By using

oscilloscope, observe on the waveforms of each output terminal and

record the measured results in table 18-3.


18－13

Table 18-1 The measured results of the output terminal of signal squarer and PLL

( mV500Vm = , kHz20fc = ).

Test Points Output Signal Waveforms

QPSK

Input Signals

Signal Squarer 1

Output Signal T1

Signal Squarer 2

Output Signal T2

PLL

Output Signal T3

18-4: Measured Results

18－14


Table 18-2 Observe on the output signal of QPSK demodulator by changing the frequency of data signal ( mV500Vm = , kHz20fc = , Duty cycle of data signal is 33 %).

Data signal frequencies 100 Hz 1 kHz

Clock pulse frequencies 300 Hz 3 kHz

QPSK Input Signals

Signal Squarer 1

Output Signal T1

Signal Squarer 2

Output Signal T2

PLL

Output Signal T3


18－15

Table 18-2 Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Continue) ( mV500Vm = , kHz20fc = , Duty cycle of data signal is 33 %).



Frequency Divider

Output Signal T4

I-Data

Output Signal

Waveforms

Q-Data

Output Signal

Waveforms

QPSK

Demodulated

Signal Waveforms

18－16


Table 18-3 Observe on the output signal of QPSK demodulator by changing the frequency of data signal ( mV500Vm = , kHz20fc = , Duty cycle of data signal is 66 %).



QPSK Input Signals

Signal Squarer 1

Output Signal T1

Signal Squarer 2

Output Signal, T2

PLL

Output Signal T3


18－17

Table 18-3 Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Continue) ( mV500Vm = , kHz20fc = , Duty cycle of data signal is 66 %).



Frequency Divider

Output Signal T4

I-Data

Output Signal

Waveforms

Q-Data

Output Signal

Waveform

QPSK

Demodulated

Signal Waveform

18－18


1. What are the basic circuit structures of QPSK demodulator?

2. What are the functions of the phase shifter in QPSK demodulator?

3. Explain the circuit structure of parallel to serial converter and also the

functions of the parallel to serial converter in QPSK demodulator?

18-5 Problems Discussion

Table 18-1 The measured results of the output terminal of signal squarer and PLL (Vm=500mV, fc=20kHz).

Test Points Output Signal Waveform

QPSK Input Signals

Signal Squarer 1 Output Signal T1


Table 18-1 The measured results of the output terminal of signal squarer and PLL (Vm=500mV, fc=20kHz).

Test Points Output Signal Waveform

PLL Output Signal T3

Table 18-2 Observe on the output signal of QPSK demodulator by changing the frequency of data signal (Vm=500mV, fc=20kHz, Duty cycle of data signal is 33%) Data Signal Frequencies

100Hz 1kHz


300Hz 3kHz

QPSK Input Signals




100Hz 1kHz


300Hz 3kHz

PLL Output Signal T3

Frequency Divider Output Signal T4

I- Data Output Signal Waveform


100Hz 1kHz


300Hz 3kHz

Q- Data Output Signal Waveform

QPSK Demodulated Signal Waveform

Dct 6000 09 Qpsk Manual

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Transcript of Dct 6000 09 Qpsk Manual