AFE031C2000

SPI

GPIO

ADC

Button

Slave Button Module(s)

JTAG

DC Power Bus

Network Processor Module

AM335xTouch-screen LCD

UART

DC/DC

DC/DC: LM34910,TPS62170

To System

Host (Debug)

PLC Modem(Master Button

Module)

Ajinder Singh , Dave Hermann

TI DesignsDC Power-Line Communication Reference Design

TI Designs Design FeaturesTI Designs are analog solutions created by TIs analog Robust protection against power-up surges withexperts. Reference Designs offer the theory, part two-stage AC-coupling design with TVS protectionselection, simulation, complete PCB schematic and Power design implements low-pass filtering to filterlayout, bill of materials, and measured performance of PLC communication from switching regulatoruseful circuits. Circuit modifications that help to meet operationalternate design goals are also discussed.

Hardware and software supports multiple nodesDesign Resources DC-input voltage 18-V to 35-V operation

Long cable support, (40-m) cable passed with noTool Folder Containing Design Files24VDCPLCEVM bit errors even at the lowest Transmitter Power

AFE031 Product Folder LevelTMS320F28035 Product Folder Configurable hardware that supports different PLCLM34910 Product Folder standardsTPS62170 Product Folder Complete PHY, MAC, and application layerTPD1E10B06 Product Folder

Featured ApplicationsTMDXEVM3358 Tool Folder Industrial control Lighting applications Smoke and fire detection systems and many more

building automation applications

ASK Our Analog ExpertsWebBench Calculator ToolsTI Designs Precision Library

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and otherimportant disclaimers and information.

All trademarks are the property of their respective owners.

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System Description www.ti.com

1 System DescriptionThe DC (24 V, nominal) Power-Line Communication (PLC) reference design is intended as an evaluationmodule for users to develop end-products for industrial applications leveraging the capability to deliverboth power and communications over the same DC-power line. The reference design provides a completedesign guide for the hardware and firmware design of a master (PLC) node, slave (PLC) node in anextremely small (approximately 1-inch diameter) industrial form factor. The design files includeschematics, BOMs, layer plots, Altium files, Gerber Files, a complete software package with theapplication layer, and an easy-to-use Graphical User Interface (GUI).

The application layer handles the addressing of the slave (PLC) nodes as well as the communication fromthe host processor (PC or Sitara ARM MPU from Texas Instruments, see Figure 1). The hostprocessor communicates only to the master (PLC) node through a USB-UART interface. The master nodethen communicates to the slave nodes through PLC. The easy-to-use GUI (see Figure 7) is also includedin the EVM that runs on the host processor and provides address management as well as slave-nodestatus monitoring and control by the user.

The reference design has been optimized from each slave (PLC)-node source-impedance perspectivesuch that multiple slaves can be connected to the master (see Section 9.1). Protection circuitry has alsobeen added to the analog front-end (AFE) so that it can be reliably AC coupled to the 24-V line (seeSection 9.4). Also note that this reference design layout has been optimized to meet the PLC-powerrequirements. See Section 13.1 for the AFE031 layout requirements for high-current traces.

At the heart of this reference design are the AFE from TI, AFE031 (see Figure 2), to interface with powerlines and the TMS320F28035 Piccolo Microcontroller (see Figure 3) that runs the PLC-Lite protocol fromTI (see Section 5).

1.1 AFE031The AFE031 device is a low-cost, integrated, power-line communication (PLC) AFE device that is capableof capacitive-coupled or transformer-coupled connections to the power line while under the control of aDSP or microcontroller. The AFE031 device is also ideal for driving low-impedance lines that require up to1.5 A into reactive loads. The integrated receiver is able to detect signals down to 20 VRMS and iscapable of a wide range of gain options to adapt to varying input signal conditions. This monolithicintegrated circuit provides high reliability in demanding power-line communications applications. TheAFE031 transmit power-amplifier operates from a single supply in the range of 7 V to 24 V. At a maximumoutput current, a wide output swing provides a 12-VPP (IOUT = 1.5 A) capability with a nominal 15-Vsupply.

The analog and digital signal-processing circuitry operates from a single 3.3-V power supply. The AFE031device is internally protected against overtemperature and short-circuit conditions. The AFE031 devicealso provides an adjustable current limit. An interrupt output is provided that indicates both current limitand thermal limit. There is also a shutdown pin that can be used to quickly put the device into its lowestpower state. Through the four-wire serial-peripheral interface, or SPI, each functional block can beenabled or disabled to optimize power dissipation. The AFE031 device is housed in a thermally-enhanced,surface-mount PowerPAD package (QFN-48). Operation is specified over the extended industrialjunction temperature range of 40C to +125C.

1.2 C2000The F2803x Piccolo family of microcontrollers (C2000) provides the power of the C28x core and control-law accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. Thisfamily is code-compatible with previous C28x-based code, as well as providing a high level of analogintegration. An internal voltage regulator allows for single-rail operation. Enhancements have been madeto the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators withinternal 10-bit references have been added and can be routed directly to control the PWM outputs. TheADC converts from 0 to 3.3-V fixed full scale range and supports ratiometric VREFHI and VREFLOreferences. The ADC interface has been optimized for low overhead and latency.

Based on TIs powerful C2000-microcontroller architecture and the AFE031 device, developers can selectthe correct blend of processing capacity and peripherals to either add power-line communication to anexisting design or implement a complete application with PLC communications.

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LM34910 Step-Down Switching Regulator

AFE031 Powerline

Communications Analog Front End

TMS320F28035Microcontroller

TMDXEVM3358Sitara MPU

TPS62170 Step-Down Switching Regulator

24V (DC Line)

15V3.3V

GND

LM34910 Step-Down Switching Regulator

AFE031 Powerline

Communications Analog Front End

TMS320F28035Piccolo

Microcontroller

TPS62170 Step-Down Converter

15V3.3VHost

Master

Slave

UART Interface

www.ti.com PLC-Over-DC Design Features

2 PLC-Over-DC Design Features DC-input voltage 18-V to 35-V operation Uses DC-power line and GND for both power and communication to multiple nodes

Eliminates need for additional serial-communication wiring Significantly reduces copper-wire installation

Complete PHY, MAC, and application layer handles node addressing and communications Reduces design time and increases system-installation speed

Configurable hardware supports different PLC standards PLC-Lite, G3 and PRIME

3 Block Diagram

Figure 1. PLC Over DC Solution System Block Diagram

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Peripherals

Serial Interfaces2x SPI

TMS320F2803x

1x I2C

Memory

32 / 64 KB Flash

Debug

Real -Time JTAG

10 KB RAM

Boot ROM

1x SCI

Timer Modules

1 x 32-bit eCAP

Power & Clocking

Clocking

Dual Osc 10 MHz

On-Chip Osc

Dynamic PLL Ratio

Changes

Power- on Reset

Brown Out Reset

3x Comparator

Watchdog Timer

Missing Clock Detection Circuitry128- Bit Security Key/Lock

Up to 16 ch, 12 - bit A/D Converter

Connectivity44 I/Os

Converter

3x 32-bit CPU Timers

1 x 32-bit eQEP

1x LIN1x CAN

32- bit Control Law Accelerator

C28x 32- bit CPU

Up to 60 MHz32x32 -bit Multiplier

RMW Atomic ALU

7x 16- bit ePWM

15x PWM Outputs

5x 150- ps HR PWM

AFE031TX

RX

2-Wire TX - RX

Interface

10-bitDAC LPF PA

Zero Cross Detector

Gain Control

TX

RXATTNLPF10-bitDAC

I/O

SPI

Block Diagram www.ti.com

Figure 2. AFE031 Block Diagram