DC-DC Converter for Photovoltaic SystemsFelipe Jung∗, Samuel dos A. Pinheiro∗, Cleyton T. Paz∗, Marcos Fiorin∗, Tiago Dequigiovani∗

∗IFC - Catarinense Federal Institute, Luzerna, SC, Brazil, 89609-000Emails: jung.flp, samuel.pinheiro077 @gmail.com, tcharles mecatronica@yahoo.com.br,

marcos.fiorin, tiago @luzerna.ifc.edu.br

Abstract— This paper presents the implementation of a DC-DC converter for application in photovoltaic power systems. Theproject’s purpose is to adapt a set of photovoltaic cells with15 to 30 Vdc voltage to a 400 Vdc bus. The adopted topologypossesses two conversion stages, DC/AC and AC/DC, with ahigh frequency transformer to isolate them. In this paper it isreported the operating stages, it is also presented the simulationand experimental results with ZVS operation. The experimentalresults were obtained with a prototype with 700 W power ratingand 20 kHz switching frequency. It is ascertained that thewaveforms obtained are according with theoretical analysis.

I. INTRODUCTION

In the past years, the interest in researches about renewableenergy sources has considerably increased due to the increaseof the world’s consume, global warming and pollution. Likephotovoltaic cells and fuel cells, several renewable sourcesprovide electric energy in the form of direct current (DC), sothe applications of power converters end up being adapted tothe need of the load to be connected [1]. When it comes to,specifically, solar energy, recent reports indicate that Brazilhas an annual potential of photovoltaic generation of 24.993TWh, but has installed or in construction only 15.12 MWh [2].Such data, together with the current energy scenario, show thedelay of that area’s development and justify the necessity ofinvestment in researches focused on photovoltaic energy inBrazil.

In this paper, an isolated DC-DC power converter is appliedto the connection of photovoltaic cells to a DC bus, namedDC microgrid. A microgrid is a system that can operate inan autonomus way without being necessary to connect it to adistribution grid. In terms of energy generation, a microgridconsists of small wind generators, fuel cells, modules ofphotovoltaic panels, among others [3].

Fig. 1 shows some applications of this bus in which, throughindividual power converters, one can connect to differentenergy sources, in addition to supply of DC loads, AC loads,and battery loads [4]. It is highlighted, in Fig. 1, the applicationof the power converter studied in this paper.

In this project, it is considered the use of photovoltaicpanels with generation capacity of up to 240 Wp (Watts peak)each, through the supply of up to 30 V in direct current. Thepresented converter is designed to output the voltage of 400V and the rated power of 1 kW. Therefore, it supports theconnection of four photovoltaic panels connected in parallel.

In the following sections, it will be presented the charac-teristics of a particular photovoltaic system, the topology andanalysis of the adopted DC-DC converter, technical definitions

Figure 1. Typical applications of a DC microgrid

of the components, simulation and experimental results, andconclusions.

II. FEATURES OF THE PHOTOVOLTAIC SYSTEM

The design of the presented converter is adapted for theoperation with the photovoltaic panels that have the specifi-cations showed in the Table I. The data are provided by themanufacturer Kyocera.

TABLE ISPECIFICATIONS OF THE PHOTOVOLTAIC PANELS

Solar irradiation 1000 W/m2 800 W/m2

Cell temperature 25oC 45oC

Maximum power 240 W 172 W

Maximum voltage 29.8 V 26.7 V

Maximum current 8.06 A 6.45 A

In order to verify the data of Table I, Fig. 2 illustrates thegenerated voltage graphics, taken from the system made offour photovoltaic panels connected in parallel during a seven-day period.

The graphics show the voltage values with a 2.8 Ohmresistive load, which represents a power of 270 W for avoltage of 27.5 V. One can observe that the voltage reachesa maximum value around 27 V. However, due to variationsof the sunlight incidence, it falls easily to below of 20 V.In addition, one can see that there is much variation in thegenerated energy, mainly in the afternoon period. Against theobtained data, for the rated operation of the converter, it wasconsidered the range of 15 to 30 V.

0

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Vo

ltag

eA(V

)

firstAday secondAday thirdAday fourthAday Average

Figure 2. Photovoltaic panel’s genarated voltage

III. ISOLATED DC-DC CONVERTER

In order to satisfy the project specifications, several topolo-gies of DC-DC converters were studied for the photovoltaicenergy processing. Since various distinct energy sources canbe connected to the DC bus, it is required an isolated converterfor the connection of each source to this bus.

Isolated converters own a galvanic isolation between inputand output, which is obtained through the use of a transformer.There are diverse topologies of isolated converters, including,according to [5], the best known and most used flyback,push-pull, half bridge, and full bridge converters. Flyback,push-pull and half bridge converters are recommended forapplications where the average power is less than 500 W. Thefull bridge converter is recommended for applications in whichthe average power is up to 1500 W [5]. In order to anticipatethe need for expansion of the converter’s capacity for theoperation with four 240 W panels, the adopted topology forthe DC/AC stage of the converter is the full-bridge converter.

That topology is shown in Fig. 3 and consists of a fullbridge inverter, a transformer operating under high frequencyswitching, a rectifier bridge connected in the secondary wind-ing of the transformer, and a LC output filter. The source Vinrepresents the voltage generated by the photovoltaic cells.

S2

S1

S4

S3

Vin+-

DR2

DR1

DR4

DR3

Lf

Cf RL

1 : n

+

Vo

-

X Z

Y

A

B

Figure 3. Full bridge DC-DC converter topology

In this project, it was used a transformer without centraltap due to the fact that the apparent power of the transformeris 11% bigger than the real power of the load while thisdifference increases to 57% in a central tap transformer.Besides, the reverse voltage on the diodes is equal to the peak

voltage on the secondary winding while in the other topology,this voltage is doubled [5].

Thus, there are two stages of conversion in this converter.First, there is a inverter stage (DC/AC conversion), in whichthe continuous voltage is turned into alternated voltage andlinked to the primary winding of a transformer, and secondly,the voltage is raised by the transformer and then, rectified(AC/DC conversion).

A. Command logic

The command logic adopted in this converter consists of thecombination of two technics: phase shifting and PWM (PulseWidth Modulation) [6]. According to [7], all the switchesconduct for half of the switching period and it is inserted adelay in the command of one of the legs of the inverter. WhenS1 and S4 are in on-state, the voltage in the primary windingof the transformer is +Vin, and when S2 and S3 are in on-state, the voltage in the primary winding of the transformer is−Vin. Fig. 4 displays the switching sequence and the variableresponsible for the adjust of the delay time (td). After rectified,the average load voltage is given by the ratio of the time inwhich the voltage applied in the transformer input is Vin andthe time in which it is 0 V. So, the voltage Vo can be describedby (1).

V o =

[1−

(2td

Ts

)]Vinn

(1)

Where Vin is the DC input voltage; td is the delay time;Ts is the switching period; n is the turns ratio of transformer.

B. Operating stages

For the description of the operating stages, it will beconsidered that the filter inductor (Lf ) has a sufficiently highvalue so that the load current can be considered in continuousconduction mode (CCM). It will also be considered that thesemiconductors devices are ideals.

Many works have presented the analysis of this converter[6], [8], [9], [10], [11], with the main purpose of verifying andoptimizing the commutation processes among the switches,some works also include active switches [12], [13].

This topology uses the circuit parasitic elements like leakageinductance of the transformer primary (Llk) and parasiticcapacitors parallel of switches, in order to achieve zero voltageswitching (ZVS) in the switches. The phase shift operationallows a resonant discharge of the output capacitance andthe parallel capacitance of each semiconductor. This processallows the antiparallel diode to conduct just prior to turn-onof the switches, therefore a ZVS condition is achieved [10].

A qualitative analysis of operating stages is described in thesequence for verification of the circuit operation. During oneswitching period one can observe 12 operating stages. Thewaveforms referring to each stage are represented in Fig. 4,and the equivalent circuits are shown in Fig. 5.

First Stage (t0 ≤ t < t1): Considering the steady statecircuit, the switches S1 and S4 are conducting the currentthrough the transformer leakage inductance Llk and primary

magnetizing inductance, so the energy is stored into them. Thepower is transferred from Vin to the load and VAB = +Vin. Inthe secondary, there is a freewheeling stage where the currentin DR2 and DR3 decreases at the same time that the currentin DR1 and DR4 increases, which maintains the voltage in thesecondary null.

Second Stage (t1 ≤ t < t2): When the freewheelingstage in the secondary is over, with the diodes DR1 and DR4

assuming the full value of the secondary current, the appliedvoltage in VAB is transferred to the secondary, according tothe winding ratio (n) of the transformer. During this stage, theswitches S1 and S4 conduct and the transfer of energy fromthe source to the load continues.

Third Stage (t2 ≤ t < t3): At t2, S1 is turned off withZVS due to its parallel capacitance. The resonant stage starts,where the energy stored in Llk charge the capacitor of S1.The voltage across S1 arises and the voltage across S2 fallsto zero. The blank time (tb) has to be larger than this stage toensure ZVS condition for S2.

Fourth Stage (t3 ≤ t < t4): When the voltage across S2

reaches zero, its intrinsic diode starts to conduct with S4, then,

VAB

t [s]

Ip

t [s]

IDR1 IDR3

VS

S4

D2

D2

D3

t2t1 t3t0 t4 t5 t9t6

S3

D1

S1

S4

S4,C1,C2

S2

S3

tb

D2,C3,C4 S3,C1,C2

t [s]

tb

D1,C3,C4

D1

D4

t [s]t7 t8 t10 t11 t12

t [s]

t [s]

S1 S2 S1

S3 S4 S3 S4

Ts/2

td td

Figure 4. Theoretical waveforms

after the blank time finishes, the gate voltage is applied to S2

and ZVS commutation occurs to it.Fifth Stage (t4 ≤ t < t5): At t4, the switch S4 is turned

off under ZVS condition. The energy stored in Llk charges thecapacitor of S4, discharges the capacitor of S3, and establishesa resonant stage between S2 and the parallel capacitors of S3

and S4. The voltage across S4 raises at the same time as thevoltage across S3 falls to zero. In the secondary, there is afreewheeling stage where the current in DR1 and DR4 starts todecrease at the same time that DR2 and DR3 start to conduct.

Sixth Stage (t5 ≤ t < t6): After the voltage across S3

reaches zero, this switch is turned on under ZVS condition.Due to effect of the Llk, the current flows through the intrinsicdiodes of S2 and S3. The voltage in VAB is equal to −Vin. Inthe secondary, the voltage remains null due to the freewheelingstage. The time interval from t3 to t5 is the equivalent timeof td.

Seventh Stage (t6 ≤ t < t7): At t6, the current in theprimary reaches 0 A and inverts its direction. The source Vintransfers the energy to the circuit through S2 and S3. Thefreewheeling stage in the secondary continues and the voltageis null.

Eighth Stage (t7 ≤ t < t8): At t7, the load stage of theinductor Llk is finalized and the switches S2 and S3 conductthe primary current, the applied voltage in VAB is transferredto the secondary. The diodes DR2 and DR3 assume the fullvalue of the secondary current.

Ninth Stage (t8 ≤ t < t9): At time t8, S2 is turned off andthe current flows through S3 and the parallel capacitors of S1

and S2. This resonant LC stage charges the capacitor of S2

and discharges the capacitor of S1.Tenth Stage (t9 ≤ t < t10): At the time t9, the voltage

across S1 reaches zero, and S1 can be turned on after a smallblank-time (tb), and ZVS is ensured because there is enoughenergy in the output filter to maintain the current through S3

and D1.Eleventh Stage (t10 ≤ t < t11): Likewise the fifth stage,

at this one occurs a resonant stage. At t10 the switch S3 isturned off under ZVS condition, and the energy stored in Llk

charges capacitor of the S3 and discharges capacitor of theS4. In the secondary, there is a freewheeling stage where thecurrent in DR2 and DR3 starts to decrease at the same timethat DR1 and DR4 start to conduct.

Twelfth Stage (t11 ≤ t < t12): At time t11 the voltageacross S4 reaches zero and this switch must be turned on whilethe current is still negative (before t12). The instant of gate S4

define the delay time (td). Due to effect of the Llk, the currentflows through the intrinsic diodes of S1 and S4. The voltage inVAB is equal to +Vin. In the secondary, the voltage remainsnull due to the freewheeling stage. The switching period endsat t12 instant that is equal to t0.

IV. CONVERTER SPECIFICATIONS

Table II presents the main specification of the converter.Although the implemented converter’s power is 700 W, thedevices were designed foreseeing the operation of 1 kW.

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo2o [t1 – t2]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo1o [t0 – t1]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo3o [t2 – t3]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

+-

+-

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo4o [t3 – t4]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo5o [t4 – t5]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

+-

+-

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo6o [t5 – t6]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo7o [t6 – t7]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo8o [t7 – t8]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo9o [t8 – t9]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LO

AD

S1

S4S2

+-

+-

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo10o [t9 – t10]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LOA

D

S1

S4S2

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo11o [t10 – t11]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-LO

AD

S1

S4S2

+-

+-

S3

Vin+-

DR2

DR1

DR4

DR3

Stageo12o [t11 – t12]

Llk

Ip+o VAB -

+Vs

-

IDR1 IDR3

IE

Lf

Cf

+

Vo

-

LOA

D

S1

S4S2

Figure 5. Equivalent circuit to each stage

In tables III, IV and V, it is shown the parameters of the

TABLE IISPECIFICATIONS OF THE DC-DC CONVERTER

Input Voltage (Vin) 15 to 30 V

Switching frequency (fs) 20 kHz

Output Voltage (Vo) 400 V

Output Power (Po) 1 kW

Load Resistance (RL) 160 Ω

transformer, of the LC filter, and the semiconductors usedrespectively. The transformer ratio is of about 27 times. Thedesign methodologies are presented in [5] and [7].

TABLE IIIPARAMETERS OF THE TRANSFORMER

Chosen core EE 55/28/21

Primary winding 2x10 18 AWG

Secondary winding 54x1 18 AWG

For the design of the elements of the LC filter, it is definedthat the cut frequency is 4 kHz, 10 times lower than the outputwaveform frequency in the rectifier bridge.

TABLE IVPARAMETERS OF THE LC FILTER

Current ripple (∆I) 20%(2.5A)

Inductance (Lf ) 5 mH

Core EE 55/28/21 142x2 21 AWG

Gap 1.8 mm

Capacitance (Cf ) 100 nF

Voltage ripple (∆V o) 5%(400V)

TABLE VSEMICONDUCTOR DEVICES

Description Specification

DR1,DR2,DR3,DR4 HFA08TB120 (8A, 1200V, trr=28 ns)

S1,S2,S3,S4 IRGP4063 (48A at 100oC)

V. SIMULATION RESULTS

The simulation results, considering all ideal elements, arepresented in order to verify the ZVS operation on the semi-condutor devices. The Table VI shows the parameters ofsimulation results.

TABLE VISIMULATION PARAMETERS

Description Specification

C1, C2, C3, C4 15 nF

Llk 1 µH

tb 0.5 µs

Vin 30 V

Po 300 W

Where C1 up to C4 are the parallel capacitances of S1 upto S4, respectively.

A. Commutation process

Figures 6 and 7 show the behavior of the commutationon the switches of the leading leg (S1, S2) and the lagginglag (S3, S4). Each figure contains the command signals, theswitches voltage, and the switches current in the correspondingleg. Fig. 6 presents the leading leg commutation.

0.0012436

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0.4

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0.8

1

VS1 (CIRCLE) VS2 (TRIANGLE)

0

-5

5

10

15

20

25

30

Vds1 (CIRCLE) Vds2 (TRIANGLE)

0.001243

0

-10

-20

-30

10

20

30

I(S1) (CIRCLE) I(S2) (TRIANGLE)

t2 t3 time [s]

Figure 6. Turn-off S1 and turn-on S2

One can observe in Fig. 6 that when S1 is blocked, thestored energy in Llk charges the capacitor C1 and dischargesthe capacitor C2, providing ZVS in S1.

When the voltage in C2 reaches zero, the intrinsic diode ofS2 starts to conduct the freewheeling current together with S4,providing S2 to be turned on under zero voltage (ZVS).

This commutation is represented in Fig. 4, at the time t2and t3. The duration of this time interval can be calculated by(2), considering the current in the Llk inductor to be constantduring this stage.

∆t3 =(C1 + C2)

|Ip(t2)|Vin (2)

where:∆t3 is the period t3 − t2;|Ip(t2)| is the absolute value of the primary current at t2.

The process of blocking of S2 and conducting of S1 happensin an analog way in the time interval between t8 and t9.This interval duration is determined by (3). For the symmetriccurrent Ip, ∆t9 is equal to ∆t3.

∆t9 =(C1 + C2)

|Ip(t8)|Vin (3)

Fig. 7 presents the lagging leg commutation. The ZVS canbe observed on the turn-on and turn-off of the switches S3

and S4. This interval is represented on Fig. 4 at the time t4to t5, where the charge of C4 and discharge of C3 occur.

0.0013006

0

0.2

0.4

0.6

0.8

1

VS3 (RETANGLE) VS4 (STAR)

0

-5

5

10

15

20

25

30

Vds3 (RETANGLE) Vds4 (STAR)

0.0013

0

-10

-20

10

20

I(S3) (RETANGLE) I(S4) (STAR)

t4 t5time [s]

Figure 7. Turn-off S4 and turn-on S3

That commutation between S3 and S4 occurs in an analogway at the interval t10 to t11. The duration of each time intervalcan be calculated by equations (4) and (5).

∆t5 =(C3 + C4)

|Ip(t4)|Vin (4)

∆t11 =(C3 + C4)

|Ip(t10)|Vin (5)

In comparison to the commutation of the lagging leg, it isverified that the time of charge/discharge of the capacitors islarger due to the fact that its transition happens in the end ofthe freewheeling stage (instant t4 or t10), and not at the instantof current Ip peak, resulting in a smaller current value.

B. ZVS Analysis

There is always ZVS on the leading leg for both turn-onand turn-off commutation. One must only verify the maximumcapacitance to make sure that the end of the charge/discharge

occurs during the blank time (tb), specially in operation withlight-load.

It also occurs ZVS on turn-on and turn-off commutation inthe lagging lag for operation with full-load and so one mustdesign the capacitor value for the same reasons cited for theleading leg. However, in operation with light-load, the ZVSmay not occur due the low value of current Ip or even becauseof a discontinued conduction of this current.

In Fig. 8, one can observe the voltage VAB , the primarycurrent, and the switches S1 and S3 currents. In this figure,one can verify that the commutation of S3 occurs at the end ofthe freewheeling stage. The freewheeling current, also calledcirculating current, is conducted through the switch of thelagging leg and, in case of being discontinuous, at the turn-off of S3 (t10) there won’t be current to charge/discharge thecapacitors [14].

0

-20

-40

20

40

VAB

0

-10

-20

-30

10

20

30

Ip (primary current)

0.00144 0.00146 0.00148 0.0015Time (s)

0

-10

-20

-30

10

20

30

I(S1) I(S3)

t8 t10

Figure 8. VAB voltage and Ip, S1 and S3 currents

VI. EXPERIMENTAL RESULTS

In this section, it will be presented the results obtainedwith the implementation of the converter. The measures weremade with the input voltage of 30 V, a resistive load in theoutput power of the 700 W, and the converter working withoutfeedback.

With the intention of verifying the operation of the circuitunder soft commutation (ZVS) and comparing with simulatingresults, an auxiliary inductor of 1 µH was added in serieswith the primary winding, and 15 nF capacitors were addedin parallel with the switches. The parameter of the design ofthe auxiliary inductor are: Core - NEE-42/21/15; conductorused - copper, AWG 18; conductors in parallel - 11; numberof turns - 3.

A. Control Logic and drive circuit

The switching strategy was implemented in the microcon-troller NXP LPC1343, in which the generation of the controlsignals for each switch utilized the hardware availability,optimizing the size of the firmware and the precision in the

switching time intervals. For the drive circuit, it was used theCI HCPL3150, so that the waveforms showed in Fig. 9 wereobtained.

(a) (b)

(c) (d)

S1 S3

S4

S1

S1 S2 S3 S4

Figure 9. Command signal in the switches

It can be noticed, in Fig. 9(a) and 9(b), that the switches S1

and S2, as well as the switches S3 and S4, are never triggeredat the same time and there is even a blank time to avoid that tohappen. The delay between S1 and S4, and S2 and S3, definedby the time td, can be checked in Fig. 9(c) and 9(d).

B. DC-AC Conversion Stage

Fig. 10 presents the input and the output voltage in thetransformer, where one can check that the relation between theinput and the output rms voltage values is of approximately28 times. The oscillations that occur in the waveforms mightcome from the resonance with leakage inductance and straycapacitances of the transformer.

Figure 10. Primary (CH2) and secondary (CH1) voltage of the transformer

C. AC-DC Conversion Stage

In Fig. 11, one can observe the voltage waveform after therectifying stage (CH2) and the load voltage after the LC filter(CH1). The output voltage is about 400 V.

Figure 11. Output voltage (CH1) and rectified voltage (CH2)

Due the parasitic elements in the converter, it is madenecessary to add a snubber circuit to avoid that overvoltageexceeds the rupture voltage in the diodes on the rectifiercircuit.

The circuit used to provide the clamping of the voltage isshown in Fig. 12, and it is connected to the points X, Y, andZ shown in Fig. 3, where Rc = 82 kΩ -5 W, Cc = 47 nFand Dc = HFA08TB120. The methodology for designing thisRCD clamped snubber can be found in [15].

DC CCX Y

Z

RC

Figure 12. RCD Snubber

D. ZVS Operation

Fig. 13 displays the signal of command and the voltageon the switches S1(13(a)) and S3(13(b)). In these figures, theintervals where the intrinsic diode of each switch conducts arecircled, allowing the turn-on under ZVS in those switches.

DS1

(a)

DS3

(b)

Figure 13. Gate signal and VCE at S1 and S3

Fig. 14 presents the voltage in the secondary and the currentin the primary of transformer. In the waveform of the primarycurrent can be noticed the stages of charging and freewheeling.

Figure 14. Primary voltage (CH1) and primary current (CH2)

Fig. 15 shows the influence, in the effective duty cycle, ofthe parasitic elements of the transformer and of the inductanceadded in series, used to ensure ZVS operation on all switches.

Figure 15. VAB (CH1) and secondary voltage (CH2)

VII. CONCLUSIONS

The DC-DC converter presented in this paper was im-plemented and the results showed are coherent with thetheoretical analysis made. In this topology of the DC-DCconverter, few additional elements are necessary to achieveZVS operation on the switches, and the dissipative snubberused for voltage clamping is connected on the secondary,where the current is low, preventing it to consume a significantparcel of energy. However, the losses caused by Joule effecton the inverter stage, the circulating current, and the limitationof the effective duty cycle are the drawbacks. That can beverified in Fig. 15, where the input voltage has a 5 V dropwhen compared to the rated voltage and the effective dutycycle loss reaches 15%. In order to work with higher powerin the converter, one can increase the transformer’s ratio andapply other constructive techniques in the transformer, aimingto reduce its stray capacitances.

ACKNOWLEDGMENTS

The authors thank the Catarinense Federal Institute (IFC)for the structure and financial support.

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