Davide Zoni - Curriculum Vitae et Studiorum

Name Davide ZoniCitizenship ItalianPhone (+39)- 02 2399 9623Email davide.zoni@polimi.itWebsite http://home.deib.polimi.it/zoniAddress Dipartimento di Elettronica Informazione e Bioingegneria (DEIB)

Politecnico di Milano, 20133, Milan, ITALY

Short Bio

He received the Master in Computer Engineering in 2010 and the Ph.D. in Information Technology in2014, both from Politecnico di Milano where he holds a Post-Doc position at DEIB. During the PhD,he spent 7 months at Polytechnic University of Valencia working with Prof. Jose Flich on innovativesolutions for Networks-on-Chip (NoCs) and 4 months at University of Cyprus working with Prof. YanosSazeides and Prof. Chrys Nicopoulos on efficient power gating techniques for NoCs. He also visited ARM(Cambdridge, UK), as Post-Doc researcher, working with Dr. Stephan Diestelhorst on the next-generationcache coherence protocols for GPU-CPU multi-cores (Aug - Dec 2015).

Short Summary

Research Interests - His research interests include low power design methodologies for embeddedsystems with particular emphasis on the cache coherence and the on-chip interconnet. In 2015, he openeda new research area on RTL design of side-channel aware computer architectures working with Prof.Alessandro Barenghi and Prof. Gerardo Pelosi.EU Projects and International Collaborations - He participated in 3 European Projects (2PARMA(2010-2012), HARPA (2013-2016), MANGO (2015-2018), contributing from the beginning to define thestructure and the objectives of MANGO. He built a heterogeneous network of collaborations beyond theEU projects with universities (UPV and UCY) and companies (IMEC and ARM). He has a biweeklyappointment with Dr. Stephan Diestelhorst (leader of the System Modeling Group at ARM Research)with whom shared a research line on next-generation big.LITTLE architectures.Teaching and Students’ Supervision - He worked as teaching assistant for the “Embedded Systems 1”(M.Sc. Course) since 2012, and for the “Architetture dei Calcolatori e Sistemi Operativi” (B.Sc. Course)since 2017. Moreover, he is tutor for the “Progetto Finale di Reti Logiche” (B.Sc. Course) since 2017. Heco-advised 7 M.Sc. students and he is currently supervising 4 M.Sc. students.Pubblications and Awards - Since 2012, he published 19 conference papers and 6 journal articles. Healso received a best paper award in 2012, two HiPEAC Collaboration Grants in 2013 and 2014 and twoHiPEAC Industrial Grant in 2015 and 2017.

Contents

Position and Education 2

Honors and Awards 4

Teaching and Supervising 5

Research Interests, Collaborations and Professional Activities 7

Publications 11

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Position and Education

Record of Employment

1st September 2015 – now

Post-Doctoral Research Assistant (according to the Italian law n.240/2010 - art.22) at the De-partment of Electronics, Computer Science and Bioengineering (DEIB) of the Politecnico diMilano working on Online Power Monitoring Methodologies and hardware-side countermeasuresto side-channel attacks.

16th April 2014 – 31st August 2015

Post-Doctoral Research Assistant (according to the Italian law n.240/2010 - art.22) at the Depart-ment of Electronics, Computer Science and Bioengineering (DEIB) of the Politecnico di Milanoworking on cache coherence and on-chip interconnect design for low-power embedded multi-cores.

1st January 2011 – 21st March 2014

PhD student at the Department of Electronics, Computer Science and Bioengineering (DEIB)of thePolitecnico di Milano.

Education

• PhD in Information Technology at Politecnico di Milano.Title obtained on 21st March 2014 (European PhD Title with final evaluation: A+).Title: “Exploring power reliability and performance aspects in on-chip networks for multi-cores”Advisor: Prof. William FornaciariReviewers: Prof. C. Brandolese, Prof. F. Catthoor, Prof. J. Flich, Prof. D. Soudris

Minor Research Title: “Server consolidation of multi-tier workloads including performance andreliability constraints” (March 2011 - November 2011).Advisor: Prof. Paolo Cremonesi

• M.Sc. in Computer Science Engineering. December 2010. (110/110 cum laude)Thesis title: “Gestione Dinamica delle Risorse per Sistemi Embedded Multi-Core e WorkloadEterogenei”Advisor: Prof. William Fornaciari

Visiting experiences

• Visiting researcher at ARM, Cambridge, UK (Aug 2015 - Dec 2015).

• Visiting researcher at University of Cyprus, Nicosia, Cyprus (Jan 2015 - Apr 2015).

• Visiting researcher at Polythecnic University of Valencia, Valencia, Spain (Jun 2014 - Jul 2014).

• Visiting researcher at Polythecnic University of Valencia, Valencia, Spain (Jan 2014 1 month).

• Visiting researcher at Polythecnic University of Valencia, Valencia, Spain (Jun 2013 - Sept 2013).

External Courses

• Comprehensive Digital IC Implementation & Sign-Off (Using Cadence tools), STFC RutherfordAppleton Laboratory, UK (Jan 22-26 2018).

• Essential Verification with SystemVerilog and UVM, IMEC, Leuven BELGIUM (Jan 9-13 2017).

• Advanced Synthesis with Encounter RTL Compiler, EUROPRACTICE - Online Course (2017).

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• Encounter RTL Compiler, EUROPRACTICE - Online Course (2017).

• SystemVerilog for Design and Verification, EUROPRACTICE - Online Course (2016).

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Honors and Awards

AW6. HIPEAC INDUSTRIAL INTERNSHIP - (Aug 2017 - Dec 2017)“Analytical Vulnerability Factor Correlation Study”,Supervisor: Dr. Reiley Jeyapaul (ARM Ltd)

AW5. HIPEAC INDUSTRIAL INTERNSHIP - (Aug 2015 - Dec 2015)“Impact of weak memory models on application scalability and hardware design”,Supervisor: Dr. Stephen Diestelhorst (ARM Ltd)

AW4. HIPEAC COLLABORATION GRANT - (Jan 2015 - Apr 2015)“Exploring NoC resynchronization schemes to support DVFS- and NTC-based optimizations”,Supervisor: Prof. Yanos Sazeides (Univeristy of Cyprus)

AW3. HIPEAC COLLABORATION GRANT - (JUN 2013 - Sept 2013)“Dynamic router model and control to optimize power-performance tradeoff in NoCs”,Supervisor: Prof. Jos‘e Flich (Polytechnic Univeristy of Valencia)

AW2. IEEE SoC 2012 Best Paper AwardD. Zoni, S. Corbetta and W. Fornaciari, “Thermal-Performance Trade-off in Network-On-ChipArchitectures”, in IEEE International Symposium on System-on-Chip, Tampere, Finland October11-12, 2012. [C7].

AW1. IEEE SoCC 2012 Travel Grant AwardD. Zoni and W. Fornaciari, “A Sensor-less NBTI mitigation methodology for NoC architectures”,SoCC’2012 25th IEEE International System-on-Chip Conference, Niagara Falls, New York, USA,September 12–14, 2012. [C6]

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Teaching and Supervising

Teaching

2017-2018

• Progetto Finale di Reti Logiche (20 hours, Tutor) - Undergraduate Level - Master of Science inInformation Technology, BSc-IT, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

• Architetture dei Calcolatori e Sistemi Operativi (ACSO) (20 hours, Teaching Assistant) - Under-graduate Level - Master of Science in Information Technology, BSc-IT, Politecnico di Milano, 1stsemester. Lecturer: Prof. L. Breveglieri.

• Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

2016-2017

• Energy Aware Design of Computing Systems and Applications (2 hours) - PhD Course in Informa-tion Technology, Department of Electronics, Information and Bioengineering (DEIB), Politecnicodi Milano.

• Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

2015-2016

• Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

2014-2015

• Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

2013-2014

• Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

2012-2013

• Embedded Systems 1 (20 hours, Teaching Assistant) - Graduate level - Master of Science inInformation Technology, Politecnico di Milano, 1st semester. Lecturer: Prof. W. Fornaciari.

Graduate Students Supervision/Co-Advisor

• Luca Cremona, December 2017, “A Methodology to Augment RTL Designs with Online PowerMonitoring Capability”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Luca Colombo, April 2017, “A novel Coherence Protocol for Selectively Power Gating the L2Banks in Multi-Cores to Optimize the Energy-Performance Trade-Off”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

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• Fabio Pancot, Decemberr 2016, “Exploring the end-to-end compression to optimize the power-performance tradeoff in NoC-based multicores”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Mauro Belluschi, September 2016, “Exploring Future DNUCA Architectures by Bridging theApplication Behavior and the COherence protocol Support”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Andrea Marchese, July 2016, “A DVFS-Capable Heterogeneous Network-on-Chip Architecture forPower Constrained Multi-Cores”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Luca Borghese, September 2015, “Developing a Network Interface Controller to bridge NoC andWishbone-based multi-cores”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Andrea Canidio, July 2015, “A Power Gating Methodology to Aggressively Reduce Leakage Powerin Networks-on-Chip Buffers”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

Graduate Students Supervision/Co-Advisor (Ongoing)

• Andrea Galimberti, Expected Graduation end 2018, “Hardware implementation of a post-quantumcriptographic algorithm”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. Alessandro Barenghi, Prof. Gerardo Pelosi. Co-advisor: Dr. Davide Zoni.

• Giovanni Scotti, Expected Graduation end 2018, “RISC-V embedded CPU implementation forsecurity”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Matteo Brevi, Expected Graduation July 2018, “Side-Channel Information Leakage on FPGADevices: Comparing Clean Room and Target Analysis”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

• Tamer Ahmed Elatras, Expected Graduation April 2018, “A Flow Control Mechanism for FullyAdaptive Routing Algorithms in On-Chip Networks”.Master of Science in Engineering of Computing Systems, Politecnico di Milano, Milano, Italy.Advisor: Prof. William Fornaciari. Co-advisor: Dr. Davide Zoni.

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Research Interests, Scientific Collaborations andProfessional Activities

Research Interests

My research interests are focused on the design methodologies and architectures for embedded multi-cores with emphasis on the security and the low power aspects. In particular, the research activitiesare organized in three different branches: (I) Energy-Performance Optimization of the Multi-cores, (II)Designing Secure Computer Architectures in the IoT and Beyond and (III) Design and Verification ofPower Efficient Embedded Multi-Cores and Gate-Level Tools.

(I) Energy-Performance Optimization of the Uncore in Multi-coresAfter the multi-core revolution, the continuous evolution of market applications and technological deviceshave posed new challenges to hardware manufacturers, in order to meet ever-increasing low-power andperformance requirements. In this scenario, the focus of the design architects shifted from the computa-tional logic to the uncore subsystems, namely the interconnect and the cache hierarchy, to sustain therequired data communication. Moreover, the uncore logic strongly affects the system-wide performanceother than being the primary source of power consumption in the chip. This branch of my research mainlyfocuses on the Networks-on-Chip (NoCs) as the standard on-chip interconnection fabric in multi-coresalso addressing the design of novel cache coherence protocols to support the physically distributed,logically shared cache hierarchy. Both power gating and Dynamic Voltage and Frequency Scaling (DVFS)methodologies for NoCs have been explored to optimize the energy-performance trade-off [J5, J2].Conversely, several optimized cache coherence protocols have been explored to support the DynamicNon Uniform Cache Access (DNUCA) architecture as well as the possibility to power gating selected L2cache banks during CPU intensive periods of the application execution. This research sits on the novellow-power design perspective of acting on cache resources rather than on computational logic to saveenergy [J7].This part of my research strongly relies on ad-hoc cycle-accurate simulation tools that integrates thefunctional and power models on both the multi-core parts side by side with the modeled DVFS andpower-gating actuators, thus imposing a balanced effort between the evaluation of new architecturalsolutions and the need to deeply customize state of the art research simulators to accurately model theadditional considered components, e.g., DVFS and power gating actuators [J3, J1].

(II) Designing Secure Computer Architectures in the IoT and BeyondThe security of modern cryptographic schemes relies on the secret key, rather than leaveraging theknowledge of the encryption algorithm that is supposed to be known to the attacker. A generic encryptionalgorithm takes a secret key and a plaintext as inputs and outputs the chipertext. Conversely, the decryp-tion algorithm takes the secret key and the chipertext as inputs to output the plaintext. Traditionally, thecryptanalysis is used to mathematically prove that an encryption algorithm does not contain weaknessesthat allow to retrieve the plaintext from the chipertext without knowing the secret key.The Internet of Things (IoT) revolution highlights a tightly connected digital world and pushes to thelimit the development of these cryptographic algorithms in low-cost hardware, i.e., smart-cards, micro-controllers as well as smartphones and tablets. In this scenario, the traditional cryptanalysis techniques tosecure the so called main channel of information, i.e. to prove the harness of the encryption algorithmagainst the most powerful computing attacker, is not enough any more. In fact, the IoT makes extremelyeasy for the attacker to gain physical access to these low-cost devices and taking measurements ontheir physical variables, e.g., power consumption. The values of these physical variables are known asside-channel information, since they do not directly allow to retrieve the secret key, while they stronglydepend on how the target device implements the cryptographic scheme as well as on the processed data,i.e., plaintext and secret key. In particular, the Side-Channel Attacks (SCAs) emerges as a family ofcryptographic attacks that exploit the side-channel information extracted from a device that is running the

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target cryptographic scheme to retrieve the secret key.The SCAs open a new security dimension that intimately depends on the implementation of the cryp-tosystem, and for which any cryptanalysis proof is of no help. Although several, mostly software-basedcountermeasures to SCAs have been proposed in the open literature, the hardware design side of thisresearch area is mostly unexplored due to the high degree of cross-disciplinary skills involved, i.e.,hardware design architects, low-level software engineers and cryptographers have to coexists within thesame research team. However, a fresh, security-aware, hardware design methodology is of paramountimportance. Conversely, with no security-related guarantees from the platform level even the protectedsoftware implementations are still vulnerable to SCAs. This branch of my research is supported by thestrong collaboration with Prof. Alessandro Barenghi and Prof. Gerardo Pelosi from the cryptoanalysisresearch group at Politecnico di Milano. The research focuses on the hardware analysis and the designof countermeasures for both embedded CPUs and cryptographic hardware accelerators. In particularthe research outputs valuable contributions to face both Differential Power Analysis (DPA) [CS1] andTemplate-based [CS2] side-channel attacks.

(III) Design and Verification of Power Efficient Embedded Multi-Cores and Gate-Level ToolsThe gate-level simulation of computing devices enables accurate power, area and timing estimates thatcan be also back annotated in the DSE flow to increase the architectural design space exploration accuracy.Moreover, the hardware prototype can be leverage to support cross-disciplinary research, e.g., the designof security-aware computer architectures.My research in this area is focused on the design of low-power, cache coherent embedded multi-coresstarting from open source embedded CPUs, with particular emphasis on the synergic interaction betweenthe interconnect and cache hierarchy. The hardware design and verification of novel NoC architecturesrepresents an important tile of this research [J4], while the critical objective is to deliver an open source,cache-coherent embedded multi-core for education and to enable further research. At this stage, theresearch outcome is a dual-core architecture that implements a simple Valid-Invalid (VI), snooping-basedcoherence protocol. The architecture is scheduled to be exploited in the analysis of the side-channelvulnerabilities from the security viewpoint.Starting from the hardware design a set of companion tools and methodologies for gate-level verificationand analysis have been developed. In particular, a power analysis toolchain for gate-level netlist has beendeveloped for both the ASIC and the FPGA hardware design flows. It allows to accurately estimate thepower consumed by any synthesized architecture with a configurable granularity in the order of tenthsof nanoseconds. The tool has been used to support the SCA vulnerability analysis in [CS1]. Moreover,[C19] introduces a run-time power monitoring methodology that automatically extracts and implements apower model from the RTL description of a generic architecture.

Contribution to European Research Projects

• H2020-FET-671668Name - MANGO: exploring Manycore Architectures for Next-GeneratiOn HPC systemsDuration (Kick-off)- 36 months (Oct 1, 2015)Project Coordinator - Universitat Politecnica de ValenciaLocal Project Leader - Prof. William Fornaciari (william.fornaciari@polimi.it)Role - Task Leader (T2.3), Runtime Resource Management System SupportActivity - Design and implementation of an RTL power monitoring solution for the hardwareaccelerators. The power estimates are collected in the host controller and used to feed the resourcemanagement optimization policy at software level.

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• FP7-ICT-612069Name - HARPA: Harnessing Performance VariabilityDuration (Kick-off)- 39 months (Sept 1, 2013)Project Coordinator - Politecnico di MilanoLocal Project Leader - Prof. William Fornaciari (william.fornaciari@polimi.it)Role - Work Package Leader (WP1), HARPA OSActivity - Analysis, Design and Implementation of (i) low level monitors and actuators for power-performance-reliability optimizations (ii) optimization policies and required infrastructure to makethe estimates and actuation capabilities from hardware level up to the Operating System.

• FP7-ICT-248716Name - 2PARMA: PARallel PAradigms and Run-time MAnagement techniques for Many-coreArchitecturesDuration (Kick-off)- 36 months (Jan, 2010)Project Coordinator - Politecnico di MilanoLocal Project Leader - Prof. Cristina Silvao (cristina.silvano@polimi.it)Role - research team memberActivity - Design and Implementation of the initial resource management policy at Operating Systemlevel, that has been later extended in the Barbequee Open Source Project (http://bosp.dei.polimi.it/).

Scientific Collaborations Beyond EU-Projects

• Cryptography group @POLIMI - Politecnico di Milano, Italy (Jul 2015 - now)Contact(s) - prof. Alessandro Barenghi (alessandro.barenghi@polimi.it), prof. Gerardo Pelosi(gerardo.pelosi@polimi.it)Research Activity - hardware-side countermeasures to side-channel attacks (SCAs).

• ARM Research - ARM Cambridge, UK (Sept 2015 - ongoing)Contact(s) - Dr. Stephan.Diestelhorst (stephan.diestelhorst@arm.com)Research Activity - Coherence protocol and on-chip solutions for big.LITTLE architectures.

• UCY - University of Cyprus, Cyprus (Jan 2015 - ongoing)Contact(s) - prof. Yanos Sazeides (yanos@cs.ucy.cy), Chrys Nicopoulos (nicopoulos@ucy.ac.cy)Research Activity - Power gating methodologies for multi-cores targetting low-power and reliabilityaspects.

• Automation and Control GROUP @POLIMI - Politecnico di Milano, Italy (2015 - now)Contact(s) - prof. Marcello Farina (marcello.farina@polimi.it Research Activity - Distributedcontrol methodologies to efficiently support RTL-level power monitoring for embedded computingarchitectures.

Referee services

• Journal of Microprocessors and Microsystems (MICPRO) (2015-2017)

• Journal of Systems Architecture (JSA) (2014-2017)

• Transactions on Parallel and Distributed Systems (TPDS) (2014-2017)

• Journals on Parallel and Distributed Computing (JPDC) (2017)

• Transactions on Embedded Computing Systems (TECS) (2014-2015)

• Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2014-2015)

• VLSI Journal (2017)

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Technical Program Committee Membership

• PARMA-DITAM 2018: PARMA-DITAM Workshop

• CS2 2018: Security in Computing Systems (CS2)

• DATE 2018: Track D7 - Networks-on-Chip

• CS2 2017: Security in Computing Systems (CS2)

Chair services

• Session Chair DATE 2018: More than Moore Interconnects

• Session Chair ISVLSI 2017: Emerging and Post CMOS Technlogies II

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Complete Publications List

Refereed International Journals IJ (7)Refereed International Conferences and Workshops IC (20)Technical Reports and Theses TR (2)Keynotes KN (2)Currently Submitted Journals CS(3)Pending Book Chapters BC(1)

(Bibliometry: Google Scholar (All - Since 2013): Citations 144 - 142, h-index 7 - 7, i10-index 5 - 5)

Refereed International Journals

J7. D. Zoni, L. Colombo, W. Fornaciari, “DarkCache: Energy-performance Optimization of TiledMulti-cores by Adaptively Power Gating LLC Banks”, ACM Transactions on Architecture andCode Optimization (TACO) , (Accepted for pubblication: Feb-14-2018). (DOI: DOI:pending)

J6. K. Gruttner, R. Gorgen, S. Schreiner, F. Herrera, P. Penil, J. Medina, E. Villar, G. Palermo,W. Fornaciari, C. Brandolese, D. Gadioli, E. Vitali, D. Zoni, S. Bocchio, L. Ceva, P. Azzoni,M. Poncino, S. Vinco, E. Macii, S. Cusenza, J. Favaro, R. Valencia, I. Sander, K. Rosvall, N.Khalilzad, D. Quaglia, “CONTREX: Design of embedded mixed-criticality CONTRol systemsunder consideration of EXtra-functional properties”, Microprocessors and Microsystems , pp. 39-55(2017). (DOI: https://doi.org/10.1016/j.micpro.2017.03.012)

J5. D. Zoni, A. Canidio, W. Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos and Yian-nakis Sazeides, “BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chiprouters”, Journal of Parallel and Distributed Computing , (2017). (DOI: http://dx.doi.org/10.1016/j.jpdc.2017.01.016)

J4. D. Zoni, J. Flich and W. Fornaciari, “CUTBUF: Buffer Management and Router Design for TrafficMixing in VNET-Based NoCs”, IEEE Transactions on Parallel and Distributed Systems , (2016).(DOI: http://dx.doi.org/10.1109/TPDS.2015.2468716)

J3. D. Zoni, F. Terraneo and W. Fornaciari, “A DVFS Cycle Accurate Simulation Framework withAsynchronous NoC Design for Power-Performance Optimizations”, Journal of Signal ProcessingSystems , (2016). (DOI: http://dx.doi.org/10.1007/s11265-015-0989-1)

J2. D. Zoni, F. Terraneo and W. Fornaciari, “A control-based methodology for power-performanceoptimization in NoCs exploiting DVFS”, Journal of Systems Architecture , (2015). (DOI: http://dx.doi.org/10.1016/j.sysarc.2015.04.004)

J1. D. Zoni and W. Fornaciari, “Modeling DVFS and Power-Gating Actuators for Cycle-AccurateNoC-Based Simulators”, ACM Journal on Emerging Technologies in Computing Systems , (2015).(DOI: https://doi.org/10.1145/2751561)

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Refereed International Conferences and Workshops

C20. G. Massari, F. Terraneo, M. Zanella, D. Zoni, “Towards Fine-grained DVFS in Embedded Multi-core CPUs”, ARCS 2018 - 31st International Conference on Architecture of Computing Systems ,Technical University of Braunschweig, Braunschweig, Germany (Apr 9-12, 2018 - (Accepted forpublication). (DOI: pending)

C19. D. Zoni, L. Cremona, W. Fornaciari, “PowerProbe: Run-time Power Modeling Through AutomaticRTL Instrumentation ”, Design, Automation and Test in Europe (DATE) , Dresden, GERMANY,19-23/3/2018, pp. (2018) - (Accepted for publication). (DOI: pending)

C18. L. Cremona, W. Fornaciari, A. Marchese, M. Zanella and D. Zoni, “DENA: A DVFS-capablehEterogeneous NoC Architecture”, 2017 IEEE Computer Society Annual Symposium on VLSI(ISVLSI) , Bochum, GERMANY, 2017, pp. 489-494 (2017) - (Alphabetic order). (DOI: http://dx.doi.org/10.1109/ISVLSI.2017.91)

C17. J. Flich, G. Agosta, P. Ampletzer, D. Atienza, C. Brandolese, A. Cilardo, W. Fornaciari, Y.Hoornenborg, M. Kovac, B. Maitre, G. Massari, H. Mlinaric, E. Papastefanakis, F. Roudet,R. Tornero, D. Zoni, “Enabling HPC for QoS-sensitive applications: The MANGO approach”,Design, Automation & Test in Europe (DATE) , Dresden, 2016, pp. 702-707 (2016). (DOI:http://ieeexplore.ieee.org/abstract/document/7459399/)

C16. J. Flich, G Agosta, P. Ampletzer, D. Atienza, A. Cilardo, W. Fornaciari, M. Kovac, F. Roudet,D. Zoni, “The MANGO FET-HPC Project: An Overview”, IEEE 18th International Conferenceon Computational Science and Engineering , Porto, 2015, pp. 351-354 (2015). (DOI: http://dx.doi.org/10.1109/CSE.2015.57)

C15. D. Zoni, L. Borghese, G. Massari, S. Libutti and W. Fornaciari, “TEST: Assessing NoC PoliciesFacing Aging and Leakage Power”, Euromicro Conference on Digital System Design , Funchal,2015, pp. 606-613 (2015). (DOI: http://dx.doi.org/10.1109/DSD.2015.16)

C14. F. Terraneo, D. Zoni and W. Fornaciari, “An accurate simulation framework for thermal explorationsand optimizations”, Workshop on Rapid Simulation and Performance Evaluation: Methods andTools (RAPIDO ’15) , ACM, New York, NY, USA, , Article 5 , 6 pages (2015). (DOI: http://dx.doi.org/10.1145/2693433.2693438)

C13. M. Farina, D. Zoni, W. Fornaciari, “A control-inspired iterative algorithm for memory managementin NUMA multicores”, IFAC Proceedings Volumes , Volume 47, Issue 3, 2014, Pages 6117–6122(2014). (DOI: http://dx.doi.org/10.3182/20140824-6-ZA-1003.02402)

C12. F. Terraneo, D. Zoni and W. Fornaciari, “A cycle accurate simulation framework for asynchronousNoC design”, International Symposium on System on Chip (SoC) , Tampere, Finland, 2013, pp. 1-8(2013). (DOI: http://dx.doi.org/10.1109/ISSoC.2013.6675263)

C11. D. Zoni, J. Flich and W. Fornaciari, “Adaptive routing and Dynamic Frequency Scaling for NoCpower-performance optimizations”, 23rd International Workshop on Power and Timing Modeling,Optimization and Simulation (PATMOS) , Karlsruhe, 2013, pp. 231-234 (2013). (DOI: http://dx.doi.org//10.1109/PATMOS.2013.6662179)

C10. D. Zoni, F. Terraneo and W. Fornaciari, “An analytical, dynamic, power-performance router modelfor run-time NoC optimizations”, IEEE International System-on-Chip Conference(SOCC) , Er-langen, 2013, pp. 290-295 (2013). (DOI: http://dx.doi.org/10.1109/SOCC.2013.6749703)

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C9. D. Zoni and W. Fornaciari, “Sensor-wise methodology to face NBTI stress of NoC buffers”,Design, Automation & Test in Europe Conference & Exhibition (DATE) , Grenoble, France, 2013,pp. 1038-1043 (2013). (DOI: http://dx.doi.org/10.7873/DATE.2013.216)

C8. D. Zoni and W. Fornaciari, “NBTI-aware design of NoC buffers”, Interconnection Network Archi-tecture: On-Chip, Multi-Chip (INA-OCMC ’13) , ACM, New York, NY, USA, 25-28 (2013). (DOI:http://dx.doi.org/10.1145/2482759.2482766)

C7. D. Zoni, S. Corbetta and W. Fornaciari, “Thermal/performance trade-off in network-on-chip archi-tectures”, International Symposium on System on Chip (SoC) , Tampere, FINLAND, 2012, pp. 1-8(2012). (DOI: http://dx.doi.org/10.1109/ISSoC.2012.6376363)

C6. D. Zoni and W. Fornaciari, “A sensor-less NBTI mitigation methodology for NoC architectures”,IEEE International System-on-Chip Conference (SOCC) , Niagara Falls, NY, 2012, pp. 340-345(2012). (DOI: http://dx.doi.org/10.1109/SOCC.2012.6398329)

C5. S. Corbetta, D. Zoni and W. Fornaciari, “A Temperature and Reliability Oriented SimulationFramework for Multi-core Architectures”, IEEE Computer Society Annual Symposium on VLSI, Amherst, MA, 2012, pp. 51-56 (2012). (DOI: http://dx.doi.org/10.1109/ISVLSI.2012.22)

C4. D. Zoni, S. Corbetta and W. Fornaciari, “HANDS: heterogeneous architectures and networks-on-chip design and simulation”, ACM/IEEE international symposium on Low power electronics anddesign (ISLPED ’12) , ACM, New York, NY, USA, 261-266 (2012). (DOI: http://dx.doi.org/10.1145/2333660.2333721)

C3. A. Sansottera, D. Zoni, P. Cremonesi and W. Fornaciari, “Consolidation of multi-tier workloadswith performance and reliability constraints”, International Conference on High PerformanceComputing & Simulation (HPCS) , Madrid, 2012, pp. 74-83 (2012). (DOI: http://dx.doi.org/10.1109/HPCSim.2012.6266893)

C2. C. Brandolese,W. Fornaciari, L. Rucco and D. Zoni, “Towards Energy-Efficient Functional Con-figuration in WSNs”, 11th IFAC,IEEE International Conference on Programmable Devices andEmbedded Systems , Volume 45, Issue 7, 2012, Pages 37-42 (2012). (DOI: http://dx.doi.org/10.3182/20120523-3-CZ-3015.00010)

C1. D. Zoni, P. Bellasi and W. Fornaciari, “A low-overhead heuristic for mixed workload resource parti-tioning in cluster-based architectures”, 25th international conference on Architecture of ComputingSystems (ARCS’12) , Heidelberg, Berlin, 86-97 2012 (2012). (DOI: http://dx.doi.org/10.1007/978-3-642-28293-5_8)

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Technical Reports and Theses

TR2. D. Zoni, , Exploring power reliability and performance aspects in on-chip networks for multi-coresPhD Thesis, Politecnico di Milano, (2014). (URL: https://www.politesi.polimi.it/handle/10589/89869)

TR1. D. Zoni, , Gestione dinamica delle risorse per sistemi embedded multi-core e workload eterogeneiM.Sc. Thesis, Politecnico di Milano, (2010). (URL: https://www.politesi.polimi.it/handle/10589/11804)

Keynotes

KN2. D. Zoni, “Towards GPU-aware System Wide Cache Hierarchy for Graphic Workloads”, KEYNOTE- ARM, Cambridge, UK , (December 2, 2015).

KN1. D. Zoni, “Dynamic Voltage Frequency Scaling in Networks-on-Chip: use it without abuse it”,KEYNOTE - University of Cyprus, Nicosia, Cyprus , (April 26, 2015).

Currently Submitted Journals

CS2. A. Barenghi, W. Fornaciari, G. Pelosi, D. Zoni, “Scramble Suit: A Profile Differentiation Counter-measure to Prevent template Attacks”, IEEE Transactions on Dependable and Secure Computing ,(submitted on 7/2017) - (Alphabetic order).

CS1. D. Zoni, A. Barenghi, W. Fornaciari, G. Pelosi, “A Comprehensive Side Channel InformationLeakage Analysis of an In-order RISC CPU Microarchitecture”, ACM Transactions on DesignAutomation of Electronic Systems , (submitted on 6/2017, Major due: Feb 25, 2018 ).

Pending Book Chapters

B1. William Fornaciari and Dimitrios Soudris, “Harnessing Performance Variability in Embedded andHigh-performance Many/Multi-core Platforms - A Cross-layer Approach”, Springer, NY, USA ,(expected issue date July 2018).

Milan, March 8, 2018 Signature

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