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UPF Introduction
Dennis Brophy
Vice-Chairman, Accellera
IEEE P1801
The Unified Power Format for Low Power Designs
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UPF Update - DATE 2008 - Munich, Germany2
Agenda – 13:00-13:05
Introduction
• Dennis Brophy, Vice-Chairman – Accellera
– 13:05-13:30 Architecting a low power design with UPF
• Larry Vivolo, Director Low Power Solutions – Synopsys
– 13:30-14:00
Synthesizing and implementing the low power design• Arvind Narayanan, Product Director – Magma Design
Automation
– 14:00-14:20Functional verification of a low power design
• Stephen Bailey, Chair – IEEE P1801 WG
– 14:20-14:30UPF Experience & Conclusion
• Yatin Trivedi, Magma Design Automation
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UPF Update - DATE 2008 - Munich, Germany3
What is Accellera’s Mission – Drive the worldwide development and use of
standards required by systems,
semiconductor and design tool companies
that enhance a language-based design
automation process.
– The Unified Power Format is closely
associated with the design and verification
languages sponsored by Accellera.
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Accellera MembersMembers:• Aldec
• ARM Ltd.
• Azuro• Cadence Design Systems
• Certess
• Cisco
• Denali Software Inc.
• Freescale Semiconductor • IBM
• Infineon Technologies
• Intel Corporation
• Jasper Design Automation
• Magma Design Automation• Mentor Graphics
• Nokia
• Novas
• OneSpin Solutions• Qualcomm Inc.
• Rockwell Coll ins
• Silvaco
• SpringSoft, Inc.• ST Microelectronics
• Sun Microsystems
• Synopsys
• Texas Instruments
• Xilinx
… and over 4,000 Designers Forum members
BOLD: Accellera Board Member
Officers:Chairman
Shrenik Mehta
Sun Microsystems
Vice-Chairman
Dennis Brophy
Mentor Graphics
SecretaryKaren Bartelson
Synopsys
Treasurer
Stan KrolikoskiCadence
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UPF Update - DATE 2008 - Munich, Germany5
Industry Need
• Power has become the dominate factor in the design oftoday’s electronic systems – Explosion in battery operated systems
– Many (most) non-portable designs are also constrained bypower consumption requirements
• Heat generation and dissipation
• Practical power supply & management
• Current state is a hodge-podge of commercial and adhoc solutions – SAIF, GAF, etc.
– Specification of power aware design characteristics• Often done late at gate-level and ad hoc
– Need to verify correctness of power-aware functionality
– Done sooner and with higher correlation to design intent
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UPF Update - DATE 2008 - Munich, Germany6
Action Initiated
• DAC 2006: – TI and Nokia organized a meeting on the topic of an
open standard for low power design flows – The 4 top EDA vendors attended
• Plus Atrenta
– Broad, significant user representation including• Texas Instruments
• Nokia
• ARM
• ST Microelctronics
• Philips (NXP)
• Sun Microsystems
– Shrenik Mehta represented Accellera
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UPF Update - DATE 2008 - Munich, Germany7
UPF Timeline Proposed
Si2 / Accellera Workshop on LowPower
5 Oct 06
Submission to Accellera Board for Approval
30 Nov 06
Hand-off to IEEE and/or other suitable
standards organizations
31 Jan 07
Accellera TSC formation11 Sep 06
First drafts available for review30 Oct 06
Design Objectives Document; Weekly
meetings start
18 Sep 06
Initial TSC Meeting
MilestoneWeek Of
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Actual UPF Timeline
All donations accepted23 Oct 06
First draft available for review27 Dec 06
Accellera TSC formation28 Aug 06
Accellera/Si2 Sponsored Workshop05 Oct 06
Design Objectives Document25 Sep 06
Frequent telecon and face-to-face
meetings commence
18 Sep 06
MilestoneWeek Of
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Actual UPF Timeline (2)
Accellera Board approval22 Feb 07
Transfer to IEEE working groupMay 07
Final draft available for review19 Jan 07
Submission to Accellera Board for
Approval
24 Jan 07
Accellera TSC approval23 Jan 07
Final draft completion23 Jan 07
MilestoneWeek Of
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Accellera Moves UPF to IEEE
• Accellera policy is to transfer its standards
to IEEE – UPF is in the IEEE stage of standardization
– IEEE P1801 was formed in 2007
• Accellera supports IEEE/IEC dual logoprocess
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UPF Update - DATE 2008 - Munich, Germany11
Agenda
– 13:00-13:05Introduction
• Dennis Brophy, Vice-Chairman – Accellera
– 13:05-13:30 Architecting a low power design with UPF
• Larry Vivolo, Director Low Power Solutions – Synopsys
– 13:30-14:00
Synthesizing and implementing the low power design• Arvind Narayanan, Product Director – Magma Design
Automation
– 14:00-14:20Functional verification of a low power design
• Stephen Bailey, Chair – IEEE P1801 WG – 14:20-14:30
UPF Experience & Conclusion
• Yatin Trivedi, Magma Design Automation
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Architecting a low power design with UPF
Larry Vivolo
Synopsys
IEEE P1801
The Unified Power Format for Low Power Designs
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Agenda
• The Power Challenge
• Techniques for Power Management• Building a UPF Low-Power Flow
• Benefits of the UPF Flow
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Everyone Knows… Low Power is a
Problem for Portable Devices
It’s all aboutbattery life
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Low Power Challenge
Not Limited to Hand-held Devices
Facilities
Cost
System
Packaging & Cooling
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 20 40 60 80
Reliability
Temperature
R e l i a b i l i t y
Networking
Graphics
Computing
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UPF Update - DATE 2008 - Munich, Germany16
Design Techniques for Low Power
Source: J. Rabaey, UCB 2005
Constant
Throughput/Latency
Variable
Throughput/Latency
Design Time Non-Active Modules Run Time
Dynamic &
Short
Circuit
Logic
Re-Structuring,
Logic Sizing
Reduced VDDMulti-VDD
Clock Gating
Dynamic or
Adaptive
Frequency &Voltage Scaling
LeakageStack Effect
+ Multi-VTH
Sleep Transistors
Multi-VDD
Variable VTH
Variable VTH
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UPF Update - DATE 2008 - Munich, Germany17
How to Automate these Techniques ?
• Overlay power intent on top of the design
P S
_ 1
P S
_ 2
P S
_ 3
Power Domain 3Power Domain 1
Power Domain 2
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UPF Update - DATE 2008 - Munich, Germany18
Each Step in Flow Requires
Power Intent
Synthesis
RTL Verif
Pre-Verif
Post-Verif
Signoff
Layout
Finished
GDSII
Verify retention plus power up/down cycles
Add low power elements wherever needed and optimize
for multi-voltage, multi-vth operation, plus testVerify RTL vs gates, plus low power rules
Implement optimal power grid, floorplan & switches,
P&R with power grid & layout intent/constraintsVerify final design vs. RTL, validate low power
structures
Signoff on power grid integrity, timing, power
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UPF + RTL Provide a Complete
Low Power Design Specification• Power Domains
• Power Distribution Network – Switches and Supply Nets
• Power State
• Level Shifting
• Isolation
• Retention• Switching Activity
Synthesis
UPFUPF
RTLRTL
UPFUPF
NetlistNetlist
UPFUPF
GDSIIGDSII
P&R
S i m u l a t i o n ,
L o g i c a l E q u i v a l e n c e C h e c k i n g ,
…
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UPF Benefits
• Productivity – Same intent used throughout entire
low power flow – Interoperability and productivity with
mixed EDA flows
• High Quality Results – Consistent intent throughout flow =
better checking and convergence
– IEEE P1801 approach enables
successive refinement• Simple IP Reuse
– Supports IP specification and use
– No changes needed to golden HDL
U
ni f i e d P ow er F or m a t
Synthesis
RTL Verif
Pre-Verif
Post-Verif
Signoff
Layout
Finished
GDSII
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UPF Update - DATE 2008 - Munich, Germany21
UPF Benefits
• Open standard / Interoperability
– Accellera open standards development
• Multiple donations
• All members participated on equal basis
– IEEE P1801• UPF copyright assigned to IEEE with the right tocreate derivative works
• All members have an equal vote
• No member has veto control over UPF
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Synthesizing and Implementing Low Power Designs
Arvind Narayanan
Magma Design Automation
IEEE P1801
The Unified Power Format for Low Power Designs
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UPF Update - DATE 2008 - Munich, Germany23
Power Aware Design Implementation
Register
Clock Gate
Low Power CTS
DVFS
DynamicVoltage
Supply
Circuit
Dynamic
Voltage
SupplyCircuit
Vdd
Vss
Ref
Vdd
Gnd
LS
IC
MVDD
Dynamic Power Reduction
MTCMOS
1.08v
ConstantMTCMOS
Domain
Enable
Control
Always -ON Buffers
Vdd
VssVsb
Vdb
Act ive
Act ive
Stand-by
Stand-by
Bias
Lines
BACK BIAS
Leakage Power Reduction
Power Analysis & Distr ibut ion
MTCMOSTransient Analysis
Power & IR Drop
Analysis
Power Grid
SynthesisRail EMThermal Analysis
Talus Power Talus Power
ProPro&&
Quartz RailQuartz Rail
… …
Place & RoutePlace & Route
CTSCTS
Physical SynthesisPhysical Synthesis
RTL SynthesisRTL Synthesis
MULTI-VT
Low VT Nom VT High VT
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UPF Update - DATE 2008 - Munich, Germany24
Advanced Low Power Techniques for Mobile
Devices
D S P
D o m a
i n 1
RAM
Domain 3
RAM
Domain 3
ASIC/Clocks
Domain 2
ASIC
Domain 3 ARM11+ VFP
2D/3DGraphics
Accelerator
Camer a I/F
MemoryController
P e r i p h e r a l s
L 4
I n t e r c o n n e c t
Imaging &Video
Accelerator (IVA)
InternalSRAM
LCDI/F
VideoOut
L3 Interconnect
TMS320C55xDSP
S e c u r i t y
*
* TI OMAP2
• Clock Gating
• Power awareCTS
• Retention flop
synthesis
• Clock Gating
• Power awareCTS
• Retention flop
synthesis
• Multi-VDD
• DVFS• Level Shifters
• Multi-Vt
• Multi-VDD
• DVFS
• Level Shifters
• Multi-Vt
• MTCMOS
• Isolation cells• Back-Bias
(VTCMOS)
• MTCMOS
• Isolation cells• Back-Bias
(VTCMOS)
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Design Implementation using Flow
• Domain Definition
– Power domains
– Supply rails
• Domain Relationship
– Power state tables
• Special Cells
– Retention
– Isolation
– Level shifters
– Switches
Uni f i e d P
ow er F or m a t
Synthesis
Signoff
Layout
Talus Design
Talus Power Pro
Talus Vortex
Talus Power Pro
Quartz Rail
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Defining Domains and Electrical
Conditions
create_power_domain
add_domain_element
connect_supply_net
create_supply_netcreate_supply_port
get_supply_net
merge_power_domains
set_domain_supply_net
Diagram from Andrew
1.0v
0.8v
0.8
v
PM
ctrl
logic
IS
O
LS
LS
Domain2
Constant
D o m
a i n 0 s w
i t c
h e
dDomain1
constant
Logical Electrical Physical
UPF Commands
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Level Shifters in MVDD flows
Level shifter considerations: – Pick a power domain or a set
of elements
– Select input ports, outputports, or both
– Tolerate a voltage differencethreshold
– UP shift or down SHIFT rule
– Location (self, parent, sibling,
fanout, auto) – Insert or not insert
VDD1
1.1v S
VDD 1.3v
VDD2
1.1v C
VDD1
0.9v
VDD2
1.5v
VDD 1.1v
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Level Shifter insertion using UPF
• Constant
• Variable
• Switched constant
• Switched variable
• Constant
• Variable
• Switched constant
• Switched variable
Supply Type
1.08v
Constant
1.2vConstant
0.9vSwitched
User Defined
Regions
Isolation
Cell
set_level_shifter
map_level_shifter
UPF Commands
• Automatic rule based insertion
• Length dependant and IR drop
dependent Insertion
• Electrical Rule Checks to identify
domain relationships
• Well spacing rules honored
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UPF Update - DATE 2008 - Munich, Germany29
Level Shifter Routing Topologies
• Fishbone style
– Each Level Shifter has its own secondary
tap
– Minimizes IR drop on secondary supply
• Non-Fishbone Style
– User can specify number of Level Shifter
to share a secondary tap
– Eliminates routing congestionMinimal pins share a common
‘trunk’ and route directly to the
closest power net.
LS connected by one trunk when not
routing in the ‘fishbone’ style.
GND
VDD
VDDS Y
A
VDD
GNDY
A
VDDS
GND
GND
VDD
VDDS Y
A
VDDS
GND
VDD
Y
A
Level Shifter Types
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Isolation Cells for Shut Down Domains
1.0v
PM ctrllogic
ISOLATION
D o m a i n
0 s w
i t c
h e
d
set_isolationset_isolation_control
map_isolation_cell
UPF Commands
• Automatic placement close
to domain boundary
• Options for clamp “0” or “1”
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Retention Flops in Shut Down Domains
1.0v
PM ctrllogic
ISOLATION
D o m a i n
0 s w
i t c
h e
d
RETENTION
set_retentionset_retention_control
map_retention_cell
UPF Commands
• Maintains state of domainsthat are powered down
• Automatic placement and
power connectivity
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PR RET
Switch Cell inference using UPF
Module A
Lp1
Lp2Lp3
Ln3Ln1
Ln2
Logic
pdA
set_domain_supply_net pdA
-primary_power_net PR
-primary_ground_net VSS
spAOn
SW1
create_power_switch SW1 -domain pdA -input_supply_port {inp PR}
-output_supply_port {outp RET}
SW1
UPF Commands
1.2v
200Mhz
Switched VDD
1 . 6
v
2 0 0 M h z
S w
i t c
h e
d V
D D
1.4v
200Mhz
Constant VDD
M T C M O
S
M T C M O
S
Distributed MTCMOS
Fine Grain
GlobalStandard cell specific
Grid based insertion
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Power State Table
• A power state table defines the legal combinations of
states for different domains
• create_pst command creates a PST, using a specificorder of supply nets during operation of the design
• Each row defines a valid combination of supply
states
• Power states enable optimization and verification
– Infer or verify level shifters and isolation gates
create_pst
add_pst_state
UPF Commands
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Power Integrity Sign-Off
MTCMOSTransient Analysis
Power & IR Drop
Analysis
Power Grid
Synthesis Rail EMThermal Analysis
Quartz
Rail
Power
IRDrop
ThermalIR
Drop
Delay
Rail
EM
Spice
Engine
RTLRTL
GDSIIGDSII
• Power/IR drop s ign-off solution to ensure power network integrity
• Accuracy
– Built-in spice engine for sign-off accuracy
– Static & t ransient power & IR drop analysis
• Integration
– Concurrent optimization and analysis for optimal QoR
– IR drop induced delay
• Predictability
– RTL-to-GDSII power sign-off accuracy with early predictabili ty
Support for SAIF from UPF
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IEEE P1801
The Unified Power Format for Low Power Designs
Verification of Low Power Designs
Stephen Bailey
Mentor Graphics
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UPF Update - DATE 2008 - Munich, Germany37
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow – Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
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UPF Update - DATE 2008 - Munich, Germany38
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow – Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
S t P Vi f E l
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System Power View of Example
Design -- Interleaver • Simple power
architecture
• Simple for
education
purposes• Power
domains:
– PD_tx
– PD_rx
TestBench
interleaver
in2wire
pktcntr FIFO
out2wire
RAM
Logic Hierarchy
View PD_Interleaver
Power Domain View
PD_rx
in2wire pktcntr
PD_tx
out2wire
fifo
ram
PD_tx
PD_rx
Defining the System Power
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Defining the System Power
States
OnOff OnOff Sleep
OnOnOnOff Receive
OnOff OnOnTransmit
OnOnOnOnDuplex
PD_rx_vssPD_rx_vddPD_tx_vssPD_tx_vdd
State
PD
Supply
Interleaver Power State
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Interleaver Power State
Specification
OnOff OnOff Sleep
OnOnOnOff Receive
OnOff OnOnTransmit
OnOnOnOnDuplex
PD_rx_vssPD_rx_vddPD_tx_vssPD_tx_vdd
create_pst \
interleaver_pst PD_tx_vdd vss PD_rx_vdd vss
add_pst_state
Duplex PD_tx_vddon vsson PD_rx_vddon vsson
add_pst_state
Transmit PD_tx_vddon vsson PD_rx_vddoff vsson
add_pst_state
Receive PD_tx_vddoff vsson PD_rx_vddon vsson
add_pst_state
Sleep PD_tx_vddoff vsson PD_rx_vddoff vsson
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Exploiting Power State Data
• Required for implementation QoR – Ensure electrically correct implementation
– Optimize away unneeded power logic• No level shifters if source/sink always at same voltage
• No isolation if source/sink off relative to each other
• Can be exploited in verification – Checks for missing level shifters and isolation
– Coverage, e.g., The PMB’s FSM
– Assertions to flag entry into undefined power state – …
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UPF Update - DATE 2008 - Munich, Germany43
Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow – Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
Reusable IP Power Specification
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Reusable IP Power Specification
Interleaver Contains Reusable IP Block• In2wire and out2wire blocks
are instances of the same
module
• Rdyacpt is the reusable IP
module
TestBench
interleaver
in2wire
pktcntr FIFO
out2wire
RAM
Logic Hierarchy
View
rdyacpt #(8) in2wire (
.upstream_rdy(di_rdy),
.upstream_acpt(di_acpt),
.upstream_data(di_data),
.downstream_rdy(in_rdy),
.downstream_acpt(in_acpt),
.downstream_data(input_down_data),
.reset_n(reset_n),
.clk(clk) );
rdyacpt #(8) out2wire (
.upstream_rdy(out_rdy),
.upstream_acpt(out_acpt),
.upstream_data(do_reg),
.downstream_rdy(do_rdy),
.downstream_acpt(do_acpt),
.downstream_data(do_data),
.reset_n(reset_n),
.clk(clk) );
What to Specify for IP to Keep
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What to Specify for IP to Keep
RTL & UPF Reusable• Only specify constraints for IP usage in a low
power design context:
– Power Domains:
Finest granularity of power domains for the IP
– Retention:What state must be saved on power down; restored
on power up
– Isolation:
Required logic levels under PSO conditions to ensurecorrect functionality
Finest Granularity of Power
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Finest Granularity of Power
Domains• Sets of logic that can be shutdown or run at
different voltage levels inside the domain
• For rdyacpt: – Simple logic all on at same time and all operating at
same voltage level
– Could specify no power domain and let it besubsumed into the parent instance’s power domain
– But, that would not allow us to specify isolation and
retention strategies
– Therefore, create one power domain which could be
merged later into the parent’s domain
# Assumes the caller of the UPF file containing this sets the scope
# to the rdyacpt instance (in2wire or out2wire)
create_power_domain pd_rdyacpt –include_scope
Specify IP State Requiring
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Specify IP State Requiring
Retention• Rdyacpt requires state of all registers to be
retention registers
– Likely scenario for most IP blocks – If register values aren’t saved, they need to be
reset on power up
• Note: Example utilizes changes in command structure approved by
IEEE WG specifically for use in IP situations such as this.
set_retention rdyacpt_ret –domain pd_rdyacpt
# Default is strategy applies to all elements of the domain
# Defer retention logic and implementation specifics to IP
# integrator
S if I l ti V l f IP
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Specify Isolation Values for IP• For inputs:
– Safe values when the source domain is shutdown and the IP’s
domain is on
• For outputs:
– Safe values for outputs (inactive) where relevant
– Otherwise defer to sink domain to define
• Note: Example utilizes changes in command structure approved by
IEEE WG specifically for use in IP situations such as this.
RTL code:
always @(posedge clk or negedge reset_n) …
set_isolation rdyacpt_clk_iso –domain pd_rdyacpt
-elements {clk} -clamp_value 0
set_isolation rdyacpt_rst_iso –domain pd_rdyacpt
-elements {reset_n} -clamp_value 1
# Other inputs do not trigger activity; no iso required for them
IP I t t Will
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IP Integrator Will:
• Integrate IP into system’s power architecture – Power:
• All supply nets needed by the IP will be created by the IPintegrator
• Supplies associated with the domain as required
– Logic:
• Refine retention strategies to include save/restore logiccontrol signals
• Refine isolation strategies to include isolation enablesignals
• Add any implementation details required – Map retention cells
– Add level shifting strategies
A d
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Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow – Gate-level power verification
• UPF: The Industry Standard for Low
Power Design
• Conclusions
Q ick Re ie
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Quick Review
• We have already defined: – The system power states
– IP low power design requirements
• Before we can do an RTL power awaresimulation:
– Need to define chip-level power domains – Chip supply network
– Chip retention and isolation strategies• In sufficient detail to simulate low power behavior
– May define level shifting strategies• Required before synthesis
• May defer to later RTL sign-off verification stage
Chip Power Domain Definition
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Chip Power Domain Definition
• Power domains:
– PD_Interleaver
– PD_tx
– PD_rx
PD_Interleaver
Power Domain View
PD_rx
in2wire pktcntr
PD_tx
out2wire
fifo
ram
set_scope .create_power_domain PD_Interleaver
-include_scope
create_power_domain PD_rx
-elements {in2wire pkt_counter}
create_power_domain PD_tx
-elements {out2wire fifo}
Create the Supply Network
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Create the Supply Network
• Common ground for chip
• Switched VDD for PD_rx andPD_tx
• Retention & isolation
supplies
PD_Interleaver
PD_rx
in2wire pktcntr
PD_tx
out2wire
fifo
ram
create_supply_port vss_pad –direction in
create_supply_port vdd_pad –direction in
create_supply_net vss
connect_supply_net vss –ports {vss_pad}
create_supply_net vdd
connect_supply_net vdd –ports {vdd_pad}
create_supply_net PD_rx_vdd
create_supply_net PD_tx_vdd
vdd_
pad
vss_
pad
Create the Power Switches
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for the Chip• Switch PD_rx primary supply
• Switch PD_tx primary supplycreate_power_switch rx_prim_pwr
-output_supply_port {rx_vdd_out PD_rx_vdd}
-input_supply_port {rx_vdd_in vdd}
-control_port {rx_en rx_iso_en}-on_state {PD_rx_vddon rx_vdd_in {~rx_iso_en}}
create_power_switch tx_prim_pwr
-output_supply_port {tx_vdd_out PD_tx_vdd}
-input_supply_port {tx_vdd_in vdd}
-control_port {tx_en tx_iso_en}-on_state {PD_tx_vddon tx_vdd_in {~tx_iso_en}}
PD_Interleaver
PD_rx
in2wire pktcntr
PD_tx
out2wire
fifo
ram
vdd_
pad
vss_
pad
rx_iso
_en
tx_iso
_en
Relate the Supplies to the
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pp
Domains• Switch PD_rx primary supply
• Switch PD_tx primary supply
• Uses new IEEE command structure
create_power_domain PD_Interleaver
-primary_power_net vdd
-primary_ground_net vss
create_power_domain PD_rx
-primary_power_net PD_rx_vdd
-primary_ground_net vss-default_iso_power_net vdd
-default_ret_power_net vdd
create_power_domain PD_tx
-primary_power_net PD_tx_vdd
-primary_ground_net vss-default_iso_power_net vdd
-default_ret_power_net vdd
PD_Interleaver
PD_rx
in2wire pktcntr
PD_tx
out2wire
fifo
ram
vdd_
pad
vss_
pad
rx_iso
_en
tx_iso
_en
Logic Control of Isolation &
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g
Retention• Control signals enabling PD_rx and
PD_tx isolation
• Control signals for save/restore ofPD_rx & PD_tx retention registers
• Uses new IEEE command structure
set_retention PD_rx_ret –domain PD_rx
-save_signal {rx_sleep posedge}
-restore_signal {rx_sleep negedge}
set_isolation PD_rx_iso –domain PD_rx-isolation_signal {rx_iso_en posedge}
set_retention PD_tx_ret –domain PD_tx
-save_signal {tx_sleep posedge}
-restore_signal {tx_sleep negedge}set_isolation PD_tx_iso –domain PD_tx
-isolation_signal {tx_iso_en posedge}
PD_Interleaver
PD_rx
in2wire pktcntr
PD_tx
out2wire
fifo
ram
vdd_
pad
vss_
pad
rx_iso
_en
tx_iso_en
rx_
sleep
tx_
sleep
Don’t Forget Logic Configuration
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g g g
of IP Block!• Both instances of rdyacpt’s domains
require supply associations
• IEEE WG is reviewing
easier methods for
accomplishing this level
of configuration
set_scope in2wireload_upf rdyacpt.upf
create_power_domain PD_rdyacpt
-primary_power_net .PD_rx_vdd
-primary_ground_net .vss
-default_iso_power_net .vdd
-default_ret_power_net .vdd
set_scope .out2wire
load_upf rdyacpt.upf
create_power_domain PD_rdyacpt
-primary_power_net .PD_tx_vdd
-primary_ground_net .vss-default_iso_power_net .vdd
-default_ret_power_net .vdd
IP Block Retention & Isolation
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Logic Configuration• Specify the logic control signals for isolation and
retention of both instances of rdyacpt
set_scope .in2wireset_retention rdyacpt_ret –domain pd_rdyacpt
-save_signal {rx_sleep posedge}
-restore_signal {rx_sleep negedge}
set_isolation rdyacpt_clk_iso –domain pd_rdyacpt
-isolation_signal {rx_iso_en posedge}
set_isolation rdyact_rst_iso –domain pd_rdyacpt-isolation_signal {rx_iso_en posedge}
set_scope .out2wire
set_retention rdyacpt_ret –domain pd_rdyacpt
-save_signal {tx_sleep posedge}
-restore_signal {tx_sleep negedge}
set_isolation rdyacpt_clk_iso –domain pd_rdyacpt
-isolation_signal {tx_iso_en posedge}
set_isolation rdyact_rst_iso –domain pd_rdyacpt
-isolation_signal {tx_iso_en posedge}
Do We Have Enough for RTL
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Simulation?• Yes, … But
– Retention functionality is generic
– If you know your implementation technology
• Should map to a retention simulation model
• Ensures accurate verification of save & restore
protocols
• Relative to other register control signals
Example: map_retention_cell PD_rx_ret –domain PD_rx
-lib_model_name CFRFF
Do We Have Enough for RTL
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Simulation?• Yes, … But
– Could specify level shifting strategies
– If multi-voltages employed and operating
voltages are specified
– Necessary prior to RTL implementation!
Example:
set_level_shifter PD_rx_lss –domain PD_rx
-threshold 0.2
-applies_to inputs
-rule low_to_high
UPF Simulation Semantics
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UPF Simulation Semantics
• General supply connectivity concepts – All logic elements have a set of supply nets that
deliver power to that element
• At a minimum, power and ground supplies
• UPF provides automated connection semanticsfor specific supply types: – Primary supplies
• Automatically connected to primary power, ground, etc. of thelogic extent of the domain
– Isolation supplies• Automatically connected to isolation cells created in UPF
– Retention supplies• Automatically connected to retention portion of retention
registers created in UPF
UPF Power State Semantics
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UPF Power State Semantics
• ON = Normal Functional Behavior – All supplies are ON
– Normal behavior of the logic
• OFF = Power Shutdown Behavior – At least one supply is OFF
– Functionality is disabled
– Signals driven by functionality are corrupted
• BIAS = Corrupt on Change Behavior – Not an ON state with slower, characterized performance
• That would simply be ON with different voltage level(s) of supplies
– “Retention” mode with uncharacterized performance – Un-characterized performance simulated by corrupting signals
when they change
– New in IEEE version
Agenda
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Agenda
• UPF-Based PA Design Flow
– System-level power specification
– Reusable IP block power specification
– RTL power design
– Implementation flow – Gate-level power verification
• UPF: The Industry Standard for Low
Power Design• Conclusions
Gate-Level Verification
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Gate Level Verification
• Options
– Simulation:
• PG connected netlist
• Functional netlist + UPF
– Logic Equivalency Checking
Gate-Level PG Connected Netlist
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Simulation• If:
– Your technology gate library is power-aware
• Has power, ground, bias, etc. pins• Functionality modeled power-aware
– Behavior cognizant of PSO, bias modes, etc.
• Implementation tools fully connect the supply network to the
cell instances
• Then:
– Nothing more to do as power-aware simulation
semantics are automatic – Exception: Timing (bias modes)
• Likely addressed by simulating each state separately
Gate-Level Functional Netlist +
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UPF Simulation• Technology library is NOT modeled power-aware – No PG pins on cells
– EXCEPTION: Retention registers must model “balloon latch”
retention capability
• Implementation tools must output – Gate-level functional netlist
– SDF timing – UPF that contains the supply network specification for the gate-
level design
• How power is supplied to each element in the design
– UPF would not include what is part of netlist• No retention, isolation or level shifting specification
• These cells should already be in the netlist
Logic Equivalency Checking
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g q y g
• Enhanced to perform power equivalencychecking
– Match low power functionality specified inUPF to the gate level netlist:
• Physical switches exist where required as per theUPF abstract supply switching specification
• Isolation cells with appropriate functionality onconnections between domains
• Registers with retention functionality that matches
the save/restore semantics implied or specified• Each element is supplied according to UPF
specification
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UPF Usage Experience
Yatin Trivedi
Magma Design Automation
IEEE P1801
The Unified Power Format for Low Power Designs
UPF Experience
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p
• Multiple Perspectives
– Suppliers
• Build tools & technology
• Deliver training & consulting
– Consumers
• Design & Verification engineers
UPF: Participating Companies
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• AMD
• ArchPro
• ARM
• Atrenta
• Azuro
• ChipVision
• FreeScale• IBM
• Infineon
• Intel
• LCDM Eng
• LSI Logic
• Magma• Mentor
• Nokia
• Nordic Semi
• Novas• NXP
• Qualcomm
• Si2
• STARC
• STM• Synchronous DA
• Synopsys
• TI
• Toshiba
• VaST
• Virage Logic• Xilinx
UPF Participating CompaniesTechnology donations to Accellera
UPF TSC• Mentor Graphics
• External power configuration file for verification
• Magma
• Power Management commands
• Vast
• System level modeling methodology and
format• Synopsys
• RTL constructs (Verilog and VHDL)
• Power Management commands
• Switching activity format – SAIF
• Texas Instruments
• Retention cell semantics• Atrenta, Synchronous DA
Accellera: Consumers Suppliers
IEEE: Consumers Suppliers
Low Power Solutions a Year Later
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David Peterman of TI receives UPF 1.0 on behalf of User community
from Accellera Chairman Shrenik Mehta
UPF 1.0 IndustryEndorsement & Support
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Endorsement & Support• Infineon:
The quick development and release of the UPF 1.0 standard is based on our close partnershiprelations with EDA suppliers who share the same vision and attitude in making things happen.We are convinced that UPF will support us in achieving zero-defect quality and our productivi tyobjectives, which both are key for Infineon's World class Automotive Product Portfolio.
Hartmut Hiller, Senior Director Design Methodology Automotive, Industrial & Multimarket
• Nokia:Nokia is committed to use UPF standard in SoC production flow. Finding a Power ManagementFlow for SoC design is everyone’s interest.
Mika Naula, Senior System Architect, Nokia
• Synopsys: Applauds Accellera for approving the UPF standard for low power design and verif icat ion. Weplan to deliver our UPF 1.0-based implementation and verification solution during 2007. Inresponse to customer demand for a standard that enables consistent and interoperable end-user low power flows and methodologies, Synopsys - together with Magma Design Automation,Mentor Graphics, leading end-customers and IP companies - has made strong contributions toUPF 1.0 based on our proven technologies. UPF 1.0 is ready for industry use.
Rich Goldman, Vice President, Synopsys, Strategic Market Development
UPF 1.0 IndustryEndorsement & Support
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• Magma:The speed at which the UPF standard has been developed and approveddemonstrates the power of one open, inclusive and cooperative industry-wide effort.Users wi ll realize signi ficant improvements in product ivity and quality of results byhaving a single, portable file and format with which they can specify, modify andmaintain design data. Accellera, Magma, Mentor, Synopsys and all the companies
that donated technology and expertise should be commended.
Kam Kittrell, General Manager, Design Implementation Business Unit, Magma Design Automation
• Mentor:
Designers want a single format that is simple to use, extensible, and capable ofdescribing complex power behavior. The Unified Power Format (UPF) 1.0 standardachieves this by being open and comprehensive enabling support from leading EDAvendors and customers for industry-wide adoption. Mentor is committed to
Accellera's UPF 1.0 standard as we are a leading contributor of our proventechnology to this open standard for low power design and verification
Robert Hum, Vice President & General Manager, Mentor Graphics Design Verification& Test Division
Endorsement & Support
UPF EDA Support – Digital Design
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Based on Q4 05 through Q3 06 EDAC MSS data plus other publicly available market data
UPF
66%
Other
34%
UPF EDA Support – Digital Simulation
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UPF Update - DATE 2008 - Munich, Germany75
154.7 28.9 29.34
Other
34%
UPF
66%
Based on 2007 John Cooley DeepChip DevCon Survey “ Mindshare” – 818 Respondents
Full Catalog of UPF Products
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UPF Tool Flow
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UPFUPF
UPFUPF
UPFUPF S i m u l a
t i o n ,
L o g
i c a
l E q u
i v a
l e n c e
C h e c k i
n g , …
Verilog(Netlist)
Verilog(Netlist)
Synthesis
Verilog(Netlist)
Verilog(Netlist)
P&R
HDL/RTL
HDL/RTL
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SpyGlass Power
Power & Voltage Domain Verif icationVerify and fix level shifter, isolation logic, SRPG, MTCMOS
RTL, gates, layout
Power Domain SequencingFormally prove power up/down sequencing
Power EstimationTiming-aware power estimation at RTL, gates, layout
Power Reduct ion and PlanningIntelligent power reduction and domain planning at RTL
UPF
Library data
SuppliesScope
DomainsSignals
SpyGlass Power
Power & Voltage Domain Verif icationVerify and fix level shifter, isolation logic, SRPG, MTCMOS
RTL, gates, layout
Power Domain SequencingFormally prove power up/down sequencing
Power EstimationTiming-aware power estimation at RTL, gates, layout
Power Reduct ion and PlanningIntelligent power reduction and domain planning at RTL
UPF
Library data
SuppliesScope
DomainsSignals
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MPSim Multi-CPU
Simulation
MPSim Multi-CPU
Simulation
Test benchRTL
Designer
Debug
Designer
DebugProtoMeter
Coverage
ProtoMeter
Coverage
UPF Specification Simulate power off corruption
Simulate retention and
save/restore of states
Simulate isolation and clamping
Trace complete power network and
switches
Visualize power switch states
Visualize the states of powered off
blocks throughout simulation
Annotate powered off signals
Automate power verification
combinations
Verify all possible powercombinations
Power verification closure
MPSim
Designer
ProtoMeter
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Placed gates
Balanced clocks)
Placed gates
UPF Q4-07)
Gate level
netlist
GDSII
PowerCentric™Low Power Clock
Implementation
Physical
Synthesis
Routing
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l y m p u
s - S o C
Predictable Success
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Design Compiler Ultra
Power Compiler
DFT Compiler/DFT MAX
UPFUPF
RTLRTL
UPFUPF
NetlistNetlist
UPFUPF
GDSIIGDSII
IC Compiler TetraMax
V C S
, F o r m a
l i t y
, L e
d a
P r i m e
T i m e
( S I , P X )
P r i m e R
a i l
Innovator
DesignWare IP
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IPrima Foundation nHigh-Densit y Logic High-Density Memory B
ase I/O
ASAP Logic ASAP Logic
Metal ProgrammableMetal Programmable
High-Speed
High-Density
Standard CellsStandard Cells
High-Speed
Ultra-High-Density
Ultra-Low-Power
ECO
STAR Memory SystemSTAR Memory System
Star Memories
BIST & Repair IP
ASAP Memory ASAP MemoryHigh-Speed
Ultra-Low-Power
NOVeANOVeA Non Volatile Memory
Specialty I/OsSpecialty I/Os
SSTL-2
HSTL-2
PCI and PCI-X
USB1.1
*all included in
Base I/O package
Value Added IPValue Added IP
Low Power Methodology Manual
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Contact: [email protected]
Conclusion
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• User community is actively guiding UPF
– All leading users enthusiastically participate
– Concepts are production proven
• EDA community is strongly behind UPF
– Supported by 8 out of 9 leading vendors – Interoperability is the key to success
• IEEE standardization On Track
– World-wide adoption assured
– Broad education effort to follow
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Questions & Answers