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www.flextiles.eu
www.thalesgroup.com
Research & Technology
HiP
EA
C'1
2
FlexTileswww.flextiles.eu
Fabrice Lemonnier, DATE 2012
Project coordinator: THALES
Funding budget: 3,670,000€
Starting date: 15/10/2011
Duration: 36 months
www.thalesgroup.com
3 / 3 / 22
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www.flextiles.eu
Industrial issues
Embedded Real-Time Applications
low power consumption
low volume
Adapt to environment dynamicity, flexibility & dependability
Smart cameraCognitive radio UAV
Time To Market
adaptable product line
Fault-tolerance
4 / 4 / 22
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ALE
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www.flextiles.eu
Challenges
address increasing application dynamicity
-using self-adaptive capabilities
increase software development productivity of manycore
-reduce Time to Market
-reuse of legacy software
-reuse of hardware IPs.
increase accessibility to manycore technologies
-propose a European alternative on the worldwide market of this technology
increase energy efficiency
-for embedded systems
-and High-Performance Computing (HPC) systems.
5 / 5 / 22
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ALE
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011.
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rtp
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TE
'12
www.flextiles.eu
Objectives of the project
1) develop a heterogeneous manycore based on available IPs
definition of generic interfaces
2) improve programming efficiency of heterogeneous manycores
3) self-adaptation
thanks to virtualisation layer
4) develop a dynamic reconfigurable technology
pre-emption and relocation capabilities.
6 / 6 / 22
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ALE
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011.
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'12
www.flextiles.eu
Other Projects
Existing manycores provide static allocation and sheduling
• TILE-Gx™ 8000 from Tilera (16 to 100 cores)
• MPPA® from Kalray (256 to 1024 cores)
• PicoArray from Picochip (248 cores)
• FlexTiles (1 to thousands of cores)
Projects:
Morpheus
Hardware Flexibility / dynamicity
Prog
ram
mab
ility
FlexTiles
FOSFOR
ReconOSAether
Apple-Core
Tsar Mosart
reconfigurable inside
ADAM
7 / 7 / 22
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ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
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DA
TE
'12
www.flextiles.eu
1) develop a heterogeneous manycore system on a chip
Homogeneous GPP nodes
Heterogeneous acceleratorsnodes
GPP Node
AI
DSPNode
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Generic Interfaces
eFPGA Domain (Reconfigurable HW acc.)
Dedicated Accelerator
Node
Dedicated Accelerator
Node
8 / 8 / 22
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oval
. ©
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ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
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DA
TE
'12
www.flextiles.eu
1) Execution model
Master Nodes
Slave Nodes
GPP
eFPGA nodesDSP nodes
GPP Node
acceleratornode
NI
NoC
NI
Accelerator Interface (AI)
accrequests
control / status
DMA
DMArequests
data
9 / 9 / 22
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ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
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DA
TE
'12
www.flextiles.eu
2) programming efficiency of heterogeneous manycores
Virtualisation layer
relocatable binary code
Parallelisation, partioning
Application
Hardware Nodes
Compilation Synthesis, P&Rrelocatable bitstream
Hardware Abstraction Layer
Hardware Abstraction Layer API
Operating Library API
Kernel Resource Monitoring &
Allocation
DIAGNOSISO = F(L)
ACTION
SYSTEM
toolchain
operating library
heterogenousmanycore
MONITORING
10 /10 / 22
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ALE
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011.
Tem
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e t
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vers
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DA
TE
'12
www.flextiles.eu
3) self-adaptation: virtualization layer
Heterogeneous Hardware
Controlled byKernel and
Virtualization layerEthernet
IMDCT MatrixMult
Accelerator/Virtual Code
Dynamicallocation / binding
DIAGNOSISO = F(L)
ACTION
SYSTEM
MONITORING
Mapping
GPP Node
AI
DSPNode
NI
GPP Node
NI
NoC
NI NI NI
AI AI
NI
Config. Ctrl.
DDR Ctrl.
NI
GPP Node
NI
I/O
NI
Dedicated Accelerator
Node
Dedicated Accelerator
Node
eFPGA Domain (Reconfigurable HW acc.)
11 /11 / 22
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rmat
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ent
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pert
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ALE
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hibi
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hale
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oval
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ALE
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011.
Tem
plat
e t
rtp
vers
ion
7.0
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DA
TE
'12
www.flextiles.eu
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
4) develop a new dynamic reconfigurable technology
Homogeneous manycore
FlexTiles: a 3D stacked chip
12 /12 / 22
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rmat
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s do
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ent
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ALE
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You
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ictly
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hibi
ted
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hale
s pr
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ten
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oval
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ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
DA
TE
'12
www.flextiles.eu
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
4) develop a new dynamic reconfigurable technology
Homogeneous manycore
FlexTiles: a 3D stack chip
NoC
Two layers communicating through one or several NoCs
13 /13 / 22
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ALE
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ictly
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hibi
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hale
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oval
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ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
DA
TE
'12
www.flextiles.eu
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
4) develop a new dynamic reconfigurable technology
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
3D stacked reconfigurable layer
14 /14 / 22
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ALE
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You
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oval
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
DA
TE
'12
www.flextiles.eu
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
4) develop a new dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Map Accelerated functions
15 /15 / 22
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ALE
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ictly
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hibi
ted
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hale
s pr
ior
writ
ten
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oval
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
DA
TE
'12
www.flextiles.eu
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
4) develop a new dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Duplicate
16 /16 / 22
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ALE
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t is
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ictly
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hibi
ted
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hale
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oval
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TH
ALE
S 2
011.
Tem
plat
e t
rtp
vers
ion
7.0
.8
DA
TE
'12
www.flextiles.eu
Tile Tile Tile
Tile Tile Tile
Tile Tile Tile
4) develop a new dynamic reconfigurable technology
3D stacked reconfigurable layer
Homogeneous manycore
NoC
FlexTiles: a 3D stack chip
Migrate
17 /17 / 22
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ALE
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ALE
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011.
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plat
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DA
TE
'12
www.flextiles.eu
4) develop a new dynamic reconfigurable technology
I/O
NoC
GPP
Acc1
GPP
Acc1
GPP
Acc3
GPP
Acc4I/O
GPP
DDR ctrl
GPP
thread1 thread2 thread3 thread4
API
thread1 thread2
thread1 thread2thread3 thread4
API
thread1
thread2
Application
Tools for parallelisation and mapping
Acc1
Acc1
Acc3
Acc4
Dynamic allocation
Dynamic allocation
Tools for parallelisation and mapping
18 /18 / 22
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ALE
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ALE
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TE
'12
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NoC QoS
chip
GPP
icache
dcache
dLMEM GPP
NI
iLMEM eFPGA
eFPGA
dLMEM eFPGA
iLMEM DSP
DSP
dLMEM DSP
DDR
NI+
DDR ctrl
on chipshMEM
NI NI
controlNOC
bitstreamNOC
dataNOC
instructionNOC
test/debugNOC
19 /19 / 22
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ALE
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'12
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ANoC (CEA)
GALS: asynchronous logic in nodes, local synchronous coreshighly scalablebetween nodes: no global clock, no even local clockpower efficient and dependablepacket switchingwormhole protocollow latency
20 /20 / 22
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AEtheral NoC (TUe)
Guaranteed levels of services and performancesContention free routing by constructionwormhole routing specified at design time Globally Synchronous with time slots
21 /21 / 22
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Results
• Versatile accelerated multicore architecture• SystemC simulator and FPGA demonstrators
• Physical design of embedded reconfigurable technology• To be implemented on a 3D stacked layer
• HW and SW interfaces to address heterogenous manycores• Create or use standards
• Virtualisation layer code, kernel• Self adaptive
• Heterogeneous manycore Tool chain• Design both multicore and accelerated functions at the same time
• Network selection according to required QoS
22 /22 / 22
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Consortium and questions
Partners & Third Party
Country Main scientific and technical contributions
THALES France Infrastructure and applications
KIT Germany Virtualisation layer
TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United Kingdom
FPGA Demonstrator
ACE Netherlands Parallelisation and compilation Tools
8 partners in 5 countries
23 /23 / 22
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