13

TAB

2

DPAK

D(2, TAB)

G(1)

S(3)AM01475V1

FeaturesOrder code VDS RDS(on) max. ID PTOT

STD12N60M6 600 V 450 mΩ 9 A 96 W

• Reduced switching losses• Lower RDS(on) per area vs previous generation• Low gate input resistance• 100% avalanche tested• Zener-protected

Applications• Switching applications• LLC converters• Boost PFC converters

DescriptionThe new MDmesh M6 technology incorporates the most recent advancements to thewell-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronicsbuilds on the previous generation of MDmesh devices through its new M6technology, which combines excellent RDS(on) per area improvement with one of themost effective switching behaviors available, as well as a user-friendly experience formaximum end-application efficiency.

Product status link

STD12N60M6

Product summary

Order code STD12N60M6

Marking 12N60M6

Package DPAK

Packing Tape and reel

N-channel 600 V, 390 mΩ typ., 9 A, MDmesh M6 Power MOSFET in a DPAK package

STD12N60M6

Datasheet

DS13291 - Rev 1 - April 2020For further information contact your local STMicroelectronics sales office.

www.st.com

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ±25 V

IDDrain current (continuous) at Tcase = 25 °C 9

ADrain current (continuous) at Tcase = 100 °C 6

IDM (1) Drain current (pulsed) 24 A

PTOT Total power dissipation at Tcase = 25 °C 96 W

IAR (2) Avalanche current, repetitive or not repetitive 1.8 A

EAS (3) Single pulse avalanche energy 130 mJ

dv/dt (4) Peak diode recovery voltage slope 15V/ns

dv/dt (5) MOSFET dv/dt ruggedness 100

Tstg Storage temperature range-55 to 150 °C

Tj Operating junction temperature range

1. Pulse width is limited by safe operating area.2. Pulse width limited by Tjmax.

3. Starting Tj = 25 °C, ID = IAR, VDD = 50 V.

4. ISD ≤ 9 A, di/dt = 400 A/μs, VDS(peak) < V(BR)DSS, VDD = 400 V

5. VDS ≤ 480 V

Table 2. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 1.3°C/W

Rthj-pcb(1) Thermal resistance junction-pcb 50

1. When mounted on an 1-inch² FR-4, 2 Oz copper board.

STD12N60M6Electrical ratings

DS13291 - Rev 1 page 2/15

2 Electrical characteristics

(Tcase = 25 °C unless otherwise specified)

Table 3. Static

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 600 V

IDSS Zero gate voltage drain current

VGS = 0 V, VDS = 600 V 1

µAVGS = 0 V, VDS = 600 V,Tcase = 125 °C (1) 100

IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3.25 4 4.75 V

RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4.5 A 390 450 mΩ

1. Defined by design, not subject to production test.

Table 4. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance

VDS = 100 V, f = 1 MHz, VGS = 0 V

- 452 -

pFCoss Output capacitance - 39 -

Crss Reverse transfer capacitance - 4.5 -

Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 85 - pF

RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6 - Ω

Qg Total gate charge VDD = 480 V, ID = 9 A,

VGS = 0 to 10 V

(see Figure 14. Test circuit for gatecharge behavior)

- 12.3 -

nCQgs Gate-source charge - 3 -

Qgd Gate-drain charge - 6.5 -

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0to 80% VDSS.

Table 5. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 300 V, ID = 4.5 A,

RG = 4.7 Ω, VGS = 10 V

(see Figure 13. Test circuit forresistive load switching times andFigure 18. Switching timewaveform)

- 16.6 -

nstr Rise time - 6.4 -

td(off) Turn-off delay time - 23.9 -

tf Fall time - 9.9 -

STD12N60M6Electrical characteristics

DS13291 - Rev 1 page 3/15

Table 6. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 9 A

ISDM (1) Source-drain current (pulsed) - 24 A

VSD (2) Forward on voltage VGS = 0 V, ISD = 9 A - 1.6 V

trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs,

VDD = 60 V

(see Figure 15. Test circuit forinductive load switching and dioderecovery times)

- 174 ns

Qrr Reverse recovery charge - 1.27 µC

IRRM Reverse recovery current - 14.6 A

trr Reverse recovery time ISD = 9 A, di/dt = 100 A/µs,

VDD = 60 V, Tj = 150 °C

(see Figure 15. Test circuit forinductive load switching and dioderecovery times)

- 241 ns

Qrr Reverse recovery charge - 1.9 µC

IRRM Reverse recovery current - 15.6 A

1. Pulse width is limited by safe operating area.2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%.

STD12N60M6Electrical characteristics

DS13291 - Rev 1 page 4/15

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area

GADG260320201609SOA

10 1

10 0

10 -1

10 -1 10 0 10 1 10 2

ID (A)

VDS (V)

tp =10 µs

tp =1 µs

tp =1 ms

tp =10 ms

V(BR)DSS

IDM

Opera

tion i

n this

area

is lim

ited b

y RDS(

on)

RDS(on) max.

single pulse

TC = 25 °CTJ ≤ 150 °CVGS=10 V

tp =100 µs

Figure 2. Maximum transient thermal impedance

GADG260320201610ZTH

100

10-1

10-2

10-6 10-5 10-4 10-3 tp (s)

4duty

s

Rthj-c = 1.3 °C/W

3

Zthj-c(°C/W)

Figure 3. Typical output characteristics

GIPG131220181132OCH

24

20

16

12

8

4

00 2 4 6 8 10 12 14 16 18

ID (A)

VDS (V)

VGS = 10 V

VGS = 6 V

VGS = 7 V

VGS = 8 V

VGS = 9 V

VGS = 5 V

Figure 4. Typical transfer characteristics

GIPG131220181133TCH

24

20

16

12

8

4

01 2 3 4 5 6 7 8 9

ID (A)

VGS (V)

VDS =20 V

Figure 5. Typical gate charge characteristics

GADG230320201125QVG

600

500

400

300

200

100

0

12

10

8

6

4

2

00 2 4 6 8 10 12 14

VGS (V)

Qg (nC)

VDD = 480 VID = 9 A

VDS (V)

Qgs Qgd

Qg

VDS

Figure 6. Typical drain-source on-resistance

GADG260320201616RID

420

410

400

390

380

3700 2 4 6 8 ID (A)

VGS =10 V

RDS(on)

(mΩ)

STD12N60M6Electrical characteristics (curves)

DS13291 - Rev 1 page 5/15

Figure 7. Typical capacitance characteristics

GIPG131220181130CVR

10 3

10 2

10 1

10 0

10 -1 10 0 10 1 10 2

C (pF)

VDS (V)

CISS

COSS

CRSS

f = 1 MHz

Figure 8. Typical output capacitance stored energy

ADG131220181241EOS

4

3

2

1

00 100 200 300 400 500

EOSS (µJ)

VDS (V)

Figure 9. Normalized gate threshold voltage vstemperature

GIPG131220181031VTH

1.1

1.0

0.9

0.8

0.7

0.6-75 -25 25 75 125

VGS(th) (norm.)

TJ (°C)

ID = 250 μA

Figure 10. Normalized on-resistance vs temperature

GIPG131220181123RON

2.2

1.8

1.4

1.0

0.6

0.2-75 -25 25 75 125

RDS(on) (norm.)

VGS = 10 V

TJ (°C)

Figure 11. Normalized breakdown voltage vs temperature

GIPG131220181128BDV

1.08

1.04

1.00

0.96

0.92

0.88-75 -25 25 75 125

V(BR)DSS (norm.)

ID = 1 mA

TJ (°C)

Figure 12. Typical reverse diode forward characteristics

GADG230320201128SDF

1.1

1.0

0.9

0.8

0.7

0.6

0.50 2 4 6 8

VSD (V)

ISD (A)

Tj = -50 °C

Tj = 25 °C

Tj = 150 °C

STD12N60M6Electrical characteristics (curves)

DS13291 - Rev 1 page 6/15

3 Test circuits

Figure 13. Test circuit for resistive load switching times

AM01468v1

VD

RG

RL

D.U.T.

2200μF VDD

3.3μF+

pulse width

VGS

Figure 14. Test circuit for gate charge behavior

AM01469v10

47 kΩ

2.7 kΩ

1 kΩ

IG= CONST100 Ω D.U.T.

+pulse width

VGS

2200μF

VG

VDD

RL

Figure 15. Test circuit for inductive load switching anddiode recovery times

AM01470v1

AD

D.U.T.S

B

G

25 Ω

A A

B B

RG

GD

S

100 µH

µF3.3 1000

µF VDD

D.U.T.

+

_

+

fastdiode

Figure 16. Unclamped inductive load test circuit

AM01471v1

VD

ID

D.U.T.

L

VDD+

pulse width

Vi

3.3µF

2200µF

Figure 17. Unclamped inductive waveform

AM01472v1

V(BR)DSS

VDDVDD

VD

IDM

ID

Figure 18. Switching time waveform

AM01473v1

0

VGS 90%

VDS

90%

10%

90%

10%

10%

ton

td(on) tr

0

toff

td(off) tf

STD12N60M6Test circuits

DS13291 - Rev 1 page 7/15

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance. ECOPACK specifications, grade definitions and productstatus are available at: www.st.com. ECOPACK is an ST trademark.

4.1 DPAK (TO-252) type A2 package information

Figure 19. DPAK (TO-252) type A2 package outline

0068772_type-A2_rev27

STD12N60M6Package information

DS13291 - Rev 1 page 8/15

Table 7. DPAK (TO-252) type A2 mechanical data

Dim.mm

Min. Typ. Max.

A 2.20 2.40

A1 0.90 1.10

A2 0.03 0.23

b 0.64 0.90

b4 5.20 5.40

c 0.45 0.60

c2 0.48 0.60

D 6.00 6.20

D1 4.95 5.10 5.25

E 6.40 6.60

E1 5.10 5.20 5.30

e 2.159 2.286 2.413

e1 4.445 4.572 4.699

H 9.35 10.10

L 1.00 1.50

L1 2.60 2.80 3.00

L2 0.65 0.80 0.95

L4 0.60 1.00

R 0.20

V2 0° 8°

STD12N60M6DPAK (TO-252) type A2 package information

DS13291 - Rev 1 page 9/15

Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm)

FP_0068772_27

STD12N60M6DPAK (TO-252) type A2 package information

DS13291 - Rev 1 page 10/15

4.2 DPAK (TO-252) packing information

Figure 21. DPAK (TO-252) tape outline

P1A0 D1

P0

FW

E

D

B0K0

T

User direction of feed

P2

10 pitches cumulativetolerance on tape +/- 0.2 mm

User direction of feed

R

Bending radius

B1

For machine ref. onlyincluding draft andradii concentric around B0

AM08852v1

Top covertape

STD12N60M6DPAK (TO-252) packing information

DS13291 - Rev 1 page 11/15

Figure 22. DPAK (TO-252) reel outline

A

D

B

Full radius

Tape slot in core for tape start

2.5mm min.width

G measured at hub

C

N

40mm min. access hole at slot location

T

AM06038v1

Table 8. DPAK (TO-252) tape and reel mechanical data

Tape Reel

Dim.mm

Dim.mm

Min. Max. Min. Max.

A0 6.8 7 A 330

B0 10.4 10.6 B 1.5

B1 12.1 C 12.8 13.2

D 1.5 1.6 D 20.2

D1 1.5 G 16.4 18.4

E 1.65 1.85 N 50

F 7.4 7.6 T 22.4

K0 2.55 2.75

P0 3.9 4.1 Base qty. 2500

P1 7.9 8.1 Bulk qty. 2500

P2 1.9 2.1

R 40

T 0.25 0.35

W 15.7 16.3

STD12N60M6DPAK (TO-252) packing information

DS13291 - Rev 1 page 12/15

Revision history

Table 9. Document revision history

Date Version Changes

01-Apr-2020 1 First release.

STD12N60M6

DS13291 - Rev 1 page 13/15

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

STD12N60M6Contents

DS13291 - Rev 1 page 14/15

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2020 STMicroelectronics – All rights reserved

STD12N60M6

DS13291 - Rev 1 page 15/15