PWP RHB NTwww.ti.com

FEATURES APPLICATIONS

DESCRIPTION

Delayx0

12−Bit GrayscalePWM Control

DC Register

GS Register

DC EEPROM

Constant CurrentDriver

LED Open Detection

TemperatureError Flag

(TEF)

Max. OUTnCurrent

Delayx1

12−Bit GrayscalePWM Control

DC Register

GS Register

DC EEPROM

Constant CurrentDriver

LED Open Detection

Delayx15

6−Bit Dot

12−Bit GrayscalePWM Control

DC Register

GS Register

DC EEPROM

Constant CurrentDriver

LED Open Detection

OUT0

OUT1

OUT15

SOUT

SINSCLK

IREF

XERR

XLAT

GSCLKBLANK

DCPRG

DCPRG

DCPRG

VPRG

VPRG

VPRG

GNDVCC

VPRG

InputShift

Register

InputShift

Register

VPRG 110

2312

191180

9590

116

5

VPRG

0

0

95

96

191

LED OpenDetection

(LOD)

5

9590

6 11

DCPRG

0

192

96

01

01 0

1

01

GS Counter CNT

CNT

CNT

CNT

96

96

StatusInformation:

LOD,TED,

DC DATA

1920

191

1

0

0

1

VREF =1.24 V

Correction

6−Bit DotCorrection

6−Bit DotCorrection

01Blank

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

• Monocolor, Multicolor, Fullcolor LED Displays• 16 Channels• LED Signboards• 12 bit (4096 Steps) Grayscale PWM Control• Display Backlighting• Dot Correction• General, High-Current LED Drive– 6 bit (64 Steps)

– Storable in Integrated EEPROM• Drive Capability (Constant Current Sink)

The TLC5940 is a 16-channel constant-current sink– 0 mA to 60 mA (VCC < 3.6 V) LED driver. Each channel has an individually adjust-– 0 mA to 120 mA (VCC > 3.6 V) able 4096-step grayscale PWM brightness control

and a 64-step constant-current sink (dot correction).• LED Power Supply Voltage up to 17 VThe dot correction adjusts the brightness variations• VCC = 3 V to 5.5 V between LED channels and other LED drivers. The

• Serial Data Interface, SPI comp. dot correction data is stored in an integratedEEPROM. Both grayscale control and dot correction• Controlled In-Rush Currentare accessible via a serial interface. A single external• 30-MHz Data Transfer Rateresistor sets the maximum current value of all 16

• CMOS Level I/O channels.• Error Information The TLC5940 features two error information circuits.

– LOD: LED Open Detection The LED open detection (LOD) indicates a broken ordisconnected LED at an output terminal. The thermal– TEF: Thermal Error Flagerror flag (TEF) indicates an overtemperature con-dition.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright © 2004–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS.

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

TA PACKAGE (1) PART NUMBER

-40°C to 85°C 28-pin HTSSOP PowerPAD™ TLC5940PWP

-40°C to 85°C 32-pin 5 mm x 5 mm QFN TLC5940RHB

-40°C to 85°C 28-pin PDIP TLC5940NT

(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI website at www.ti.com.

over operating free-air temperature range (unless otherwise noted) (1)

UNIT

VI Input voltage range (2) VCC –0.3 V to 6 V

IO Output current (dc) 130 mA

VI Input voltage range V(BLANK), V(DCPRG), V(SCLK), V(XLAT) –0.3 V to VCC +0.3 V

V(SOUT), V(XERR) –0.3 V to VCC +0.3 VVO Output voltage range

V(OUT0) to V(OUT15) –0.3 V to 18 V

EEPROM program range V(PRG) –0.3 V to 24 V

EEPROM write cycles 50

HBM (JEDEC JESD22-A114, Human Body Model) 2 kVESD rating

CBM (JEDEC JESD22-C101, Charged Device Model) 500 V

Tstg Storage temperature range –55°C to 150°C

TA Operating ambient temperature range –40°C to 85°C

HTSSOP (PWP) (4) 31.58°C/W

Package thermal impedance (3) QFN (RHB) 35.9°C/W

PDIP (NP) 48°C/W

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.(3) The package thermal impedance is calculated in accordance with JESD 51-7.(4) With PowerPAD soldered on PCB with 2 oz. trace of copper. See SLMA002 for further information.

2

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RECOMMENDED OPERATING CONDITIONS

DISSIPATION RATINGS

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

MIN NOM MAX UNIT

DC CHARACTERISTICS

VCC Supply Voltage 3 5.5 V

VO Voltage applied to output (OUT0–OUT15) 17 V

VIH High-level input voltage 0.8 VCC VCC V

VIL Low-level input voltage GND 0.2 VCC V

IOH High-level output current VCC = 5 V at SOUT –1 mA

IOL Low-level output current VCC = 5 V at SOUT, XERR 1 mA

OUT0 to OUT15, VCC < 3.6 V 60 mAIOLC Constant output current

OUT0 to OUT15, VCC > 3.6 V 120 mA

V(PRG) EEPROM program voltage 20 22 23 V

TA Operating free-air temperature range -40 85 °C

AC CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)

f(SCLK) Data shift clock frequency SCLK 30 MHz

f(GSCLK) Grayscale clock frequency GSCLK 30 MHz

twh0/twl0 SCLK pulse duration SCLK = H/L (see Figure 8) 16 ns

twh1/twl1 GSCLK pulse duration GSCLK = H/L (see Figure 13) 16 ns

twh2 XLAT pulse duration XLAT = H (see Figure 11) 20 ns

twh3 BLANK pulse duration BLANK = H (see Figure 13) 20 ns

tsu0 SIN–SCLK (see Figure 11) 10 ns

tsu1 SCLK–XLAT (see Figure 11) 10 ns

tsu2 VPRG–SCLK (see Figure 6) 10 nsSetup time

tsu3 VPRG–XLAT (see Figure 6) 10 ns

tsu4 BLANK–GSCLK (see Figure 13) 10 ns

tsu5 VPRG–DCPRG 1 ms

th0 SCLK–SIN (see Figure 11) 10 ns

th1 XLA–SCLK (see Figure 11) 10 ns

th2 SCLK–VPRG (see Figure 6) 10 nsHold Time

th3 XLAT–VPRG (see Figure 6) 10 ns

th4 BLANK–GSCLK (see Figure 13) 10 ns

th5 DCPRG–VPRG 1 ms

tprog Programming time for EEPROM 20 ms

POWER RATING DERATING FACTOR POWER RATING POWER RATINGPACKAGE TA < 25°C ABOVE TA = 25°C TA = 70°C TA = 85°C

28-pin HTSSOP with 3958 mW 31.67 mW/°C 2533 mW 2058 mWPowerPAD™ (1)soldered

28-pin HTSSOP with PowerPAD™ un- 2026 mW 16.21 mW/°C 1296 mW 1053 mWsoldered

32-pin QFN (1) 3482 mW 27.86 mW/°C 2228 mW 1811 mW

28-pin PDIP 2456 mW 19.65 mW/°C 1572 mW 1277 mW

(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.

3

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ELECTRICAL CHARACTERISTICS

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH High-level output voltage IOH = -1 mA, SOUT VCC– 0.5 V

VOL Low-level output voltage IOL = 1 mA, SOUT 0.5 V

VI = VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, –1 1XLATµAVI = GND; VPRG –1 1II Input current

VI = VCC; VPRG 50

VI = 22 V; VPRG; DCPRG = VCC 4 10 mA

No data transfer, all output OFF, 0.9 6VO = 1 V, R(IREF) = 10 kΩ

No data transfer, all output OFF, 5.2 12VO = 1 V, R(IREF) = 1.3 kΩICC Supply current mA

Data transfer 30 MHz, all output ON, 16 25VO = 1 V, R(IREF) = 1.3 kΩ

Data transfer 30 MHz, all output ON, 30 60VO = 1 V, R(IREF) = 640 Ω

IO(LC) Constant output current All output ON, VO = 1 V, R(IREF) = 640 Ω 54 61 69 mA

All output OFF, VO = 15 V, R(IREF) = 640 Ω,Ilkg Leakage output current 0.1 µAOUT0 to OUT15

All output ON, VO = 1 V, R(IREF) = 640 Ω, ±1 ±4OUT0 to OUT15, –20°C to 85°C

All output ON, VO = 1 V, R(IREF) = 640 Ω, ±1 ±8OUT0 to OUT15∆IO(LC0) Constant current error %

All output ON, VO = 1 V, R(IREF) = 320 Ω, ±1 ±6OUT0 to OUT15, –20°C to 85°C

All output ON, VO = 1 V, R(IREF) = 320 Ω, ±1 ±8VCC = 4.5 V to 5.5 V, OUT0 to OUT15

Device to device, Averaged current from OUT0 to –2∆IO(LC1) Constant current error ±4 %OUT15, R(IREF) = 1920 Ω (20 mA) +0.4

Device to device, Averaged current from OUT0 to –2.7∆IO(LC2) Constant current error ±4 %OUT15, R(IREF) = 480 Ω (80 mA) +2

All output ON, VO = 1 V, R(IREF) = 640 Ω ±1 ±4 %/VOUT0 to OUT15Power supply rejection ratio,∆IO(LC3) PSRR All output ON, VO = 1 V, R(IREF) = 320 Ω , ±1 ±6 %/VOUT0 to OUT15

All output ON, VO = 1 V to 3 V, R(IREF) = 640 Ω, ±2 ±6 %/VOUT0 to OUT15∆IO(LC4) Load regulation

All output ON, VO = 1 V to 3 V, R(IREF) = 320 Ω, ±2 ±8 %/VOUT0 to OUT15

T(TEF) Thermal error flag threshold Junction temperature (1) 150 170 °C

V(LED) LED open detection threshold 0.3 0.4 V

Reference voltageV(IREF) RI(REF) = 640 Ω 1.20 1.24 1.28 Voutput

(1) Not tested. Specified by design

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SWITCHING CHARACTERISTICS

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

VCC = 3 V to 5.5 V, TA = -40°C to 85°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tr0 SOUT 16Rise time ns

tr1 OUTn, VCC = 5 V, TA = 60°C, DCx = 3F 10 30

tf0 SOUT 16Fall time ns

tf1 OUTn, VCC = 5 V, TA = 60°C, DCx = 3F 10 30

tpd0 SCLK–SOUT (see Figure 11) 30 ns

tpd1 DCPRG–OUT0 30 ns

tpd2 BLANK–OUT0 (see Figure 13 ) 60 nsPropagation delay time

tpd3 OUTn - XERR (see Figure 13 ) 1000 ns

tpd4 GSCLK–OUT0 (see Figure 13 ) 60 ns

tpd5 XLAT–IOUT (dot correction) 1000 ns

td Output delay time OUTn–OUT(n+1) (see Figure 13 ) 20 30 ns

5

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DEVICE INFORMATION

123

4 56789

1011121314

282726

252423222120

1918171615

GNDBLANK

XLATSCLK

SINVPRGOUT0OUT1OUT2OUT3OUT4OUT5OUT6OUT7

VCCIREFDCPRGGSCLKSOUTXERROUT15OUT14OUT13OUT12OUT11OUT10OUT9OUT8

PWP PACKAGE(TOP VIEW)

ThermalPAD

THERMALPAD

GS

CLK

24

SO

UT

23

XE

RR

22

OU

T15

21

OU

T14

20

OU

T13

19

OU

T12

18

OU

T11

17

OUT1016

OUT915

OUT814

NC13

NC12

OUT711

OUT610

OUT59

OU

T4

8

OU

T3

7

OU

T2

6

OU

T1

5

OU

T0

4

VP

RG

3

SIN

2

SC

LK1

DCPRG 25

IREF 26

VCC 27

NC 28

NC 29

GND 30

BLANK 31

XLAT 32

RHB PACKAGE(TOP VIEW)

NC − No internal connection

1

2

3

4

5

6

7

8

9

10

11

12

13

14

18

17

16

15

22

21

20

19

26

25

24

23

28

27

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

GND

VCC

IREF

DCPRG

GSCLK

SOUT

XERR

OUT15

SCLK

XLAT

BLANK

OUT0

VPRG

SIN

NT PACKAGE(TOP VIEW)

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

6

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TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

DEVICE INFORMATION (continued)TERMINAL FUNCTION

TERMINAL

NO. I/O DESCRIPTIONNAME

DIP PWP RHB

Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is alsoBLANK 23 2 31 I reset. When BLANK = L, OUTn are controlled by grayscale PWM control.

Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H,DCPRG 19 26 25 I DC is connected to the DC register.

DCPRG is also controls EEPROM writing, when VPRG = V(PRG)

GND 22 1 30 G Ground

GSCLK 18 25 24 I Reference clock for grayscale PWM control

IREF 20 27 26 I Reference current terminal

12, 13,NC – – No connection28, 29

OUT0 28 7 4 O Constant current output

OUT1 1 8 5 O Constant current output

OUT2 2 9 6 O Constant current output

OUT3 3 10 7 O Constant current output

OUT4 4 11 8 O Constant current output

OUT5 5 12 9 O Constant current output

OUT6 6 13 10 O Constant current output

OUT7 7 14 11 O Constant current output

OUT8 8 15 14 O Constant current output

OUT9 9 16 15 O Constant current output

OUT10 10 17 16 O Constant current output

OUT11 11 18 17 O Constant current output

OUT12 12 19 18 O Constant current output

OUT13 13 20 19 O Constant current output

OUT14 14 21 20 O Constant current output

OUT15 15 22 21 O Constant current output

SCLK 25 4 1 I Serial data shift clock

SIN 26 5 2 I Serial data input

SOUT 17 24 23 O Serial data output

VCC 21 28 27 I Power supply voltage

Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, theVPRG 27 6 3 I device is in DC mode. When VPRG = V(PRG), DC register data can programmed into DC

EEPROM with DCPRG=HIGH.

XERR 16 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.

Data latch. Note that the internal connections are switched by VPRG. At XLAT↑ (VPRG =XLAT 24 3 32 I GND), GS register gets new data. At XLAT↑ (VPRG = VCC), DC register gets new data.

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PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

VCC

INPUT

GND

400 W

INPUT EQUIVALENT CIRCUIT

(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)

23 W

23 W

SOUT

GND

OUTPUT EQUIVALENT CIRCUIT (SOUT)

_

+

Amp

400 W

100 W

VCC

INPUT

GND

INPUT EQUIVALENT CIRCUIT (IREF)

XERR

GND

OUTPUT EQUIVALENT CIRCUIT (XERR)

23 W

INPUT

INPUT

GND

GND

INPUT EQUIVALENT CIRCUIT (VCC)

INPUT EQUIVALENT CIRCUIT (VPRG)

OUT

GND

OUTPUT EQUIVALENT CIRCUIT (OUT)

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

Resistor values are equivalent resistances, and they are not tested.

Figure 1. Input and Output Equivalent Circuits

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Testpoint

CL = 15 pF

SOUT

V(LED) = 4 V

RL = 51

CL = 15 pF

OUTn Testpoint

_+

VCC = 0 V ~ 7 V

V(LED) = 1 V

OUT0

OUTn

OUT15

Testpoint

RIREF = 640

IREF

IOLC, IOLC3, IOLC4, IOUT/IREF

twho, twIO, twh1, twl1, tsu0 tsu4, th4

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 2. Parameter Measurement Circuits

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TYPICAL CHARACTERISTICS

100

1 k

100 k

10 k

I − Output Current − mAO

0 20 60 100

Re

fere

nc

e R

es

isto

r, R

-(I

RE

F)

W

40 80 1200

1 k

3 k

4 k

2 k

T − Free-Air Temperature − CAo

0-20 20 100P

ow

er

Dis

sip

ati

on

Ra

te -

mA

-40 806040

TLC5940PWPPowerPAD Soldered

TLC5940PWPPowerPAD Unsoldered

TLC5940RHB

TLC5940NT

0

70

60

50

40

30

20

10

90

100

80

I-

Ou

tpu

t C

urr

en

t -

mA

O

V − Output Voltage − VO

0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 30.30

I = 60 mAmax

I = 30 mAmax

I = 5 mAmax

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

REFERENCE RESISTOR POWER DISSIPATION RATEvs vs

OUTPUT CURRENT FREE-AIR TEMPERATURE

Figure 3. Figure 4.

OUTPUT CURRENTvs

OUTPUT VOLTAGE

Figure 5.

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PRINCIPLES OF OPERATION

SERIAL INTERFACE

SCLK

SOUT

SIN

VPRG

Vcc

DC nMSB

GS MSB

X

1 1

XLAT

DC nLSB

96 192

GSLSB

193

DC n+1 MSB

DC n+1 MSB−1

1

DC nMSB

DC nLSB

DCMSB

GSMSB

SIDMSB

X

2

th3 tsu3 th3

tsu2th2 tsu2th2

DC Mode DataInput Cycle

GS Mode DataInput Cycle

DC Mode DataInput Cycle

X

ERROR INFORMATION OUTPUT

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

The TLC5940 includes a flexible serial interface, which can be connected to microcontrollers or digital signalprocessors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signalshifts the data from the SIN pin to the internal register. After all data is clocked in, a rising edge of XLAT latchesthe serial data to the internal registers. All data are clocked in with the MSB first. Multiple TLC5940 devices canbe cascaded by connecting the SOUT pin of one device with the SIN pin of the following device. The SOUT pincan also be connected to the controller to receive status information from TLC5940. The serial data format is96-bit or 192-bit wide, depending on programming mode of the device.

Figure 6. Serial Data Input Timing Chart

The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normaloperating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR ispulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turnedon, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together andpulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error(see Figure 14).

To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.

Table 1. XERR Truth Table

ERROR CONDITION ERROR INFORMATION SIGNALS

TEMPERATURE OUTn VOLTAGE TEF LOD BLANK XERR

TJ < T(TEF) Don't Care L X H H

TJ > T(TEF) Don't Care H X L

OUTn > V(LED) L L HTJ < T(TEF)

OUTn < V(LED) L H LL

OUTn > V(LED) H L LTJ > T(TEF)

OUTn < V(LED) H H L

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TEF: THERMAL ERROR FLAG

LOD: LED OPEN DETECTION

DELAY BETWEEN OUTPUTS

OUTPUT ENABLE

SETTING MAXIMUM CHANNEL CURRENT

Imax

V(IREF)R(IREF)

31.5

(1)

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. Ifthe junction temperature exceeds the threshold temperature (160°C typical), the TEF circuit trips and pulls XERRto ground. TEF status can also be read out from the TLC5940 status register.

The TLC5940 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are metsimultaneously:1. BLANK is set to LOW2. When the voltage at OUTn is less than V(LED) of 0.3 V (typical) (Note: the voltage at each OUTn is sampled

1 µs after being turned on).

The LOD circuit also pulls XERR to GND when tripped. The LOD status of each channel can also be read outfrom the TLC5940 status information data (SID) in GS data input cycle.

The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant currentdriver block of the device (see the functional block diagram). The fixed-delay time is 20 ns (typical), OUT0 has nodelay, OUT1 has 20 ns delay, and OUT2 has 40 ns delay, etc. The maximum delay is 300 ns from OUT0 toOUT15. The delay works during switch on and switch off of each output channel. These delays prevent largeinrush currents which reduces the bypass capacitors when the outputs turn on.

All OUTn channels of TLC5940 can switched off with one signal. When BLANK is set to high, all OUTn aredisabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set tolow, all OUTn work under normal conditions.

Table 2. BLANK Signal Truth Table

BLANK OUT0 - OUT15

LOW Normal condition

HIGH Disabled

The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed betweenIREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of31.5. The maximum output current can be calculated by Equation 1:

where:V(IREF) = 1.24 VR(IREF) = User selected external resistor.

Figure 3 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREFterminal to GND, and IO is the constant output current of OUT0 to OUT15.

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POWER DISSIPATION CALCULATION

P = V x I +D CC CC

V x IOUT MAX

xDCn

63x d

PWMx N(( )) (2)

OPERATING MODES

SETTING DOT CORRECTION

IOUTn Imax DCn63 (3)

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

The device power dissipation needs to be below the power dissipation rate of the device package to ensurecorrect operation. Equation 2 calculates the power dissipation of device:

where:VCC: device supply voltageICC: device supply currentVOUT: TLC5940 OUTn voltage when driving LED currentIMAX: LED current adjusted by R(IREF) ResistorDCn: maximum dot correction value for OUTnN: number of OUTn driving LED at the same timedPWM: duty cycle defined by BLANK pin or GS PWM value

The TLC5940 has different operating modes depending on the signals VPRG and DCPRG. Table 3 shows theavailable operating modes. The TLC5940 GS operating mode (see Figure 11) and shift register values are notdefined after power up. One solution to solve this is to set dot correction data after TLC5940 power up andswitch back to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummydata and latch it while TLC5940 is in GS PWM mode.

Table 3. TLC5940 Operating Modes Truth Table

SIGNALINPUT SHIFT REGISTER MODE DC VALUE

DCPRG VCPRG

L EEPROMGND 192 bit Grayscale PWM Mode

H DC Register

L EEPROMVCC 96 bit Dot Correction Data Input Mode

H DC Register

L EEPROMV(PRG) X EEPROM Programming Mode

H Write dc register value to EEPROM

The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected tothe output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. Thechannel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Equation 3determines the output current for each output n:

where:Imax = the maximum programmable output current for each output.DCn = the programmed dot correction value for output n (DCn = 0 to 63).n = 0 to 15

Dot correction data are entered for all channels at the same time. The complete dot correction data formatconsists of 16 x 6-bit words, which forms a 96-bit wide serial data packet. The channel data is put one afteranother. All data is clocked in with MSB first. Figure 7 shows the DC data format.

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DC 15.5

95

DC 14.5

79

DC 0.5

5

DC 0.0

0

DC 15.0

90

DC 1.0

6

LSB MSB

DC OUT0 DC OUT15DC OUT2 − DC OUT14

DC n

MSB

DC nMSB−1

DC nMSB−2

DC nLSB+1

DC nLSB

DC nMSB

DC n+1MSB

DC n+1MSB−1

DC nMSB−1

DC nMSB−2

DC n−1LSB

DC n−1LSB+1

DC n−1MSB

DC n−1MSB−1

DC n−1MSB−2

1 2 3 95 96 1 2SCLK

SOUT

SIN

MODE

XLAT

DC Mode Data

Input Cycle n

DC Mode Data

Input Cycle n+1

VCC

t

tsu1 th1

wh0

twl0

twh2

DCPRG

VPRG

V(PRG)

tsu5 tprog th5

DC EEPROM Write Timing

0 V or VCC

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

Figure 7. Dot Correction Data Packet Format

To input data into the dot correction register, VPRG must be set to VCC. The internal input shift register is thenset to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dotcorrection register. Figure 8 shows the dc data input timing chart.

Figure 8. Dot Correction Data Input Timing Chart

The TLC5940 has also an EEPROM to store dot correction data. To store data from the dot correction register toEEPROM, DCPRG is set to high after applying VPRG to VPRG pin. Figure 9 shows the EEPROM programmingtimings.

Figure 9. EEPROM Programming Timing Chart

14

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SETTING GRAYSCALE

Brightness in % GSn4095

100(4)

GS 15.11

191

GS 14.11

178

GS 0.11

11

GS 0.0

0

GS15.0

180

GS 0.0

12LSB MSB

GS OUT0 GS OUT15GS OUT2 − GS OUT14

tsu2

SCLK

SOUT

SIN

MODE

GSMSB

1

Following GS Mode DataInput Cycle

XLAT

DCLSB

96

DC Mode DataInput Cycle

192 193

GS + 1MSB

1

DC nLSB

DCMSB

GSMSB

SIDMSB

SIDMSB−1

First GS Mode DataInput CycleAfter DC Data Input Cycle

192

SID n + 1

MSB

GS + 1LSB

th3

tsu3

th2

th3

XXSIDLSB

tpd0

GSLSB

twh2

th1tsu1

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12-bitper channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 4 determinesthe brightness level for each output n:

where:GSn = the programmed grayscale value for output n (GSn = 0 to 4095)n = 0 to 15Grayscale data for all OUTn

The input shift register enters grayscale data into grayscale register for all channels simultaneously. Thecomplete grayscale data format consists of 16 x 12 bit words, which forms a 192-bit wide data packet (seeFigure 10). The data packet must be clocked in with the MSB first.

Figure 10. Grayscale Data Packet Format

When VPRG is set to GND, TLC5940 enters the grayscale data input mode. The device switches the input shiftregister to 192-bit width. After all data is clocked in, a rising edge of XLAT signal latches the data into thegrayscale register (see Figure 11). The first GS data input cycle after dot correction requires an additional SCLKpulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register isreplaced with status information data (SID) after latching into grayscale register.

Figure 11. Grayscale Data Input Timing Chart

15

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STATUS INFORMATION OUTPUT

LOD 15LOD 0TEFXXDC15.5DC 0.0XX

19117617516816772710

MSBLSB

LOD DataTEFDC ValuesReserved

GRAYSCALE PWM OPERATION

GSCLK

BLANK

GS PWMCycle n

1 2 3 1

GS PWMCycle n+1

OUT0

OUT1

OUT15

XERR

n x t d

tpd2

tpd2 + td

tpd2 + 14 x td

tpd3

tpd4

twh1twl1

twl1tpd4

4096

th4 twh3

tpd4+ n x td

tsu4

(Current)

(Current)

(Current)

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG =GND). After the XLAT signal latches the data into GS register the input shift register data will be replaced withstatus information data (SID) of the device (see Figure 11). LOD, TEF and dot correction EEPROM data(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at the SOUT pin. The statusinformation data packet is 192-bit wide. Bit 176 - bit 191 contains the LOD status of each channel. Bit 175contains the TEF status. If DCPRG is low, bit 72 - bit 167 contains the value of the dot correction EEPROM. IfDCPRG is high, bit 72 - bit 167 contains the data of the dot correction register. The remaining bits are reserved.The complete status information data packet is shown in Figure 12.

Figure 12. Status Information Data Packet Format

The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK increasesthe grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following rising edgeof GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of each outputOUTn with the grayscale counter value. All OUTn with grayscale values equal to counter values are switched off.A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscalePWM cycle (see Figure 13).

Figure 13. Grayscale PWM Cycle Timing Chart

16

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SERIAL DATA TRANSFER RATE

f(GSCLK) 4096 f(update)

f(SCLK) 193 f(update) n(5)

APPLICATION EXAMPLE

TLC5940

SIN SOUT

OUT0 OUT15

SCLK

GSCLK

XLAT

VPRG

BLANK

IREF

XERR

DCPRG

TLC5940

SIN SOUT

OUT0 OUT15

SCLK

GSCLK

XLAT

VPRG

BLANK

IREF

XERR

DCPRG

IC 0 IC n

7

SIN

SCLK

GSCLK

XLAT

BLANK

XERR

DCPRGController

SOUT

VPRG_D

VPRG_OE

W_EEPROM

100 k

50 k

50 k

50 k

50 k

50 k

50 k

VPRG

100 nF

V(LED)V(LED)V(LED)V(LED)VCC

100 nF

V(22V)V(22V)

VCC VCC

TLC5940

SLVS515A–DECEMBER 2004–REVISED AUGUST 2005

Figure 14 shows a cascading connection of n TLC5940 devices connected to a controller, building a basicmodule of an LED display system. The maximum number of cascading TLC5940 devices depends on theapplication system and is in the range of 40 devices. Equation 5 calculates the minimum frequency needed:

where:f(GSCLK): minimum frequency needed for GSCLKf(SCLK): minimum frequency needed for SCLK and SINf(update): update rate of whole cascading systemn: number cascaded of TLC5940 device

Figure 14. Cascading Devices

17

PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TLC5940NT ACTIVE PDIP NT 28 13 TBD Call TI Level-NA-NA-NA

TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHB ACTIVE QFN RHB 32 73 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 8-Aug-2005

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) PackageType

PackageDrawing

Pins PackageQty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TLC5940NT ACTIVE PDIP NT 28 13 Green (RoHS &no Sb/Br)

CU NIPDAU N / A for Pkg Type

TLC5940NTG4 ACTIVE PDIP NT 28 13 Green (RoHS &no Sb/Br)

CU NIPDAU N / A for Pkg Type

TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHB ACTIVE QFN RHB 32 73 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHBG4 ACTIVE QFN RHB 32 73 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 27-Feb-2006

Addendum-Page 1

MECHANICAL DATA

MPDI004 – OCTOBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NT (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

4040050/B 04/95

24 PINS SHOWN

1.425(36,20)

1.385

0.295(7,49)

(8,00)0.315

(35,18)

28PINS **

A MIN

A MAX

B MAX

B MIN

13

0.250 (6,35)0.280 (7,11)

12

0.200 (5,08) MAX

DIM 24

1.230(31,24)

(32,04)1.260

0.310(7,87)

(7,37)0.290

B

0.125 (3,18) MIN

Seating Plane

0.010 (0,25) NOM

A

0.070 (1,78) MAX

24

1

0.015 (0,38)0.021 (0,53)

0.020 (0,51) MIN

0.100 (2,54)

M0.010 (0,25)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.

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