Data Sheet No. PD60251 - Infineon Technologies

Features• Floating channel designed for bootstrap operation• Fully operational to +600 V• Tolerant to negative transient voltage, dV/dt

immune• Gate drive supply range from 10 V to 20 V• Undervoltage lockout for both channels• 3.3 V logic compatible• Separate logic supply range from 3.3 V to 20 V• Logic and power ground +/- 5 V offset• CMOS Schmitt-triggered inputs with pull-down• Cycle by cycle edge-triggered shutdown logic• Matched propagation delay for both channels• Outputs in phase with inputs

Product SummaryVOFFSET 600 V max.

IO+/- 200 mA / 440 mA

VOUT 10 V - 20 V

ton/off (typ.) 135 ns & 105 ns

Delay Matching 30 ns

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Data Sheet No. PD60251

IRS2112(-1,-2,S)PbF

DescriptionThe IRS2112 is a high voltage, high speed powerMOSFET and IGBT driver with independent high- andlow-side referenced output channels. Proprietary HVICand latch immune CMOS technologies enable rug-gedized monolithic construction. Logic inputs are com-patible with standard CMOS or LSTTL outputs, downto 3.3 V logic. The output drivers feature a high pulsecurrent buffer stage designed for minimum drivercross-conduction. Propagation delays are matchedto simplify use in high frequency applications. Thefloating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configurationwhich operates up to 600 V.

(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Pleaserefer to our Application Notes and DesignTips for proper circuit board layout.

Typical Connection

HIN

up to 600 V

TOLOAD

VDD VB

VS

HO

LO

COM

HIN

LIN

VSS

SD

VCCLIN

VDD

SD

VSS

VCC

Packages

16-Lead SOICIRS2112S

14-Lead PDIP(w/o lead 4)IRS2112-1

14-Lead PDIPIRS2112

16-Lead PDIP(w/o leads 4 & 5)

IRS2112-2

HIGH AND LOW SIDE DRIVER

• RoHS compliant

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IRS2112(-1,-2,S)PbF

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Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the DesignTip DT97-3 for more details).Note 2: When VDD < 5 V, the minimum VSS offset is limited to -VDD.

Symbol Definition Min. Max. UnitsVB

High-side floating supply voltage -0.3 625

VS High-side floating supply offset voltage VB - 25 VB + 0.3

VHO High-side floating output voltage VS - 0.3 VB + 0.3

VCC Low-side fixed supply voltage -0.3 25

VLO Low-side output voltage -0.3 VCC + 0.3

VDD Logic supply voltage -0.3 VSS + 25

VSS Logic supply offset voltage VCC - 25 VCC + 0.3

VIN Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3

dVs/dt Allowable offset supply voltage transient (Fig. 2) — 50 V/ns

PD Package power dissipation @ TA ≤ +25 °C (14 Lead DIP) — 1.6

(16 Lead SOIC) — 1.25

RTHJA Thermal resistance, junction to ambient(14 Lead DIP) — 75

(16 Lead SOIC) — 100

TJ Junction temperature — 150

TS Storage temperature -55 150

TL Lead temperature (soldering, 10 seconds) — 300

Absolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measuredunder board mounted and still air conditions. Additional information is shown in Figs. 28 through 35.

°C/W

W

V

°C

Symbol Definition Min. Max. UnitsVB

High-side floating supply absolute voltage VS + 10 VS + 20

VS High-side floating supply offset voltage Note 1 600

VHO High-side floating output voltage VS

VB

VCC Low-side fixed supply voltage 10 20

VLO Low-side output voltage 0 VCC

VDD Logic supply voltage VSS + 3 VSS + 20

VSS Logic supply offset voltage -5 (Note 2) 5

VIN Logic input voltage (HIN, LIN & SD) VSS VDD

TA Ambient temperature -40 125 °C

Recommended Operating ConditionsThe input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within therecommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential. Typicalratings at other bias conditions are shown in Figs. 36 and 37.

V

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IRS2112(-1,-2,S)PbF

Symbol Definition Min. Typ. Max. Units Test Conditionston

Turn-on propagation delay VS = 0 V

toff Turn-off propagation delay

tsd Shutdown propagation delay — 130 160

tr Turn-on rise time

tf Turn-off fall time

MT Delay matching, HS & LS Turn-on/off

ns

Dynamic Electrical CharacteristicsVBIAS (VCC, VBS, VDD) = 15 V, CL = 1000 pF, TA = 25 °C and VSS = COM unless otherwise specified. The dynamicelectrical characteristics are measured using the test circuit shown in Fig. 3.

Symbol Definition Min. Typ. Max. Units Test ConditionsVIH Logic “1” input voltage 9.5 — —

VIL Logic “0” input voltage — — 6.0

VOH High level output voltage, VBIAS - VO

— 0.05 0.2

VOL Low level output voltage, VO — 0.02 0.1

ILK Offset supply leakage current — — 50 VB = VS = 600 V

IQBS Quiescent VBS supply current — 25 100

IQCC Quiescent VCC supply current — 80 180

IQDD Quiescent VDD supply current — 2.0 30

IIN+ Logic “1” input bias current — 20 40 VIN = VDD

IIN- Logic “0” input bias current — — 1.0 VIN = 0 V

VBSUV+VBS supply undervoltage positive going

7.4 8.5 9.6threshold

VBSUV-VBS supply undervoltage negative going


VCCUV+VCC supply undervoltage positive going


VCCUV-VCC supply undervoltage negative going


IO+ Output high short circuit pulsed current 200 290 —VO = 0 V, VIN = VDD

PW ≤ 10 µs

IO- Output low short circuit pulsed current 420 600 —VO = 15 V, VIN = 0 V

PW ≤ 10 µs

Static Electrical CharacteristicsVBIAS (VCC, VBS, VDD) = 15 V, TA = 25 °C and VSS = COM unless otherwise specified. The VIN, VTH, and IIN parametersare referenced to VSS and are applicable to all three logic input leads: HIN, LIN, and SD. The VO and IO parameters arereferenced to COM and are applicable to the respective output leads: HO or LO.

µA

V

mA

V

VIN = 0 V or VDD

IO = 2 mA

VS = 600 V


— 135 180— 130 160

— 75 130

— 35 65

— — 30

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IRS2112(-1,-2,S)PbF

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Functional Block Diagram

SD

LIN

VDD

PULSEGEN

RS

Q

VSS

UVDETECT

DELAY

HVLEVELSHIFT

PULSEFILTER

UVDETECT

VDD/VCCLEVELSHIFT

VDD/VCCLEVELSHIFT

RS

Q RS

R Q

HIN

COM

HO

VS

VCC

LO

VB

Lead Definitions Symbol Description

VDD Logic supplyHIN Logic input for high-side gate driver output (HO), in phaseSD Logic input for shutdownLIN Logic input for low-side gate driver output (LO), in phaseVSS Logic groundVB

High-side floating supplyHO High-side gate drive outputVS

High-side floating supply returnVCC

Low-side supplyLO Low-side gate drive outputCOM Low-side return


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IRS2112(-1,-2,S)PbF

Lead Assignments

Part Number

14 Lead PDIP

IRS211216 Lead SOIC (Wide Body)

IRS2112S

14 Lead PDIP w/o lead 4

IRS2112-1 16 Lead PDIP w/o leads 4 & 5

IRS2112-2

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IRS2112(-1,-2,S)PbF

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Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient TestCircuit

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition

Figure 6. Delay Matching Waveform DefinitionsFigure 5. Shutdown Waveform Definitions

HINLIN

trton tftoff

HOLO

50% 50%

90% 90%

10% 10%

HINLIN

HO

50% 50%

10%

LO

90%

MT

HOLO

MT

SD

tsd

HOLO

50%

90%

HV = 10 V to 600 VVCC = 15 V

10µF

0.1µF

10 k F6

0.1µF

100µF

200µH 10 k

F6

1

213

12

11

10

7

5639

HO

OUTPUTMONITOR

10 k F6

IRF820

dVs

ct

HV = 10 V to 600 VVCC = 15 V

10µF

0.1µF 0.1

µF

10µF

10µF 15 V

1

213

12

11

10

7

5639

HO

LOCL

CL(0 V to 600 V)

VS-

+VB

HIN

LIN

SD

HINLIN

HOLO

SD


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IRS2112(-1,-2,S)PbF

Figure 7B. Turn-On Propagation Delay Timevs. VCC /VBS Supply Voltage

Figure 7C. Turn-On Propagation Delay Time vs. VDD Supply Voltage

Figure 8B. Turn-Off Propagation Delay Timevs. VCC /VBS Supply Voltage

Figure 8C. Turn-Off Propagation Delay Timevs. VDD Supply Voltage

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature(oC)

Tu rn

- On

Del

ay T

im e

( ns)

.

Typ.

M ax.

Figure 7A. Turn-On Propagation Delay Timevs. Temperature

0

50

100

150

200

250

10 12 14 16 18 20

V CC / V BS Supply Voltage (V )

Tu rn

- On

Del

ay T

im e

( ns )

.

Typ.

M ax

M ax.

Typ.

0

100

200

300

400

0 2 4 6 8 10 12 14 16 18 20

VDD Supply Voltage (V)

Turn

-On

Del

ay T

ime

(ns)

.

Typ .

Max.

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature(oC)

Turn

-Off

Tim

e (n

s)

Figure 8A. Turn-Off Propagation Delay Timevs. Temperature

M ax.

Typ.

0

50

100

150

200

250

10 12 14 16 18 20

VCC/V BS Supply Voltage (V )

Tu rn

- O ff

T im

e (n

s )

Typ.

M ax .

0

100

200

300

400

0 2 4 6 8 10 12 14 16 18 20

V DD Supply Voltage (V )

Tur n

-O ff

Del

ay T

im e

( ns )


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IRS2112(-1,-2,S)PbF

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Figure 10A. Turn-On Rise Time vs. Temperature

Figure 10B. Turn-On Rise Time vs. Voltage Figure 11A. Turn-Off Fall Time vs. Temperature

Figure 9B. Shutdown Delay Timevs. VCC/VBS Supply Voltage

Figure 9C. Shutdown Time vs. VDD Supply Voltage

Typ .

Max.

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature(oC)

Shut

dow

n D

elay

Tim

e (n

s)

Figure 9A. Shutdown Delay Timevs. Temperature

M ax.

Typ.

0

50

100

150

200

250

10 12 14 16 18 20

VC C/V BS Supply V oltage (V )

Sh u

td ow

n

D el

a y T

im

e ( n

s )

Typ.

M ax .

0

100

200

300

400

0 2 4 6 8 10 12 14 16 18 20

V DD Supply Voltage (V )

Shut

dow

n D

ela

y T

ime

(ns)

Typ.

M ax.

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature (oC)

Turn

-On

Ris

e T

ime

(ns)

.

Typ

M ax

0

50

100

150

200

250

10 12 14 16 18 20

V BIAS Supply Voltage (V )

Tur

n-O

n R

ise

Tim

e (n

s) .

Typ.

M ax.

0

25

50

75

100

125

-50 -25 0 25 50 75 100 125

Temperature (oC)

T ur n

- O ff

F al l

T im

e

( ns )


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IRS2112(-1,-2,S)PbF

Figure 11B. Turn-Off Fall Time vs. Supply Voltage Figure 12A. Logic “I” Input Thresholdvs. Temperature

0

3

6

9

12

15

-50 -25 0 25 50 75 100 125Logi

c "1

" Inp

ut T

hres

hold

(V)

Temperature (°C)

Min.

03

69

1215

2.5 5 7.5 10 12.5 15 17.5 20

Logi

c "

1 "

Inpu

t Tre

shol

d (V

)

VDD Logic Supply Voltage (V)

Figure 12B. Logic “I” Input Thresholdvs. Voltage

Min.

0

3

6

9

12

15

-5 0 -25 0 2 5 50 7 5 10 0 1 25

Logi

c "0

" Inp

ut T

hres

hold

(V)

Temperature (°C)

Figure 13A. Logic “0” Input Thresholdvs. Temperature

Max.

03

69

1215

2.5 5 7.5 10 12.5 15 17.5 20

Logi

c "

0 "

Inpu

t Tre

shol

d (V

)


Figure 13B. Logic “0” Input Thresholdvs. Voltage

Max.

Figure 14A. High Level Output Voltagevs. Temperature (Io = 2 mA)

Typ

M ax

0

25

50

75

100

125

10 12 14 16 18 20

V BIAS Supply Voltage (V )

Tur n

- O ff

Fal l

Tim

e

( ns)

M ax.

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100 125

Temperature (oC)

Hig

h Le

vel O

utpu

t Vol

tag

e (V

)


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IRS2112(-1,-2,S)PbF

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Figure 14B. High Level Output Voltagevs. Supply Voltage (Io = 2 mA)

Figure 15A. Low Level Output Voltagevs. Temperature (Io = 2 mA)

Figure 15B. Low Level Output Voltage vs.Supply Voltage (Io = 2 mA)

Figure 17A. VBS Supply Current vs. Temperature

M ax

0.0

0.2

0.4

0.6

0.8

1.0

10 12 14 16 18 20

V BAIS Supply V oltage (V )

Hig

h Le

vel O

utpu

t Vol

tage

(V)

Max

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100 125

Temperature (oC)

L o w

L e v e

l O

u t

p u

t V

o l t a

g e

( V )

M ax

0.0

0.2

0.4

0.6

0.8

1.0

10 12 14 16 18 20

V BAIS Supply Voltage (V)

Low

Lev

el O

utpu

t Vol

tage

(V)

Figure 16B. VBS Supply Current vs. Voltage

0

20

40

60

80

100

-50 -25 0 25 50 75 100 125Tem perature (°C)

Max.

Typ.

Max.

Typ.

0

50

100

150

200

-50 -25 0 25 50 75 100 125

Temperature ( oC)

Figure 16A. VBS Supply Current vs. Temperatur e

Typ.

Max.

0

50

100

150

200

10 12 14 16 18 20

VBS Supply Voltage (V)

VB

S S

uppl

y C

urre

nt (µ

A)

VB

S S

uppl

y C

urre

nt (µ

A)

VB

S S

uppl

y C

urre

nt (µ

A)

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IRS2112(-1,-2,S)PbF

Figure 20A. Logic “I” Input Current vs. Temperature

Figure 17B. VBS Supply Current vs. Voltage

0

20

40

60

80

100

10 12 14 16 18 20

VB

S S

uppl

y C

urre

nt (µ

A)

Max.

Typ.

VB S Floating Supply Voltage (V )

0

5 0

1 0 0

1 5 0

2 0 0

2 5 0

3 0 0

-5 0 -2 5 0 2 5 5 0 7 5 1 0 0 1 2 5

VC

C S

uppl

y C

urre

nt (µ

A)

Temperature (°C)

Max.

Typ.

Figure 18A. VCC Supply Current vs. Temperature

Figure 18B. VCC Supply Current vs. Voltage

0

50

100

150

200

250

300

10 12 14 16 18 20

Vcc

Sup

ply

Cur

rent

(µA)

Vcc Fixed Supply Voltage (V)

Max.

Typ.

0

2

4

6

8

10

12

-50 -25 0 25 50 75 100 125

VD

D S

uppl

y C

urre

nt (µ

A)

Temperature (°C)

Max.

Typ.

Figure 19A. VDD Supply Current vs. Temperature

Figure 19B. VDD Supply Current vs. VDD Voltage

0

2

4

6

8

10

12

0 2 4 6 8 10 12 14 16 18 20

V D

D S u

p p ly

C u r

r e n

t ( µ A

)


Max.

Typ.0

20

40

60

80

100

-50 -25 0 25 50 75 100 125

L o g i

c " 1

" I n

p u t B

i a s

C u r

r e n t

( µ A

)

Temperature (°C)

Max.

Typ.


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IRS2112(-1,-2,S)PbF

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Figure 20B. Logic “1” Input Current vs. VDD Voltage

0

20

40

60

80

100

0 2 4 6 8 10 12 14 16 18 20VDD Logic Supply Voltage (V)

Cur

rent

(uA

)

Max.

Typ.

Figure 22. VBS Undervoltage (+) vs. Temperature

Max.

Typ.

Min.

6

7

8

9

10

11

-50 -25 0 25 50 75 100 125

V B S

Und

ervo

ltage

Loc

kout

-(V

)

Temperature (°C)

Figure 23. VBS Undervoltage (-) vs. Temperature

Max.

Typ.

Min.

6

7

8

9

10

11

-50 -25 0 25 50 75 100 125VC

C U

nder

volta

ge L

ocko

ut +

(V)

Temperature

Max.

Typ.

Min.

Figure 24. VCC Undervoltage (-) vs. Temperature

6

7

8

9

10

11

-50 -25 0 25 50 75 100 125

VB

S U

nder

volta

ge L

ocko

ut +

(V)

Temperature (°C)

(oC)

Max

0

1

2

3

4

5

6

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logic

"0" I

nput

Bia

s Cu

rrent

(µA

)

Figure 21A. Logic "0" Input Bias Current vs. Temperature

Max

0

1

2

3

4

5

6

10 12 14 16 18 20

Supply Voltage (V)

Logi

c "0

" Inp

ut B

ias

Cur

rent

(µA

)

Figure 21B. Logic "0" Input Bias Current vs. Voltage

Logi

c "1

" Inp

ut B

ias

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IRS2112(-1,-2,S)PbF

6

7

8

9

10

11

-50 -25 0 25 50 75 100 125

VC

C U

nder

volta

ge L

ocko

ut -

(V)

Temperature (°C)

Figure 25. VCC Undervoltage (-) vs. Temperature

Max.

Typ.

Min.

Figure 26A. Output Source Current vs.Temperature

Figure 26B. Output Source Currentvs. Supply Voltage

Figure 27B. Output Sink Current vs. Supply Voltage

M in.

T yp.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (

o C)

O u

t pu

t S o u

r c e

C u

r r e n

t ( m

A )

M in.

Typ .

0

100

200

300

400

500

10 12 14 16 18 20

VBIA S

Supply Voltage (V)

O u

t p u

t So

u r c

e C

u r r

e n t (

m A

)

M in.

T yp.

0

150

300

450

600

750

-50 -25 0 25 50 75 100 125

Temperature (oC)

O u

t pu t

S in

k C

u r r e

n t

( m

A )

Figure 27A. Output Sink Currentvs. Temperature

M in.

Typ.

0

150

300

450

600

750

10 12 14 16 18 20

V BIA S Supply Voltage (V )

O u

t p u t

S i n

k C

u r r e

n t ( m

A

)


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IRS2112(-1,-2,S)PbF

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Figure 28. IRS2112 TJ vs. Frequency (IRFBC20)RGATE = 33 Ω , VCC = 15 V


0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V

140 V

10 V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V

140 V

10 V

Figure 33. IRS2112S TJ vs. Frequency (IRFBC30)RGATE = 22 Ω , VCC = 15 V


0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V

140 V

10 V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V 140 V

10 V

Figure 31. IRS2112 TJ vs. Frequency (IRFPE50)RGATE = 10 Ω , VCC = 15 V


0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V

140 V

10 V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V 140 V 10 V


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IRS2112(-1,-2,S)PbF


Figure 35. IRS2112S TJ vs. Frequency (IRFPE50)RGATE = 10 Ω , VCC = 15 V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)

Junc

tion T

empe

ratur

e (°C

)

320 V

140 V10 V

0

25

50

75

100

125

150

1E+2 1E+3 1E+4 1E+5 1E+6

Frequency (Hz)Ju

nctio

n Tem

pera

ture (

°C)

320 V 140 V 10 V

Figure 36. Maximum VS Negative Offset vs.VBS Supply Voltage

Figure 37. Maximum VSS Positive Offset vs.VCC Supply Voltage

-15.0

-12.0

-9.0

-6.0

-3.0

0.0

10 12 14 16 18 20

VBS Floating Supply Voltage (V)

VS

Offs

et S

uppl

y V

olta

ge (V

)

Typ.

0.0

4.0

8.0

12.0

16.0

20.0

10 12 14 16 18 20

VCC Fixed Supply Voltage (V)

V SS

Logic

Sup

ply O

ffset

Volt

age (

V)

Typ.


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01-601001-3002 03 (MS-001AC)14-Lead PDIP

Case outline

14-Lead PDIP w/o Lead 4 01-601001-3008 02 (MS-001AC)


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IRS2112(-1,-2,S)PbF

16-Lead SOIC (wide body) 01 601501-3014 03 (MS-013AA)

16 Lead PDIP w/o Leads 4 & 5 01-601501-3010 02


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C A R R I E R T A P E D IM E NS I O N FO R 1 6 S O IC W

C o d e M in M ax M in M axA 11 .9 0 1 2. 10 0. 46 8 0 .4 76B 3 .9 0 4.1 0 0. 15 3 0 .1 61C 15 .7 0 1 6. 30 0. 61 8 0 .6 41D 7 .4 0 7.6 0 0. 29 1 0 .2 99E 10 .8 0 1 1. 00 0. 42 5 0 .4 33F 10 .6 0 1 0. 80 0. 41 7 0 .4 25G 1 .5 0 n/ a 0. 05 9 n/ aH 1 .5 0 1.6 0 0. 05 9 0 .0 62

M etr ic Im p eria l

R E E L D IM E NS I O N S FO R 1 6 SO IC W

C o d e M in M ax M in M axA 32 9. 60 3 30 .2 5 1 2 .9 76 13 .0 0 1B 20 .9 5 2 1. 45 0. 82 4 0 .8 44C 12 .8 0 1 3. 20 0. 50 3 0 .5 19D 1 .9 5 2.4 5 0. 76 7 0 .0 96E 98 .0 0 1 02 .0 0 3. 85 8 4 .0 15F n /a 2 2. 40 n /a 0 .8 81G 18 .5 0 2 1. 10 0. 72 8 0 .8 30H 16 .4 0 1 8. 40 0. 64 5 0 .7 24

M etr ic Im p eria l

E

F

A

C

D

G

AB H

N OTE : CONTROLLING D IMENSION IN MM

LOADED TAPE FEED DIRECTION

A

H

F

E

G

D

BC

Tape & Reel16-Lead SOIC


http://www.irf.com


www.irf.com 19

IRS2112(-1,-2,S)PbF

LEADFREE PART MARKING INFORMATION

ORDER INFORMATION14-Lead PDIP IRS2112PbF

14-Lead PDIP IRS2112-1PbF16-Lead PDIP IRS2112-2PbF16-Lead SOIC IRS2112SPbF

16-Lead SOIC Tape & Reel IRS2112STRPbF

Lead Free ReleasedNon-Lead FreeReleased

Part number

Date code

IRSxxxx

YWW?

?XXXXPin 1Identifier

IR logo

Lot Code(Prod mode - 4 digit SPN code)

Assembly site codePer SCOP 200-002

P

? MARKING CODE

The SOIC-16 is MSL3 qualified.This product has been designed and qualified for the industrial level.

Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

Data and specifications subject to change without notice. 11/27/2006


http://www.irf.com


Data Sheet No. PD60251 - Infineon Technologies

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Transcript of Data Sheet No. PD60251 - Infineon Technologies