DARPA Advanced Computer Architecture Laboratory Simulation, Synthesis and Testing of Quantum...

Advanced Computer Architecture LaboratoryDARPADARPA

Simulation, Synthesis and Testing of Quantum Circuits

John P. Hayes and Igor L. Markov

Advanced Computer Architecture LaboratoryEECS Department

University of Michigan, Ann Arbor, MI 48109

QuIST PI Meeting, Los Angeles, June 2003


University of MichiganQuIST Project Overview

Quantum domain

Classical domain

Synthesis,simulation and test algorithms

AutomationScalability

ParallelismMicroscale

Practical logic

circuits


Project Personnel• Faculty

– John P. Hayes (EECS)– Igor L. Markov (EECS)– Stephen S. Bullock (Math)

• Postdoc– Ketan Patel

• Graduate Students– George Viamontes – Parmoon Seddighrad– Smita Krishnamurthy

• Undergraduate Students– Vivek Shende

• Administrative Assistant– Denise Duprie


Recent Results

• Simulation– New features added to our QuIDDPro simulator

– Major improvements in simulating Grover’s algorithm

• Testing– Basic results on testing reversible circuits

using standard fault models

• Synthesis– Bounds for gate counts in two-qubit circuits

– New methods for synthesizing reversible circuits


Quantum Circuit Simulation Using QuQuantum Circuit Simulation Using QuIDDsIDDs

• Motivation– Need for a better way to simulate quantum circuits

• Quantum Information Decision Diagram (QuIDD)– New data representation based on the concept of Binary Decision

Diagram (BDD) widely used in computer-aided circuit design – Captures some exponentially-sized matrices and vectors in a form that

grows polynomially with the number of qubits– Multiplies matrices and vectors in compressed form

• QuIDDPro Simulator– Our QuIDD-based simulator implemented in C++– Experiments with Grover’s algorithm demonstrate fast execution and

low memory utilization


QuIDD Data RepresentationQuIDD Data Representation

i02/1

i02/1

2/12/12/12/1

2/12/12/12/1

2/12/12/12/1

2/12/12/12/100

01

10

11

1001 1100

1

f

0R

0C

1R

1C

1R

1C

01

0


QuIDDPro Simulation of Grover’s AlgorithmQuIDDPro Simulation of Grover’s Algorithm

H

H

H

Oracle

H

H

Conditional Phase Shift

H

H

H

|0>

|0>

|1>

.

.

.

.

.

.

.

.

.

- Search for items in an unstructured database of N items - Contains n = log N qubits and has runtime NO


QuIDDPQuIDDProro Simulation Simulation of Grover’s Algorithmof Grover’s Algorithm

Same results for any oracle that distinguishes a unique element


Same results for any oracle that distinguishes a unique element

O(p(n)(√2)n)

O(n)

QuIDDPQuIDDProro Simulation Simulation of Grover’s Algorithmof Grover’s Algorithm


Fault Testing for Reversible CircuitsFault Testing for Reversible Circuits

• Outline

– Motivation

– Background

– General properties

– ILP formulation

– Future work


MotivationMotivation

Classical Reversible Circuits

• “Energy-free” computation (non-quantum)

• Reversible applications: cryptography, DSP, etc.

• Important subclass of quantum circuits

Efficient testing will be important as in VLSI


Reversible ComputationReversible Computation

Computes bijective function

• No. of inputs = No. of outputs

• Each output comes from a unique input

Example:

Input OutputReversible XOR Gate

00 00

01 01

10 11

11 10


Reversible Gates & CircuitsReversible Gates & Circuits

NOT Gate C-NOT Gate

Toffoli Gate


Fault ModelsFault Models

Stuck-at Model: Wire stuck at 0 (or 1)

Cell Fault Model: Single component fails


Test Generation GoalTest Generation Goal

Generate (minimal) input set to detect any fault in F

Example:


Test Generation GoalTest Generation Goal

Generate (minimal) input set to detect any fault in F

Example:

Use 0100 to detect fault

Correct Output: 0010

Faulty Output: 1110

Test set is complete if it detects all faults

0 0 0 0 0/1

1 1 1/0 0/1 0/1

0 0 1 1 1

0 1 1 1 0


Properties of Reversible CircuitsProperties of Reversible Circuits

• Complete Controllability – Wires at any level can be set to any state

• Complete Observability – Any change in intermediate state change output

• Single Stuck-at Fault Model:– Test set complete iff every fault site set to 0/1

• Multiple Stuck-at Fault Model:– Same test set complete for multiple faults too!


Efficient Test Sets ExistEfficient Test Sets Exist

Theorem:

Example:

...but proof is non-constructive

1faults of #log || 2 T

ors test vect23 gates 33million one

inputs 64 circuit w/


ILP FormulationILP Formulation

Formulate minimal test set problem as ILP

•Decision variables for input vectors1 = in test set 0 = not in test set

•Constraints guarantee completeness

•Objective: minimize sum of decision

vars

Gives minimal test set


Minimize Subject to the constraints

Impractical for medium/large circuits

1210 nttt

i

iij tTf 1)(

djtTfi

iij 0 ,1)(

120 ,1,0 where ni it

ILP Formulation (contd.)ILP Formulation (contd.)


Circuit DecompositionCircuit Decomposition

Combine ILP with circuit decomposition• Decompose circuit into small sub-circuits• Apply ILP iteratively• Dynamically combine previous test vectors• Test set

compaction

C0 C1 C2C0 C1 C2C0 C1 C2


Simulation ResultsSimulation Results


On-Going WorkOn-Going Work

• Fault models and ATPG for quantum circuits

• Improved lower bounds on test set size

• Fault diagnosis methods

• Design for testability

• On-line testing and error correction


Two-qubit Computationwith Minimum Resources

Outline– Prior work

• Synthesis by matrix factorizations

– Our contribution• Entanglers and disentanglers

• Recognizing tensor products

• Circuit decompositions

– Conclusions and ongoing work


Elementary Gates Q. Computation “basic” gates


Technology-Independent Synthesis

• Input: Unitary 4x4-matrix M– Generic quantum computation on 2 qubits

• Output: circuit in terms of elem. gates that implements M up to a phase

• Minimize: circuit cost– E.g., gate count or (gate costs)

• Solutions exist iff the gate library is universal


Phase can be ignored

Gate 1 Gate 2 Gate 3


Previous Work

• Proof of universality is constructive [Barenco et. al `95] in Phys. Rev. A– Can be interpreted as a synthesis algorithm

– However, no attempt to minimize #gates

• Can be viewed as matrix factorization– [Cybenko `01]

– M=QR with unitary Q & upper-triangular R (M unitary R diagonal)

– We count gates, and the answer is …61


Our Work (1)

• Two new synthesis procedures (2 qubits)– Based on a different matrix factorization

(related to SVD and KAK decompositions)

– Also reduce generic synthesis to diagonal synthesis

– Small circuits for diagonal computations

– Smaller overall circuits than QR (Cybenko)

• Constructive worst-case bounds– Any circuit in ? gates or less

– Any circuit with 15 non-constant gates

23


Our Work (2)

• Lower bounds– There exist two-qubit computations (most of them)

that require at least 17 elementary gates• At least 15 non-const gates

• At least 2 CNOTs

– Bounds are not constructive and not tight,except for “15 input-dependent gates”

• We never use “temporary storage” qubitsbut that could lead to smaller gate counts


The Entangler and Disentangler

• “Computational basis”– |00>,|01>,|10> and |11>

• The “entangler” computation maps|00> to (|00>+|11>)/2, etc.

• The “disentangler”is E-1=E*

• Key lemma– If U=AB, then EUE* has only real entries

– An efficient way to recognize tensor products


Circuits For E and E*

• A specific circuit for the entangler E

• S=diag(1,i) counts as one elementary gate

• The Hadamard gate H counts as two

• E* is implemented by reversing the diagram– Change S to S-1=diag(1,-i)

7 elem. gates


• The “canonical decomposition” for 2-qubit computations: U K1,K2 and such that U=K1K2

– EE* is diagonal (5 gates)

– K1,K2 have only real entries

• The terms K1, K2 and can be found explicitly– Numerical analysis: polar and spectral decompositions

• Reduce K1 and K2 to tensor products using entanglers

—EUE*=E(AB)E*EE*E(CD)E*

—A,B,C and D are one-qubit computations: 3 gates each

• Note that E and E* are the same for any input

Our (Key) Synthesis Procedure

Rz Rz

Rz


Details (1)

• After the initial “divide-and-conquer”many gate cancellations can be made

• This brings down max #gates to 28– Only 15 of them depend on input,

which matches an a priori lower bound

• Further reductions based on the analysisof E(AB)E* and E(CD)E* – Max no. of gates reduced to …– However, 19 gates depend on the input

23


Details (2)

The structure of our generic 23-gate circuit

• For additional details, see– Our paper in Physical Review A (to appear in July)

– http://xxx.lanl.gov/abs/quant-ph/0211002


Validation of Our Synthesis Algorithm

• Implementation in C++– Produces 23 gates for randomly-generated 4x4-unitaries

– We plan to put it up on the Web as an ASP

• Can capture structure– Several examples in quant-ph/0211002

– Optimal results for any AB circuit(QR decomposition typically 61 gates)

– For 2-qubit Fourier transform: a circuit with minimal # of CNOT gates


• First generic synthesis algorithm to capture circuit structure, e.g., AB

• On-going work– Lower and upper bounds of ? gates (almost done)

– Solved the synthesis of n-qubit diagonal computations (produce asymptotically optimal circuits)

Summary

18


Project Summary & Future Plans• Testing of reversible circuits

– Analyzed basic testing properties of classical reversible circuits

– Showed that relatively few test-vectors required

– We are studying fault models and ATPG for quantum circuits

• Structure of quantum circuits and automatic synthesis– Developped algorithms for technology-indep. synthesis without ancillae

– Proposed circuit constructions for arbitrary 2-qubit computations

– Established lower bounds for gate counts

– Working on optimal constructions and extensions to multiple gate libraries

• More efficient simulation of Grover’s algorithm– 40 qubits in 25 hours and less than 1MB of RAM

– Intriguing questions about the power of Grower’s algorithm


Work in Progress:On The Power of Grover’s Algorithm

• Database search with a black-box predicate p(x)=1– Classical evaluation of p(x) on one input (queries)

– Quantum (parallel) evaluation of p(x) facilitates an implementation with fewer queries

• We also assume that p(x) is given as a BDD/QuIDD– BDDs are used to represent functions in practical CAD

– However, a BDD is not really a black-box

– BDD operations evaluate p(x) on multiple inputs at once(no quantum computation is involved)

• Grover on QuIDDs: same query complexity as in the quantum case– In practice this simulation is very fast and needs little memory

Non-trivial assumption


Publications(1) V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes: “Synthesis of Optimal Reversible

Logic Circuits,” 11th Intl. Workshop on Logic & Synthesis (IWLS’02), June 2002.

(2) G. F. Viamontes, M. Rajagopalan, I. L. Markov and J. P. Hayes: “High-Performance Simulation of Quantum Computation Using QuIDDs,” 6th Intl.. Conf. on Quantum Communication (QCMC’02), Cambridge, MA, July 2002. Published in Quantum Information and Computation, Rinton Press, pp.311-314, 2003.

(3) V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes: “Reversible Logic Circuit Synthesis,” Proc. 20th Intl. Conf. on Computer-Aided Design (ICCAD’02), San Jose, CA, pp. 353-360, Nov. 2002, quant-ph/0207001.

(4) G. F. Viamontes, M. Rajagopalan, I. L. Markov and J. P. Hayes: “Gate-Level Simulation of Quantum Circuits,” Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC `03), Kitakyushu, Japan, pp.295-301, Jan. 2003, quant-ph/0208003.

(5) K. N. Patel, J. P. Hayes and I. L. Markov: “Fault Testing for Reversible Circuits.” Proc. 2003 VLSI Test Symposium (VTS `03), Napa, CA, pp.410-416, April 2003.

(6) V. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes: “Synthesis of Reversible Logic Circuits.” IEEE Transactions on Computer-Aided Design. Vol. 22, pp.710-722, June 2003.

(7) S. S. Bullock and I. L. Markov: “An Arbitrary Two-Qubit Computa-tion in 23 Elementary Gates,” Proc. Design Automation Conf. (DAC `03), to appear in PRA, quant-ph/0211002.

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