Daniel Mange- Teaching Firmware as a Bridge Between Hardware and Software

8/3/2019 Daniel Mange- Teaching Firmware as a Bridge Between Hardware and Software

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vices in organization development and for teaching programs in colleges ofengineering, medicine, science, and graduate studies. He w as on sabbaticalleave at the University of Illinois Urbana, IL, and the Illinois Institute ofTechnology Chicago, IL, during the academic year of 1 981-198 2. In August1985, he joined Wilkes University, Wilkes-Barre, PA, where he is currentlya Professor of Electrical Engineering. He is presently studying mobilitylimiting mechanisms in high-speed devices, including quantum and high-field effects. He has visited several international institutions and enjoys theprivilege of knowing the cultures and educational methods being practicedaround the globe. He participated in the Sakaki Quantum Wave Projectinvolving the design of Quantum Well Wire FETs at the University ofTokyo under the Exploratory Research for Advanced Technology (ERATO)Program. Presently, he is a Visiting Professor at the National University ofSingapore.Dr. Arora is a member of several professional societies including APS,ASEE, Sigma-XI, IPA, AGS. He is listed in American Men and Women ofScience and Whos Who in Science and Engineering.

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Ganesh S. Samudra (M87) was born in India.He received the MSc. from Indian Institute ofTechnology, Bombay, India in 1976, and theM.S., M.S.E.E., and Ph.D. degrees from PurdueUniversity, Lafayette, IN.In 1985,he joined Texas Instruments, Inc., Dallas,TX, where he worked on development and supportof semiconductor process and device simulationtools. In 1987, he joined Texas Instruments,Bangalore, India, where he was section managerfor simulation. H e was elected Member of G r o wTechnical Staff, in 1988, for outstanding technical contributions in simulation.Since 1989, he has been with the Department of Electrical Engineering,National University of Singapore, Singapore, where he is presently a SeniorLecturer. He is currently working in Technology and Design CAD tools.Dr . Samudra i s Chairman of IEEE Circuits and System Chapter ofSingapore.

leach ing kirmware as a BridgeBetween Hardware and SoftwareDani e l M ange ,

Abstract-The Electrical Engineering Departm ent of the SwissFederal Institute of Technology in Lausanne, Switzerland, hasrecently introduced a new course for freshmen aimed to tietogether both sides of comp uter science (hardware, such as logicand digital systems, and software, such as classic proceduralPASCAL programming), to emphasize systematic and invariantmethods rather than describing rapidly changing technologiesand to give a faster and stronger introduction to the profession.This one-year course (with labs) is called an Introduction tofirmware theory, the term firmware being comprehended as theart and the technique of transforming hardware (logic systems)into software (prog rams) an d vice versa; the entire cou rse isbased on the central idea of equivalence between hardware andsoftware which is exhibited by means of one preferred repre-sentation, the binary decision tree. I n this paper, a very simpleexample is used to show the definition of a binary decision tree, itssimplification and its decomposition. Hardware implementationis illustrated by a demultiplexer network, while software imple-mentation is highlighted by th e use of two stru ctured languages:a high-level language called MICROPASCAL and a low-levellanguage called U, he latter being obtained by a compilationof the former. The conclusion gives a summary of the course,including lab oratory sessions, as it is taugh t a t present.I. INTRODUCTION

number of American institutions (Drexel University inA hiladelphia, Rose-Hulman Institute of Technology inTerre Haute, Indiana, and Texas A & M U niversity) are tryingexperiments for restructuring their curricula for freshmen andsophomores and are searching for a magic ingredient thatcould give engineering instructors the incentive to design,develop, and test innovative approaches to undergraduateeducation [l].

Manuscript received September 1992.The author is with the Logic Systems Laboratory, The Swiss FederalIEEE Log Number 9205770.Institute of Technology, CH 1015 Lausanne, Sw itzerland.

Member, IEEE

In the particular area of computer science, the ElectricalEngineering Department of the Swiss Federal Institute ofTechnology in Lausanne, Switzerland has faced the samechallenge and has decided to introduce in 1988 a new coursefor freshmen (first year) aimed to:give a faster and stronger introduction to the profession;tie together both sides of computer science: hardware(logic and digital systems) and software (classic proce-dural programming such as PASCAL); andemphasize systematic and (almost) invariant methodsrather than describing fast changing present technologies.

The solution arrived at consists of a one-year course(with laboratory experiments) dedicated to an Introductionto firmware theory, the term firmware being compre-hended as the ar t and the technique of t r ans f o r mi nghardware ( logic sys tems) in to sof tware (programs) andvice versa.The entire course is therefore based on the central ideaof equivalence between hardware and software; and thisequivalence, which at the mathematical level rests on theconcept of the algorithm, is exhibited by means of onepreferred representation, the binary decision tree. In thispaper, a very simple example (a decoder designed foran electronic watch) is used to show the definition ofa binary decision tree, its simplification (Section 11) andits decomposition (Section 111). Hardware implementationis illustrated by a demultiplexer network (Section IV),while software implementation is highlighted by the useof two structured languages: a high-level language calledMICROPASCAL and a low-level language called L4(Section V) . The conclusion gives a summary of the course,as it is taught at present at the Swiss Federal Institute ofTechnology.

0018-9359/93$03.00 0 1993 IEEE


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11. SIMPLIFEATION OF B I N A R Y E C I S IO N R E ESA . Example: A Watch Decoder

Any combinational logic system with 11 input binary vari-ables can be represented by various mod es of representation: atruth table with 2 rows, a Karnaugh map of 2 cells, a binarydecision tree with 2 branches.Consider, for example, the decoder which has to detect, in anelectronic watch, the number of days in a month. The monthsare represented by BCD (binary coded decimal) numbers inthe range 1-12 (from January to December) with the aid ofthe following logical variables:

M A for the tens (0 o r 1);hf~.M~.M~.MOor the units (0000 . . . 1001) .

These are to be the inputs to a combinational system whosediscrete output Z is 30 , 31 or F for February. The fivevariables MA . . A40 define 2 = 32 possible input states,12 of which are defined and 20 being undefined or dont careconditions (a) fo r 2. he output function 2 an thereforebe represented by a 32-branch binary decision tree.We will show how it is possible to use the Karnaugh map inorder to simplify the original (or canonical) 32-branch binarydecision tree. This process is called the simplification of th ebinary decision tree, i.e., the search of a tree with a minimalnumber of branches for representing a given function Z .B. Simplifying a Binary Decision Tree

We propose the following graphical method:In the Karnaugh map, an output state (2 3 0 , 3 1 orF ) s entered into each of the 12 cells corresponding toth e 12 input states M4. M3. Ad*.MI. MO given by thespecification.Dont care conditions (2 @) are entered into the 20remaining cells.The map is divided into blocks (i.e., rectangular or squaregroups of 23 cells with j = 0 . 1 . . 5 ) , and the set ofblocks must satisfy the conditions of coverage, sepa-rability, an d compatibility. Coverage means that everycell must be included in a block. Separability meansthat all the cells in the same block must have the sameoutput state, and that each cell may be included in onlyone block. Compatibility means that a branch variablecan cut the Karnaugh map into two half-maps withoutcutting any block in the map, and each half-map canbe likewise divided again, and so on until one obtainsthe set of isolated blocks. For example, in Fig. 1, thebranch variables capable of starting this subdividing, i.e.,the first-branch variables, are M A or M O .The set containing the fewest blocks is the minimal set.Each minimal set produces a minimal binary decisiontree, and each block of this set (a product of the branchvariables) produces one branch of the tree.

In the example of Fig. 1, one can verify the following:The m ap of 32 cells is completely covered by 7 blocks(coverage).The cells in each of the 7 blocks have the same outputstate (30, 31 or F ) , and each of the 32 cells is covered

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2Fig. I . Karnaugh map for the watch decoder: partition in 7 blocks

Fig. 2. Binary decision tree after aimplification (7 branches).

by one block only (separability); a dont care condition(a) can be given the value 30, 31 or F .The first-branch variable is MA since M4 divides themap into two half-maps of 16 cells each without cuttingany block. This process can be continued with variableM O (for M i = 1) an d M 3 (for M A = 0), an d so on(compatibility).I t is impossible to find a set with fewer than 7 blocks:therefore, the set is minimal.

Fig. 2 show a minimal binary decision tree consisting of7 branches and realizing the given function 2: ach block inthe Karnaugh map is a branch of the tree. A binary decisiontree has always as many output elements, represented byrectangles, as branches (7 in Fig. 2) and as many test elements,represented by diamonds, as branches minus 1 (6 in Fig. 2).Systematic methods, similar to the classical McCluskeysminimization process, must be used to prove that this treeis truly minimal. Unfortunately, these methods are tediousto handle by hand calculation and therefore need automaticcomputation [ 2 ] .

111. DECOMPOSITIONF BINARY ECISIONTREESA. Main Tree and Subtrees

Looking at the tree of Fig. 2, we can se e two iden ticalsubtrees sp ; the binary decision tree of Fig. 2 is thereforeequivalent to the two partial trees of Fig. 3. We have thuseffected a decomposition of the original tree into a maintree (2 = p p ) an d a subtree ( s p ) ; he decomposition hasnecessitated a third type of graphical element, representedby sp in a rectangle with four vertical bars (Fig. 3): this isthe call of subtree element. The decomposition of a givenbinary decision tree into several subtrees is equivalent to th ecalculation of a binary decision diagram, which can be viewedas a tree with reconvergent branches (Fig. 4) .


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z = P P

Fig. 3. Decomposition of the original tree in a main tree p p and a subtree sp .z = P PI

Fig. 4. Transformation of the original tree in a binary decision diagram.

If a decision tree can be shown to have at least one pair ofidentical subtrees it can either be decomposed into two or moretrees or transformed into a binary decision diagram. In eithercase the result is an equivalent representation that involvesfewer elements and is therefore easier to implement.B . Deriving a Minimal Decomposition

The derivation of a minimal binary decision diagram, i.e.,a minimal decomposition of a binary decision tree, is not atall trivial; a systematic method, one that uses the co n s p t ofP-functions, at present seems the only practical algorithm [3],[4]. ortunately, it is also possible to derive such a diagramdirectly from a Karnaugh map. Looking at Fig. 5, one canobserve the following:

9 The two Karnaugh maps of Fig. 5 describe the two partialtrees p p an d sp of Fig. 3.The sp Karnaugh map is simply a part of the originalKarnaugh map of Fig. 1; it is identical to one half of theoriginal map (Ad4 = 1) and equivalent to another quarterThe determination of a common subtree sp therefore revertsto the task of identifying similar blocks of blocks in the originalKarnaugh map, i.e., to identifying a rectangle or square grou p

of 2J cells having different states but the same state pattern.The two identical blocks of blocks sp , located in Fig. 1, havebeen encircled with doted lines in the map p p of Fig. 5.Although this method is highly intuitive, it nevertheless offersvery efficient means of fast hand calculation.

(Ad4 = 0 , M3 = 1).

IV . HARDWAREMPLEMENTATIONA . Demultiplexer Network

The main advantage of the graphical representation witha binary decision diagram, i.e., a single tree with reconver-

n1[T]: 31._.................~

z= P P SpFig. 5. Karnaugh map showing the identical blocks of blocks sp.M 4 4 MUX ,

@ R MO+)I I

30 31 FFig. 6. Hardware implementation as a demultiplexer network

gent branches, is its simplicity: minimal number of elements(five tests and three output elements in our example: Fig. 4)an d no need of the third type of element, the call of a sub-tree. The binary decision diagram can therefore lead directlyto a hardware implementation (Fig. 6) with the followingprocedure:

each test element (each diamond in Fig. 4) is imple-mented as a demultiplexer (DMUX) with a single controlvariable, which is the test variable;each information link between two elements of the dia-gram is implemented as a physical connection (a wire);each convergence of k arrows (representing a commonsubtree in the diagram) is implemented as an OR gatewith k inputs;the input terminal in the logic diagram is given thevalue 1.The binary outputs labeled 30, 31 and F in Fig. 6constitute

the realization of the discrete function Z of the decoder in a1 out-of-3 code.If the binary decision diagram is minimal for a givenfunction 2 i.e., has a minimal number of test elements),then the corresponding demultiplexer network will be min-imal too, i.e., will have a minimal number of demultiplex-ers.


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B . Other Hardware ApplicationsAny sequential system can be described by a state table, inwhich the next state Y+ and the output state 2 re functionsof the input state X and the present state Y . mplementing asequential system is therefore reduced to finding a minimalbinary tree (or diagram) of the discrete function Y+ ,2which depends on the X and Y variables. The main problem

remains the simplification and the possible decompositionof the canonical tree. An example of a reversible counteris detailed in [5] and [20], while an exhaustive study offinite state machines can be found in [20]. A g eneral methodfor synthesizing hardware systems by means of binary de-cision trees can be summ arized as follows: star ting with aKarnaugh map (for combinational systems) or with a statetable (sequential systems), simplification and/or decomposi-tion produces a tree with or without reconvergent branches,representing a discrete function 2 quivalent to n booleanfunctions 2,. . . . 21 . One single demultiplexer treewith OR gates (and, in the case of a sequential circuit, with flip-flops) implements the original specification; it can be shownthat a network with n multiplexer trees (with flip-flops in thecase of a sequential circuit) can constitute an equivalent sys-tem [20].In conclusion, the method of binary decision trees anddiagram s can easily and regularly be used in all hardwaredesigns. The only limitation for hand calculation, due to theuse of Karnaugh maps, is the number of input variables.

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MICROPASCAL A D R U

V. SOFTWAREMPLEMENTATIONA. Structured Programm ing

The m ain advantage of a decomposition of a tree into a maintree and several su btrees is that this preserves the structure oftrees which, in contrast to decision diagrams with convergentbranches, meet the requirements of structured programming.Let us remember the definition of a structured program:the output instruction do s , characterized by an ac-tion s and having one input terminal connected tothe preceding instruction and one output terminal con-nected to the next instruction, is a structured program.

If P and Q are structured programs thenthe sequence of P an d Q (do PQ) is a structuredprogram;the iteration of P (while a do P) s a structured program;the test giving P or Q (if a then P else Q) is a structuredprogram; andall existing structured programs are those which can beobtained by applying definitions a) through d ) a finitenumber of times.

program P Pif M4else

call s pif M3else call s p

ifMOelse do 31if M2

else&dif

do 30do F

endifendifendifprocedure s pif MOelse

endifend procedureend program

do 30do 31

00010203040506070809OAOBK

P R O G R A M p pIF M4 ELSE 03CALL 10G OTOODIF M3 ELSE 06CALL 10GOT0 OD

IF MO ELSE 09GO TOOD

D O 31IF M2ELSEOCGO OODENDIF

D O 30D O F

ENDIFENDIFENDIFPROCEDURE sp

10 IFMO ELSE 1311 Do301213 DO 114 RE T

G OTO14ENDIFEND PROGRAM

Fig. 7. Software implementation in MICROPASCAL and L4 structuredlanguages (ADR: present address).

B. Structuring and Interpreting Binary Decision TreesBinafy decision trees, unlike decision diagrams, canbe directly implemented in a structured program (Fig. 7).

This program, first expressed in a high-level languagecalled MICROPASCAL, a minimal subset of PASCAL [ 5 ] ,is derived from the decomposition of trees (Fig. 3) asfollows:the main tree is implemented as the main program p p ,beginning with the keyword program . nd terminatingwith end program;the subtree sp is realized as a single procedure sp , startingwith the keyword procedure.. . nd terminating with endprocedure;each test element of the trees (a diamond in Fig. 3) isimplemented as an if. . .else.. .endif structure;each output element (a rectangle) is implemented as ad o . . . nstruction, while each call of subtree element (arectangle with four vertical bars) is implemented as ac a l l . .. nstruction.

A straightforward compilation, by hand or by computer,transforms the MICR OPA SCAL program in an equivalent low-level language L4 program (Fig. 7). This language is alsostructured, and is implemented by a set of four instructionsonly:

a) DO s GO TO A D R + 1b) IF a THEN A D R + l ELSE ADROwith the special case when a = 0: GO TO ADROc) CALL ADSP RET TO A D R + 1d) RET

(action);(test),(unconditional jump);(procedure call);(return from procedure)


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where A D R is the actual address, ADRO an d ADSP nextaddresses. The keywords PROGRAM.. . ENDIF, PRO-CE DURE . .. an d END PROGRAM are merely comments,without any address.If the decomposition of binary trees is minimal (i.e., has aminimal number of test elements), then the high-level languageMICROPASCAL program and the low-level language L4program will be minimal too, i.e., will have a minimal num-ber of test structures (if .. else. .endif or I F . . .E L SE. . .GOTO.. ENDIF).The L4 program of Fig. 7 can be directly interpreted by asimple sequential machine, a binary decision machine, whichhas been described elsewhere [5]; this machine is built fromclassical bit-slice integrated circuits (controller or sequencer)or directly obtained as a single circuit with an UV-erasableand reprogrammable memory (for example: CMOS field-programmable controller from Advanced Micro Devices).

VI. CONCLUSIONA. Advantages and Drawbacks

The main advantage of the proposed approach is itsuniversality: minimizing binary decision trees or diagramsproduces minimal hardware circuits (i.e., multiplexer or de-multiplexer networks with a minimal number of components)or minimal program (i.e., programs with a minim al numberof IF ... HEN.. .ELSE ... instructions); this approach is apowerful tool for designing both hardware and software.On the hardware side, the increasing use of field pro-grammable gate arrays (FPGA) based upon one- or two-variable multiplexer (e.g., the ACTEL family) makes ourapproach particularly attractive; the only drawback is thedelay: in the worst case (a branch of the tree without anysimplification), the signal must go through n circuits (multi-plexer or demultiplexer) for n input variables, instead of thetwo levels for classical AND-OR networks.

On the software side, the use of binary decision machinesbuilt from actual integrated circuits becomes more and morepopular for the design of real time and m edium scale programs(approx. 500 instructions). T he binary decision treeidiagram isa tool for obtaining shorter programs and for introducing a truemethodology in software design.B. Organization of the Course

The first part of the new course Introduction to firmwa retheory is quite standard: it is devoted to the classical switchingtheory and to the analysis and synthesis of logic systems, bothcombinational and sequential ( 11 sessions of four hours each,whose one is dedicated to the lecture, the three other beingdevoted to laboratory experiments).The second part, which is the subject of this paper, com-prises seven sessions of four hours each (one hour of lectureand three hours of laboratory) as follows:1) Memories:

Definition and functional analysis of ROM and RAM;RA M with 3-state circuits and hi-directional buses;

2) Binary Decision Trees:Definition, simplification, and decomposition of binarytrees using Karnaugh map;Hardware implementation: demultiplexer/multiplexer net-work;Software implementation: definition of language L1 con-sisting of two types of instructions {I F a THEN A D R lELSE ADRO} an d {DOS GO TO A D R t } ;Interpretation of language L1 by means of a hardwareinterpreter: a binary decision machine;Application: comparator of two 4-bit numbers.

.i3) Subprograms, Procedures, and Stack M achine:Definition of subprogram s, procedures, and nested proce-dures;Software implementation of procedures: language L2 withfour types of instructions {IF a THEN A D R l ELSEADRO, DO s GO TO A D R t , CALL ADSP RET TOADRT, RET};Interpretation of language L2 by a hardware interpreter: abinary decision machine with a stack;Procedure call with parameter passing;Applications: counter mod ulo-n , decomposition of coun-ters, iterative combinational system (an adder).

4 ) Incremental Programs and Controller:.Definition of incremental programs;Software implementation with a modified version oflanguage L2: L3 = {I F a THEN A D R t 1 ELSE ADRO,DO s GO TO A D R + l , CALL ADSP GO TO A D R + 1 ,

Interpretation of L3 by a stack machine built of anApplication: digital clock.

RET);industrial controller;

5) Structured Programming:Definition of the four constructions of structure program-ming;Syntactic definition of two structured languages: a high-level language MICROPASCAL with 11 instructiontypes, a low-level language U, hich is equivalent toL3 augmented of several keywords;Realization of a classical state table with minimalcoding: software implementation based on a single treeand described by a structured MICROPASCAL or L4program;Realization of a classical state table with one-out-of-ncoding: software implementation based on 71 trees (onetree for each state) and described by a unstructured L3program;Applications: reversible co unter, car starter;Conclusion: methods for structuring unstructured pro-grams.

6) Top-Down Programming:9 Method of successive refinements;Case study: the clock algorithm, for a co mplex digital

1

watch;ealization of a classical state machine with RAM.


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First implementation with a complex program and a REFERENCESsimple processing unit (software dominant solution); [ l ] P. W. Samaras, Integrating the first two years,ASE E Prism, pp. 16- 19,Nov. 1991.econd implementation with a simple program and acomplex processing unit (hardware dominant solution). [2 ] E. Cerny, D. Mange, and E. Sanchez, Synthesis of minimal binarydecision trees. IEEE Trans. Comout., vol. C-28. no. 7. DO. 472-482,7)Microprogramming a Universal Processor:

Analysis of an arithmetical and logic unit withregisters (RA LU);Getting a universal processor by the assemblage of abinary decision machine with a stack (control unit) and aRALU (processing unit);Case study: microprogramming the multiplication of twobinary numbers;Further application (for advanced students): micro-programming the compilation of M ICROPASCA L high-level language into L4 low-level language.

Our course is followed in the three next years by morespecialized lectures on hardware (microprocessors, computerarchitecture, etc.): it must be pointed out that students aretaught during the first year a classical course about proce duralprogramming (PASCAL) during 15 sessions of three hourseach and based upon reference [21].C . Related Works

Binary decision trees have become more and more popular,especially for analyzing and testing logic circuits [6]-[SI.Program ming a binary decision machine and using it to replacehardwired logic systems or classical microprocessors is lesspopular; nevertheless, after the historical publications of Lee[9], Clare [ lo] and Boute [l l] , a number of researchers in theUnited States and overseas have paid great attention to thisnew methology and/or have realized VLSI binary decisionmachines:W. I . Fletcher, Utah State University, Logan 1121

M. Andrews, Colorado State University [13] (pp. 210-274);P. J . A. Zsombor-Murray et al., McGill University, Mon-treal, Canada [14];M. Davio et al., Philips Research Laboratory, Brusselsand UniversitC Catholique de L ouvain, Belgium [15];L. D. Coraor et al., Pennsylvania State University, Uni-versity Park [16];A. Ginetti, C. Trullemans, UniversitC Catholique de L ou-vain, Belgium [17];C. Piguet, Centre suisse dile ctron ique et de microtech-nique, Neuch ltel , Switzerland [18].

The course described in this paper is based on the book[19], in French, which w as recently published in English [ZO];significant extracts of the latter can be found in [5].

(pp. 600-645);

, ..July 1979.[3] E. Sanchez and A. Thayse, Implementation and transformation ofalgorithms based o n au tomata, Part 111, Philips J. Res., vol. 36, no. 3,[4] A. Thayse, Synthesis and optimization of programs by means of P -functions, IEEE Trans. Comput., vol. C-31, no. 1, pp. 34-40, Jan.1982.[5] D. A. Mange, A h igh-level-language programmable controller, Parts I-11, IEEE Micro, vol. 6, no. 1, pp. 25-41, Feb. 198 6; no. 2, vol. 6,pp. 47-63, Apr. 1986.[6] S. B. Akers, Bi& decision diagrams, IEEE Trans. Comput., vol. C-27,no. 6, pp. 509-516, June 1978.(71 B. M. E. Moret, Decision trees and diagrams, Computing Surveys,vol. 14, no. 4, pp. 593- 623, Dec. 1982.[8] R. E. Bryant, Graph-based algorithms for boolean function manipula-tion, IEEE Trans. Comput., vol. C-35, no. 8, pp. 677-69 1, Aug. 1986 .[9 ] C.Y . Lee, Representation of switching circuits by binary-decisionprograms, TheBellSyst. Tech.J. , vol. 38, no. 4, pp. 985-999, July 1959.(101 C . R. Clare, Designing Logic Systems Using State Machines. Ne wYork: McGraw-Hill, 1973.

[11] R.T. Boute, The binary decision machine as programmable controller,Euromicro Newsletter, vol. 2, no. 1, pp. 16-2 2, Jan. 1976.(121 W.1. Fletcher, An Engineering Approach to Digital Design. NJ :Prentice-Hall, Englewood Cliffs, 1980.[13] M. Andrews, Principles of Firmware Engineering in MicroprogramControl. London: Pitman, 1981.[141 P. J. A. Zsombo r-Murray, L. J. Vroomen, R. D. Hudson, T. Le-Ngo c, andP. H. Holck, Binary-decision-based programmable controllers, Parts I-111, IEEE Micro, vol. 3, no. 4, pp. 67-83, Aug. 1983; vol. 3, no. 5 ,pp. 16-26 , Oct. 1983; vol. 3, no. 6, pp. 24-39, Dec. 1983.[15] M.,Davio, J.-P. Deschamp s, and A. Thayse, Digital Systems withAlgorithm Implementation. Chichester: John Wiley, 1983.[16] L .D . Coraor, P.T . Hulina, and O.A . Morean, A general model formemory-based finite-state machines, IEEE Trans. Comput., vol. C-36,no. 2, pp. 175-184, Feb. 1987.[17] A. Ginetti and C. Trullemans, Compaction of CD ( 2 k - D) controlunit architectures, Integration, VLSI J. , vol. 9, pp. 179- 197, 1990.[18] C. Piguet, Binary-decision and RISC-like machines for semicustomdesign, Microproc., Microsyst., vol. 14, no. 4, pp. 231 -239, May 1990.[191 D. Mange, Systemes microprogrammes: une introduction au magiciel.Lausanne: Presses polytechniques et universitaires romandes, 1990.[20] -, Microprogrammed Systems: An Introduction to Firmware T he-ory.[21] P. Grogono , Programming in PASCAL. Reading, MA: Addison-Wesley,1984.

pp. 159-172, 1981.

London: Chapman & Hall, 1992.

Daniel Mange (S68-M69) received the M.S. andPh.D. degrees from the Swiss Federal Institute ofTechnology, Lausanne, Switzerland.Since 196 9, he has been a Professor at th e SwissFederal Institute of Technology. He held a positionas Visiting Professor at the Center for ReliableComputing, Stanford University, Stanford, CA, in1987 . He directs the Logic Sys tems Laboratory andis mostly interested in firmware theory (equivalenceand transformation between hardwired systems andprograms), cellular autom ata, and artificial life.

Daniel Mange- Teaching Firmware as a Bridge Between Hardware and Software

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