Current Integrator (CI2005) Status

Feb.28.2006Y.Fujita

Goal Specification Block diagram Status Issues Schedule

Goal• Deadtimeless Current Integrator

Specification• Maximum Clock Freq.: ~ a few MHz• Dynamic range : > 3V• Resolution : ~ 0.02% • INL : ~ 0.5%• Amp spec

– Differential input/output– GB product : ~100MHz– Gain >70dB

• TDC a few nsec resolution for test– TMC type

Block diagram

CI CI CI

SW Delaylatch

Timingcontrol

Integrator out TDC out

-0.5

0

0.5

1

D05 D11 D17 D23 D29

TMC_L06 Delay

deviation [ns] L06 390kdeviation [ns] L06 560kdeviation [ns] L06 1Mdeviation [ns] L06 10M

deviation [ns] L06

OUTPUT

TDC(TMC) part

• TDC implemented for one of CI to confirm function

• Timing resolution < 5nsec is easily achieved

- 0.5ns

0ns

0.5ns

Res

idu

al

Output of Delay chain

Status

• Spec: Modified (TDC part added)• Simulation : Finished (CI only)• Layout : Ready (CI + TDC)• Submit : Jan 10th

Layout (for 0.6um)Control circuit

CI

TMC

comp

Layout of single channel CIインバータ：遅延調整および波形整形

積分容量及びスイッチ

差動アンプ及びスイッチ

Layout cont’d TDC TEGDelay

Latch

Buffer

Issues for next production

• Better INL– Droop (Drain - Source leakage?)– Test of CSMC version asap

• TMC circuit modification– Filter implementation for TMC input signal– Easy operation (PLL etc)– Useful User I/F

Schedule 2006

• New type CI : March 2006– CMFB circuit modified– Test and modification– Specification finalize

• Fab : June 2006• Fab : Aug 2006