CSNSM Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S. Callier, S. Conforti, F....
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Transcript of CSNSM Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S. Callier, S. Conforti, F....
CSNSM
Orsay Micro-Electronics
Groups Associated
P. Barrillon, S. Blin, S. Callier, S. Conforti, F. Dulucq, J. Fleury, C. de La Taille, G. Martin-
Chassard, L. Raux, N. Seguin-Moreau, V. Tocut
+ Xiongbo Yan from IHEP Beijing
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 2
Microelectronics at in2p3
• Large force of microelectronics experienced engineers (~40)
• Expertise in detectors, chip design and test• Experience in designing and building large detectors• Common Cadence tools
• Actions :– Building blocks– Networking– poles
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 3
Motivation for poles
• Continuous increase of chip complexity (SoC, 3D…)
• Importance of critical mass– Daily contacts and discussions between designers– Sharing of well proven blocks– Cross fertilization of different projects
• Creation of poles at in2p3– OMEGA at Orsay– Strasbourg– Dipole Lyon-Clermont
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 4
• Mission
Design of basic building blocks usable by all in2p3 labs for physics experiments
• Motivations– Target analog technology (0.35µm CMOS and SiGe AMS )– Optimize ressources and competences within in2p3 – Increase visibility of in2p3 in microelectronics– reduce developpement times
• First results– 2-3 runs /yr financed by in2p3– Porquerolles workshop– Fruitful exchanges
Club building blocks 0.35µm
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 5
New club 130nm for tracking and 3D
• Networking : club 130nm created at VLSI workshop– Target common technology with CERN or other labs : IBM
130nm with CERN, Chartered 130nm (IBM compatible)
• 3D consortium : CPPM, IPHC, OMEGA, LPNHE– Complementarity– Task sharing– Coordination
• IN2P3 Recommendation : participate to 3D effort in a coherent, coordinated and funded way.
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 6
HARDROC
Orsay Micro-Electronics Groups Associated
• A strong team of 10 ASIC designers…– = 20% of in2p3 designers– = 60% of department research engineers– A team with critical mass : pole created in
2007 = OMEGA– Expertise in low noise, low power high level
of integration ASICs– 2 designers/ project– 2 projects/designer– Regular design meetings
• …Within an electronics departmt of 50 – Support for tests, mesaurements, PCBs…
• A steady production– A strong on-going R&D– Building blocks SiGe 0.35µm
SKIROC
MAROC 2
SPIROC
ASPIC
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 7
Orsay micro-electronics team
• 8 research engineers (1 IR0, 2 IR1, 5 IR2)• 1 CDD IR2 EUDET• 1 phD student• 1 visitor from China IHEP Beijing
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 8
Recent chips
• Several chips developped for ATLAS LAr, OPERA, LHCb, CALICE in BiCMOS 0.8µm and installed on experiments
• Turn to Silicon Germanium 0.35 µm SiGe BiCMOS technology in 2005
• Readout for MaPMT and ILC calorimeters• Very high level of integration : System on Chip (SoC)• Parallel activity of building blocks
SKIROCMAROC 2 HARDROC SPIROCASPIC
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 9
MAROC : 64 ch MAPMT chip for ATLAS lumi
Complete front-end chip for 64 channels multi-anode photomultipliers– Auto-trigger on 1/3 p.e. at 10 MHz, 12 bit charge output– SiGe 0.35 µm, 12 mm2, Pd = 350mW
PMF
Hold signal
PM64 channels
Photons
Variable Gain
Preamp.
Variable
Slow Shaper
20-100 ns
Bipolar
Fast Shaper
Unipolar Fast Shaper
Gain correction64*6bits
3 discris thresholds (3*12 bits)
Multiplexed Analog charge output
LUCID
S&H
3 DACs12 bits
80 MHz encoder
64 Wilkinson 12 bit ADC
64 trigger outputs(to FPGA)
Multiplexed Digital charge output
64 inputs S&H
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 10
Active board pictures
MAROC side Lattice side
64 ch PMTMAROC2 chip bounded at CERN
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 11
MAROC Efficiency curves
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 12
ILC Challenges for electronics
• Requirements for electronics– Large dynamic range (15 bits)– Auto-trigger on ½ MIP – On chip zero suppress– Front-end embedded in detector
– Ultra-low power : («25µW/ch)– 108 channels– Compactness
• « Tracker electronics with calorimetric performance »
• No chip = no detector !!
ATLAS LAr FEB 128ch 400*500mm 1 W/chFLC_PHY3 18ch 10*10mm 5mW/ch ILC : 25µW/ch
W layer
ASIC
Ultra-low POWERis the
KEY issue
Si wafers
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 13
The front-end ASICs : the ROC chips
SPIROCAnalog HCAL(SiPM)36 ch. 32mm²June 07
HARDROCDigital HCAL(RPC, µmegas or GEMs)64 ch. 16mm²Sept 06
SKIROCECAL(Si PIN diode)36 ch. 20mm²Nov 06
• Technological prototypes : full scale modules (~2m)
• EUDET EU funding (06-09)• ECAL, AHCAL, DHCAL• B=5T
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 14
DHCAL chip : HaRDROC
• Hadronic Rpc Detector Read Out Chip (Sept 06)– 64 inputs, preamp + shaper+ 2
discris + memory + Full power pulsing
– Compatible with 1st and 2nd generation DAQ : token ring readout of up to 100 chips
– First test of 2nd generation DAQ – First test detector integration
• Collaboration with IPNL/LLR/Madrid/Protvino– 1m3 scalable detector – Production of 5000 chips in 2009
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 15
HaRDROC architecture
• Variable gain (6bits) current preamps (50ohm input)
• One multiplexed analog output (12bit)
• Auto-trigger on ½ MIP• Store all channels and
BCID for every hit. Depth = 128 bits
• Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits
• Power dissipation : 1.5 mW/ch (unpulsed)-> 15µW with 1% cycle
• Large flexibility via >500 slow control settings
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 16
30 fC
10 fC
Pedestal
Dac
un
it
Channel number
S-curves of 64 channels
• 10 bit DAC for threshold • Noise ~ 1 UDAC (2mV)• Pedestal dispersion : 0.4
UDAC rms• Gain dispersion 3% rms• Crosstalk : < 2%
50% trigger versus channel number
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 17
SKIROC for W-Si ECAL
• Silicon Kalorimeter Integrated Read Out Chip (Nov 06)– 36 channels with 15 bits Preamp + bi-gain shaper +
autotrigger + analog memory + Wilkinson ADC– Digital part outside in a FPGA for lack of time and increased
flexibility– Technology SiGe 0.35µm AMS. Chip received may 07
1 MIP in SKIROC
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 18
12 bit Wilkinson ADC performance
1046 1047 1048 1049 1050 10510
50
100
150
200
250
300
350
400
450
500
ADC bins (#) mean: 1048.283 std : 0.883
Count
(#)
- to
tal is
1000
SKIROC ADC dispersion - channel 18
Noise in low gain shaper
rms = 0.9UADC(330µV)MIP =3 UADC
0 5 10 15 20 25 30 35 401045
1050
1055
1060
1065
1070
1075
1080
1085
AD
C c
ount
(#)
channel number (#)
Skiroc Pedestal Dispersion (Internal ADC)-Gain 1
1050
1080
1055 1060 1065 1070 1075 1080 1085 10900
10
20
30
40
50
60
70
80
90
100
ADC bins (#) mean: 1071.3 std : 4.629
Count
(#)
- to
tal is
1000
SKIROC ADC dispersion - channel 36
Noise in high gain shaper
rms = 4UADC(1.4mV)MIP=30UADC
Pedestal value vs Channel number
0 5 10 15 20 25 30 35 403.6
3.8
4
4.2
4.4
4.6
4.8
5Skiroc Noise Dispersion (Internal ADC)-Gain 10
channel number (#)
AD
C c
ount
RM
S (
#)
Noise vs Channel number
4
5
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 19
Front-end board for ECAL
PCB – FRONT
PCB – BACK
An ASU (Active Sensor Unit)
VFE ASIC bonded in a PCBASIC buried in the PCBASU stitching : zero thickness connection
No component All features embedded in ASIC
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 20
Second generation chip for SiPM
• SPIROC : Silicon Photomul. Integrated Readout Chip– 36 channels– Charge measurement – Time measurement – Autotrigger on MIP or spe– Sparsified readout compatible
with EUDET 2nd generation DAQ– Chips daisy-chained– Pulsed power -> 25 µW/ch
• Fabricated in SiGe AMS 0.35 µm– Submitted in june 07– Chip area : 30 mm2
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 21
SPIROC main features• Internal input 8-bit DAC (0-5V) for individual SiPM gain
adjustment• Energy measurement : 14 bits
– 2 gains (1-10) + 12 bit ADC 1 pe 2000 pe– Variable shaping time from 50ns to 100ns – pe/noise ratio : 11
• Auto-trigger on 1/3 pe (50fC)– pe/noise ratio on trigger channel : 24– Fast shaper : ~10ns– Auto-Trigger on ½ pe
• Time measurement : – 12-bit Bunch Crossing ID– 12 bit TDC step~100 ps
• Analog memory for time and charge measurement : depth = 16• Low consumption : ~25µW per channel (in power pulsing mode)• Individually addressable calibration injection capacitance• Embedded bandgap for voltage references• Embedded 10 bit DAC for trigger threshold and gain selection• Multiplexed analog output for physics prototype DAQ• 4k internal memory and Daisy chain readout
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 22
SPIROC : One channel schematic
IN test
50 -100ns
50-100ns
Gain selection
4-bit threshold adjustment
10-bit DAC
15ns
DAC output
HOLD
Slow Shaper
Slow Shaper
Fast Shaper
Time measurement
Charge measurement
TDC ramp
300ns/5 µs
12-bit Wilkinson
ADC
Trigger
Depth 16
Depth 16
Depth 16
Common to the 36 channels
8-bit DAC
0-5V
Low gain Preamplifier
High gain Preamplifier
Analog memory
15pF
1.5pF
0.1pF-1.5pF
Conversion
80 µs
READ
Variable delay
0.1pF-1.5pF
IN
Discri
Gain
Flag TDC
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 23
DAQASIC
Chip ID register 8 bits
gain
Trigger discri Output
Wilkinson ADC Discri output
gain
Trigger discri Output
Wilkinson ADC Discri output
..…
OR36
EndRamp (Discri ADC Wilkinson)
36
36
36
TM (Discri trigger)
ValGain (low gain or high Gain)
ExtSigmaTM (OR36)
Channel 1
Channel 0
ValDimGray 12 bits
…
Acquisition
readout
Conversion ADC
+
Ecriture RAM
RAM
FlagTDC
ValDimGray
12
8
ChipID
Hit channel register 16 x 36 x 1 bits
TDC rampStartRampTDC
BCID 16 x 8 bits
ADC rampStartrampb (wilkinson
ramp)
16
16ValidHoldAnalogb
RazRangN
16ReadMesureb
Rstb
Clk40MHz
SlowClock
StartAcqt
StartConvDAQb
StartReadOut
NoTrig
RamFull
TransmitOn
OutSerie
EndReadOut
Chipsat
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 24
SPIROC performance
• Good analog performance– Single photo-electron/noise = 8– Auto-trigger with good uniformity– Complex chip : many more measurements needed
• bug in the ADC necessitates an iteration
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 25
Joël Pouthas IPN Orsay
• “PMm2” (2006 – 2009), funded by the ANR : LAL, IPNO, LAPP and Photonis
• Replace large PMTs (20”) by groups of smaller ones (12”)– central 16ch ASIC (PaRISROC)– 12 bit charge + 12 bit time– water-tight, common High Voltage – Only one wire out (DATA + VCC)– Target low cost– Reuse many parts from MAROC &
SPIROC• Application : large water
Cerenkov neutrino – 1ns time resolution– High granularity– scalability
PMm2 : large photodection area
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 26
• Based on a complete 16 channels read out chip with dedicated for Photomultiplier array (PARISROC)
• Measurement of Charge and time
PArISROC specifications
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 27
ASIC Architecture
Channel 16
Channel 1
16 chargeinputs
Variable GainAmplifier
(1-8)
Gain Correction(8bits)
CRRC2Slow Shaper(50 , 100,
200 ns)
DifferentialFast Shaper
(15ns)Discri
12 bitsADC
Track & hold
Threshold
1 digital chargeoutput
variabledelay
1 ext. Common Hold
OR
16 Trigger outputs
24 bits counter10MHz
24bits absolute time measurement
Bandgap
Vref SSH
Vre
f FS
H
Vref SSH
1 OR output
Internal read
DAC10 bits
OR
new blocks
slow control signal
DAC4 bits
Threshold(4bits/ch)
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 28
3D technology
• Increasing integration density, mixing technologies
• Wafer thinning to <50 µm• Minimization of
interconnects• Large industrial demand
– Processors, image sensors…
©A. Klumpp (IZM)
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 29
Major Markets for 3D [R. Yarema FNAL]
• Pixel arrays for imagingPixel arrays with sensors and readout are well suited to 3D integration since signal processing can be placed close to the sensor. Current 2D approaches cannot handle the data rate needed for high speed imaging.
• MemoryAll major memory manufactures are working on 3D memory stacks. Significant cost reductions can be expected for large memory devices. The cost of 3D can be significantly less than going to a deeper technology node.
• MicroprocessorsA major bottleneck is access time between CPU and the memory. Memory caches are used as an interface but the area required is significant. Initial applications for 3D will use Logic to Memory, and Logic to Logic stacking. (Samsung)
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 30
3D consortium
• Collaboration between IN2P3, INFN and FNAL– SLHC, ILC and SuperB applications
• Chartered 0.13µm and Tezzaron process chosen – « IBM compatible » process– Via first : 1-2 µm vias– Assembled by Tezzaron – Run coordinated by FNAL
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 31
• 8 inch wafers• Large reticule – 24 mm x 32 mm• Features
– Deep N-well– MiM capacitors – 1 fF/um2
– Single poly– 8 levels of metal available– Zero Vt (Native NMOS) available– A variety of transistor options with
multiple threshold voltages can be used simultaneously
• Nominal• Low voltage• High performance• Low power
Eight inches
Chartered 0.13 um Process
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL
32
Tezzaron 3D Process• Complete back end of line (BEOL) processing by
adding Cu metal layers and top Cu metal (0.8 um)
6 um
Cu
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL
33
Tezzaron 3D Process
Flip 2nd wafer on top of first wafer.
Bond second wafer to first wafer using Cu-Cuthermo-compression bond.
Example: bonding identical wafers
CuCubond
12um
Thin second wafer to about 12um to expose super via.
Add metallization to back of2nd wafer for bump bond or wire bond. ORAdd Cu to back of 2nd waferto bond 2nd wafer to 3rd wafer
Cu for wafer bond to 3rd layer
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 34
Reticule
Waf er Map
TX 1 T X 2T Y1 T Y 2
A 1 B1 B 2 A 2
C1 D1 D2 C2
E1 F 1 F 2 F 2
G1 H 1 H 2 G2
J 1 K 1 K 2 J 2
Yellow =FranceGreen =I talyBlue =USAMagenta =alignmentGrey =test chips
Chip X=6.4 mmChip Y=5.5 mmTest chip Y=1.9 mmAlignment=1.0x25.9 mmFrame X=26mm, Y=31mmStreets =100 um
100 umstreet
Waf er center line
Alignment area
Blowup of waf er center lines
1mm
TX1 TX2TY1 TY2
A1 B1 B2 A2
C1 D1 D2 C2
E1 F1 F2 F2
G1 H1 H2 G2
J 1 K1 K2 J 2
Frame layout
E2
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL
TWEPP-08
35
Three Tier Arrangement for VIP1 Pixel : FNAL
22 um
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 36
3D for ATLAS
• CPPM : – move FEI4 from IBM 0.13µm to FEC4 Chartered 0.13µm (2D)– Target Mosis run 23/1/09– Fold FEC4 2D chip into FETC4 chip 3D (CPPM, Bonn,LBL) , keep analog
part in analog tier and put a simple register in digital tier
• LAL :– Study smaller pixels (50x50µm instead of 50x250)– Match Munich new ATLAS pixel prototype– Target 10 µW/ch => 400 mW/cm2
– Design analog tier with low noise low power preamp including shaping + threshold DAC
– Discriminator in digital tier + dynamic memory– Study digital coupling to analog tier with discri in digital tier – Study variants of blocks for FEI4 (preamp, discri,DAC, local storage…)
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 37
Next steps
• Omega will participate to march08 run
• Aim at studying 3D design for low power, small area pixels
• Will submit a chip with – One analog tier of low power, low
noise preamp, low offset discriminator for 50x50µ pixels
– One digital tier of local memory, sparsification and readout
• Collaboration with – ATLAS pixel group– FNAL CMS SLHC (R. Yarema)– INFN SuperB (V. Re)
Sensor layer
Pad
50 m
Pad
AnalogueAOP
Digital tier
Orsay, 19 jan 2009 C. de La Taille - microelectronics at OMEGA-LAL 38
Conclusion
• MAROC, HaRDROC, SKIROC, SPIROC…– 4 complex ASICs prototyped in 2007 : 2nd
generation chips– SoC : System on chip (ADC, TDC, DAQ…)– Production in 2009 in a dedicated run ILC
main customer– Many external requests– Long and difficult measurements…
• Coming up : 3D– CMOS 130nm– Basic analog tier for 3D integration in
collaboration with CPPM Marseille aimed at 50x50µm pixels simple readout.