CSN221_Lec_4.pdf
Transcript of CSN221_Lec_4.pdf
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Course Website: http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.htmlPiazza Site: https://piazza.com/iitr.ac.in/fall2015/csn221
Dr. Sudip Roy
CSN‐221: COMPUTER ARCHITECTURE AND MICROPROCESSORS
Computer Organization, CPU Structure and Functions
(Lecture - 4)
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What does a processor work?
• The CPU must be designed to accommodate the instructions and data to be processed
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System Bus
System Bus
Control Bus
Data Bus
Address Bus
I/O 1
CPU RAM
I/O 2
ALU
CU
Regs
PC
PSW
IRInternalCPU Bus
I/O n
Main Memory (RAM)
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CPU Structure and Functions:
• What CPU does?
1. Fetch instructions
2. Interpret (decode) instructions
3. Fetch data
4. Process data
5. Write data
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CPU Internal Structure (Processor Organization):
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Internal Registers:
• Working space (temporary storage) of processor
• Called registers
• Number and function vary between processor designs
• One of the major design decisions
• Top level of memory hierarchy
• The registers in the CPU perform two roles:
User‐visible registers: assembly‐language programmer can minimize the main memory referencing by optimizing the use of registers
Control and status registers: Used by the control unit to control the operation of the CPU
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Internal Registers:
• User‐visible registers:
1. General Purpose registers: (between 8 – 32 in number) FP register, stack operation register
2. Data registers: Only to hold data, Often possible to combine two data registers (e.g., double int a; long int a;)
3. Address registers: To hold address, like Segment Register, Stack Pointer
4. Condition Codes: Holds flag values of the result, like +ve, ‐ve, zero or overflow
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Internal Registers:
• Control and Status registers:
1. Program Counter (PC): Contains address of an instruction to be fetched
2. Instruction Register (IR): Contains the instruction most recently fetched
3. Memory Address Register (MAR): Contains the address of a location in memory
4. Memory Buffer Register (MBR): Contains the data to be written to the memory or data most recently read
• Program Status Word (PSW): A set of bits, Includes Condition Codes, Common fields are:• Sign: A sign bit of the last arithmetic operation• Zero: A bit set when the result is zero• Carry: Set if an operation resulted in a carry (addition) or a borrow (subtraction) out of a high‐
order bit• Equal: Set if a logical compare result is equality• Overflow: To indicate arithmetic overflow• Interrupt enable/disable: To enable/disable interrupt• Supervisor: To indicate whether the CPU is executing in supervisor or user mode
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Datapath and Control:
• Datapath:
• Memory, registers, adders, ALU, and communication buses
• Each step (fetch, decode, execute, save result) requires communication (data transfer) paths between memory, registers and ALU
• Control:
• Datapath for each step is set up by control signals that set up dataflow directions on communication buses and select ALU and memory functions
• Control signals are generated by a control unit consisting of one or more finite‐state machines
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