CSL718 : Superscalar Processors

Anshul Kumar, CSE IITD

CSL718 : Superscalar CSL718 : Superscalar ProcessorsProcessors

CSL718 : Superscalar CSL718 : Superscalar ProcessorsProcessors

Handling Data Dependencies

24th Jan, 2006

Anshul Kumar, CSE IITD slide 2

Illustration 1Illustration 1Illustration 1Illustration 1

CDC6600 : score-boarding scheme

• Dispatch bound fetch

• FUs : INT, MUL1, MUL2, ADD/SUB, DIV

• 1 RS per FU

• 1 RF

• In order issue, dispatch order trivial, out of order execution


Checking in dispatch bound fetchChecking in dispatch bound fetchChecking in dispatch bound fetchChecking in dispatch bound fetch

RegisterFile

Reservationstation

OC Rs1 Rs2 Rd

EU

decodedinstruction

check V bits of sources

update Rdset V bitRs1,Rs2,Rd

reset V bit of Rd

OC(opcode)

Os1

Os2 (operand value)

result, Rd

INSTRUCTION ISSUE READ OP EX COMPL WRITERES

LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2

NoNAME BUSY OP Fi Fj Fk Qj Qk Rj Rk

1 INT

2 MUL1

3 MUL2

4 ADD

5 DIV

F0 F2 F4 F6 F8 F10 F12 F14

FU No

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT Y LF

2 MUL1 Y MUL

3 MUL2 N

4 ADD Y SUB

5 DIV Y DIV

F0 F2 F4 F6 F8 F10 F12 F14

FU No

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT Y LF F2 R3

2 MUL1 Y MUL F0 F2 F4

3 MUL2 N

4 ADD Y SUB F8 F6 F2

5 DIV Y DIV F10 F0 F6

F0 F2 F4 F6 F8 F10 F12 F14

FU No

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT Y LF F2 R3 Y Y

2 MUL1 Y MUL F0 F2 F4 1 N Y

3 MUL2 N

4 ADD Y SUB F8 F6 F2 1 Y N

5 DIV Y DIV F10 F0 F6 2 N Y

F0 F2 F4 F6 F8 F10 F12 F14

FU No 2 1 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT Y LF F2 R3 N N

2 MUL1 Y MUL F0 F2 F4 1 N Y

3 MUL2 N

4 ADD Y SUB F8 F6 F2 1 Y N


F0 F2 F4 F6 F8 F10 F12 F14

FU No 2 1 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N

2 MUL1 Y MUL F0 F2 F4 Y Y

3 MUL2 N

4 ADD Y SUB F8 F6 F2 Y Y


F0 F2 F4 F6 F8 F10 F12 F14

FU No 2 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N

2 MUL1 Y MUL F0 F2 F4 N N

3 MUL2 N

4 ADD N


F0 F2 F4 F6 F8 F10 F12 F14

FU No 2 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N


3 MUL2 N

4 ADD Y ADD F6 F8 F2 Y Y


F0 F2 F4 F6 F8 F10 F12 F14

FU No 2 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N


3 MUL2 N

4 ADD Y ADD F6 F8 F2 N N


F0 F2 F4 F6 F8 F10 F12 F14

FU No 2 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N

2 MUL1 N

3 MUL2 N


5 DIV Y DIV F10 F0 F6 Y Y

F0 F2 F4 F6 F8 F10 F12 F14

FU No 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N

2 MUL1 N

3 MUL2 N


5 DIV Y DIV F10 F0 F6 N N

F0 F2 F4 F6 F8 F10 F12 F14

FU No 4 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


1 INT N

2 MUL1 N

3 MUL2 N

4 ADD N

5 DIV Y DIV F10 F0 F6 N N

F0 F2 F4 F6 F8 F10 F12 F14

FU No 5

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


Illustration 2Illustration 2Illustration 2Illustration 2

IBM 360/91 - Tomasulo’s scheme

• Issue bound fetch

• FUs : LOAD, STORE, 3 x ADD/SUB,

2 x MUL/DIV

• Group RS’s with 1 slot per FU

• 1 RF

• In order issue, out of order execution


Checking in issue bound fetchChecking in issue bound fetchChecking in issue bound fetchChecking in issue bound fetch

OC Os1/Is1 Vs1 Os2/Is2 Vs2 Rd

EU

decodedinstruction

OC, Os1, Os2, Rd

result, Rd

RegisterFile

update Rd, set V bitRs1,Rs2,Rdreset V bit of Rd

Os1

Os2 (operand value)

Reservation station check Vs1, Vs2

associative update ofIs1, Is2 with Rd, set Vs bits

INSTRUCTION ISSUE EX COMPL WRITERES

LF F6, 34(R2)

LF F2, 45(R3)

MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2

NAME BUSY OP Vj Vk Qj Qk

ADD1

ADD2

ADD3

MUL1

MUL2

F0 F2 F4 F6 F8 F10 F12 F14

Qi

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3) MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


ADD1 Y SUB

ADD2 Y ADD

ADD3 N

MUL1 Y MUL

MUL2 Y DIV

F0 F2 F4 F6 F8 F10 F12 F14

Qi

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3) MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


ADD1 Y SUB (LD1) LD2

ADD2 Y ADD ADD1 LD2

ADD3 N

MUL1 Y MUL (F4) LD2

MUL2 Y DIV (LD1) MUL1

F0 F2 F4 F6 F8 F10 F12 F14

Qi MUL1 LD2 ADD2 ADD1 MUL2

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3) MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


ADD1 Y SUB (LD1) (LD2)

ADD2 Y ADD (LD2) ADD1

ADD3 N

MUL1 Y MUL (LD2) (F4)


F0 F2 F4 F6 F8 F10 F12 F14

Qi MUL1 ADD2 ADD1 MUL2

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3) MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


ADD1 N

ADD2 Y ADD (ADD1) (LD2)

ADD3 N



F0 F2 F4 F6 F8 F10 F12 F14

Qi MUL1 ADD2 MUL2

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3) MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


ADD1 N

ADD2 N

ADD3 N



F0 F2 F4 F6 F8 F10 F12 F14

Qi MUL1 MUL2

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


LF F6, 34(R2)

LF F2, 45(R3) MUL F0,F2,F4

SUB F8,F6,F2

DIVF10,F0,F6

ADD F6,F8,F2


ADD1 N

ADD2 N

ADD3 N

MUL1 N

MUL2 Y DIV (MUL1) (LD1)

F0 F2 F4 F6 F8 F10 F12 F14

Qi MUL2

Inst

ruct

ion

stat

usF

unct

iona

l Uni

tsR

F


End of IllustrationEnd of IllustrationRef: Hennesy & Patterson’s Book [Ch. 4]Ref: Hennesy & Patterson’s Book [Ch. 4]

End of IllustrationEnd of IllustrationRef: Hennesy & Patterson’s Book [Ch. 4]Ref: Hennesy & Patterson’s Book [Ch. 4]


RAW, WAR and WAWRAW, WAR and WAW(in Static Pipeline)(in Static Pipeline)

RAW, WAR and WAWRAW, WAR and WAW(in Static Pipeline)(in Static Pipeline)

IF D RF EX WB

IF D RF EX WB

IF D RF EX WB

IF D RF EX WB

RAW

WAR

IF D RF EX WB

IF D RF EX WBWAW

EX EX


RAW, WAR and WAWRAW, WAR and WAW(in Superscalar)(in Superscalar)

RAW, WAR and WAWRAW, WAR and WAW(in Superscalar)(in Superscalar)

IF IS DP EX WB

IF IS DP EX WB

IF IS DP EX WB

write

read

write

RAW

WARWAW


Implementation using scoreboard bitImplementation using scoreboard bitImplementation using scoreboard bitImplementation using scoreboard bit

IF IS DP EX WB

IF IS DP EX WB

IF IS DP EX WB

write

read

write

RAW

WARWAW

b 0 b 1

b 0


CDC 6600 like ImplementationCDC 6600 like ImplementationCDC 6600 like ImplementationCDC 6600 like Implementation

IF IS DP EX WB

IF IS DP EX WB

IF IS DP EX WB

write

read

write

RAW

WARWAW

b 0 b 1

b 0


IBM 360 like ImplementationIBM 360 like ImplementationIBM 360 like ImplementationIBM 360 like Implementation

IF IS DP EX WB

IF IS DP EX WB

IF IS DP EX WB

write

read

write

RAW

WARWAW

b 0 b 1

b 0


Use of RenamingUse of RenamingUse of RenamingUse of Renaming

IF IS DP EX WB

IF IS DP EX WB

IF IS DP EX WB

write

read

write

RAW

WARWAW

CSL718 : Superscalar Processors

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