CSE 2021: Computer Organizationskhan/course/2021S11/slides/Lec8-1-1up.pdf · –single: bias = 127;...
Transcript of CSE 2021: Computer Organizationskhan/course/2021S11/slides/Lec8-1-1up.pdf · –single: bias = 127;...
CSE 2021: Computer Organization
Lecture-8(a)Floating point computing (IEEE 754)
Shakil M. Khan(adapted from Profs. Roumani & Asif)
Review: IEEE-754
• S: sign bit (0 non-negative, 1 negative)
• Normalize significand: 1.0 ≤ |significand| < 2.0– leading pre-binary-point 1 bit represented implicitly– significand is fraction with the “1.” restored
• Exponent: actual exponent + Bias– ensures exponent is unsigned– single: bias = 127; double: bias = 1203
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S Exponent Fraction
single: 8 bitsdouble: 11 bits
single: 23 bitsdouble: 52 bits
Bias)(ExponentS 2Fraction)(11)(x
Examples
• 13.75
– single: 0x415C0000
– double: 0x00000000 402B8000
• -15.2
– single: 0xC1733333
– double: 0x66666666 C02E6666
• 0.001
– single: 0x3A83126F
– double: 0xD2F1A9FC 3F50624D
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Exercises
• Represent 17.4 as a float
• What is the largest possible IEEE float?
• How many floats between 64,005 and 64,006?
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FP Support in MIPS
• Directives in .data
– .float and .double (note the alignment)
• Register Set
– separate set of 32 regs, $f0-$f31, with even-odd pairing
• I/O System Calls
– Syscall 2,3 (print) and 6,7 (read)
• Co-Processor
– the FP instruction subset
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Floating Point Registers
• The following is the established register usage convention for the floating point registers:
– $f0 - $f3: Function-returned values
– $f4 - $f11: Temporary values
– $f12 - $f15: Arguments passed into a function
– $f16 - $f19: More Temporary values
– $f20 - $f31: Saved values
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Name Example Comments
32 floating point
registers each is
32 bits long
$f0 - $f31
MIPS floating point registers are
used in pairs for double
precision numbers
Floating Point Instructions (1)
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Category Instruction Example Meaning
Ari
thm
eti
c
FP add single add.s $f2,$f4,$f6 $f2 ← $f4+$f6
FP subtract single sub.s $f2,$f4,$f6 $f2 ← $f4-$f6
FP multiply single mul.s $f2,$f4,$f6 $f2 ← $f4×$f6
FP divide single div.s $f2,$f4,$f6 $f2 ← $f4/$f6
FP add double add.d $f2,$f4,$f6 $f2 ← $f4+$f6
FP subtract double sub.d $f2,$f4,$f6 $f2 ← $f4-$f6
FP multiply double mul.d $f2,$f4,$f6 $f2 ← $f4×$f6
FP divide double div.d $f2,$f4,$f6 $f2 ← $f4/$f6
Floating Point Instructions (2)
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Category Instruction Example Meaning
Da
ta
Tra
nsf
er
load word copr.1 lwc1 $f2,100($s2) $f2 ← Mem[$s2+100]
store word copr.1 swc1 $f2,100($s2) Mem[$s2+100] ← $f2
Co
nd
itio
na
l B
ran
ch
FP compare single
(eq, ne, lt, le, gt, ge)c.lt.s $f2,$f4
if($f2<$f4)cond = 1,
else cond = 0
FP compare double
(eq, ne, lt, le, gt, ge)c.lt.d $f2,$f4
if($f2<$f4)cond = 1,
else cond = 0
Branch on FP true bc1t 25if cond==1 go to
PC+100+4
Branch on FP false bc1f 25if cond==0 go to
PC+100+4
Exercises
• Read a float; multiply it by 4; output
• As above but read from .data
• As above but w/o using the FP mult
• As above but for double
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Example# calculate area of a circle
.data
Ans: .asciiz "The area of the circle is: "
Ans_add: .word Ans # Pointer to String (Ans)
Pi: .double 3.1415926535897924
Rad: .double 12.345678901234567
Rad_add: .word Rad # Pointer to float (Rad)
.text
main: lw $a0, Ans_add($0) # load address of Ans into $a0
addi $v0, $0, 4 # Sys Call 4 (Print String)
syscall
#---------------- # load float (Assembler Instruction)
la $s0, Pi # load address of Pi into $s0
ldc1 $f2, 0($s0) # $f2 = Pi
#---------------- # load float (MIPS Instruction)
lw $s0, Rad_add($0) # load address of Rad into $s0
ldc1 $f4, 0($s0) # $f4 = Rad
mul.d $f12, $f4, $f4
mul.d $f12, $f12, $f2
addi $v0, $0, 3 # Sys Call 3 (Print Double)
syscall
exit: jr $ra
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CSE 2021: Computer Organization
Lecture-8(b)Intro. to hardware, Boolean algebra, Logic gates
Combinational circuits (MUX, ALU)
Shakil M. Khan(adapted from Profs. Roumani & Asif)
The Hardware Trail
1. From Ideas to 0’s and 1’s
2. The S/W H/W Interface
3. Inside the CPU
4. How is it made?
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The Software Trail … … … … … …
High Level Assembly
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The Software Trail … … … … … …
High Level Assembly
add $t0, $a0, $0
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Assembly Machine
… … … The Software Trail … … …
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Assembly Machine
… … … The Software Trail … … …
000000 00100 00000 01000 00000 100000
add $t0, $a0, $0
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Machine Disk
… … … … … … The Software Trail
Executable File
The Hardware Trail
1. From Ideas to 0’s and 1’s
2. The S/W H/W Interface
3. Inside the CPU
4. How is it made?
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Disk DRAM
Launch, Link, and Load
Executable
File
Library File
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Disk DRAM
Launch, Link, and Load
Executable
File
Library File
000000 00100 00000 01000 00000 100000
Address Content
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DRAM CPU
The Fetch-Decode-Execute Cycle
0x0040002cPC
Send PCSend Content
000000 00100 00000 01000 00000 100000
0x00400030WAIT
The Hardware Trail
1. From Ideas to 0’s and 1’s
2. The S/W H/W Interface
3. Inside the CPU
4. How is it made?
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Inside the CPU
• The CPU circuits must be able to:
– “look” at the bits coming from DRAM
– “interpret” the instruction
– and then “make it happen”
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Decode
Execute
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The Fetch-Decode-Execute Cycle
A
L
U
REGISTER FILE
000000
00100 0
0000 0
1000
00000
100000
datapath control
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The Fetch-Decode-Execute Cycle
A
L
U
REGISTER FILE
000000
00100 0
0000
01000
00000
100000
PC
The Hardware Trail
1. From Ideas to 0’s and 1’s
2. The S/W H/W Interface
3. Inside the CPU
4. How is it made?
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How is it Made?
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CPU< datapath + control >
GATES< and/or/not, nand, nor >
TRANSISTORS< mosfet >
SAND< silicon >
Peek below Gates
• Cf. Lecure 1
– transistor switches
– semiconductors
– …
– wafers, polished wafers
– ingot
– silicon (sand)
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Logic Gates: AND, OR
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1. AND Gate:
2. OR Gate
)( bac
Notation
ab c
Symbol
Truth Table
111
001
010
000
c = a · bba
)( bac
NotationSymbol
Truth Table
111
101
110
000
c = a + bba
ab
c
Logic Gates: NOT
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3. NOT Gate (Inverter):
),( aac Notation
SymbolTruth Table
cb
01
10
ca
Universal Gates
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Truth Table
011
101
110
100
Fyx
Truth Table
011
001
010
100
Fyx
Combinational Circuits: XOR
• Does this circuit behave like an XOR?
• How can we prove / verify that claim?
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a
b
z
Verilog Code
module first;
reg a, b;
wire alpha, beta;
wire notA, notB;
not myNot1(notA, a);
not myNot2(notB, b);
and upperAnd(alpha, a, notB);
and lowerAnd(beta, notA, b);
or finalOr(z, alpha, beta);
...
...
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Exercises
• Cf. – labs K – N,
– textbook Appendix C.4
– programs developed in class
• Complete the verification using:– hard-coded inputs
– command-line inputs
– sampled inputs
– exhaustive testing
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Combinational Circuits: MUX
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; else
; ),0( if
bc
acs
Notation
Symbol
Truth Table
b1
a0
cs
cb
a
s
Verify that the following circuit functions as:
C = (S == 0) ? A : B
Boolean Algebra (1)
• Logic operations/circuits can be expressed in terms of logic equations
• To implement the above digital circuit, 2 AND, 1 NOT and 1 OR gates are required
• Can we simplify the above circuit?
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AB
C
BAABC
Boolean Algebra (2)
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Expressions
Identity LawA + 0 = A
A · 1 = A
Zero and One LawA + 1 = 1
A · 0 = 0
Inverse LawA + Ā = 1
A · Ā = 0
Commutative lawA + B = B + A
A · B = B · A
Associative LawA + (B + C)= (A + B) + C
A · (B · C) = (A · B) · C
Distributive LawA · (B + C) = (A · B) + (A · C)
A + (B · C) = (A + B) · (A + C)
Boolean Algebra (3)
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Expressions
De Morgan’s
Law
BABA )(
BABA )(
Boolean Algebra (4)
• Exercise 1:– simplify the expressions:
• Exercise 2:– implement simplified expressions for (a) – (e)
using OR, AND, and NOT gates
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))(()(
)()(
))(()(
)(
)(
DCBADACBe
zwwzxxyd
yxyxc
xzyzxbCABABCBAa