CSE 140L Lecture 6Interface and State Assignment

Professor CK Cheng

CSE Dept.

UC San Diego

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Interface: Quality of Input Signal

• Debouncers– Double-Throw Switch– Single-Throw Switch

• Synchronizers– Metastability– Synchronization

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Debouncers: Double-Throw Switch

Time 0 1 2 3 4 5 6 7 8

A 0 1 1 1 1 1 1 1 1

B 1 1 0 1 0 1 0 0 0

X 1 1 0 0 0 0 0 0 0

Y 0 0 1 1 1 1 1 1 1

SR debouncer

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Debouncers: Single-Throw SwitchPull down

Vcap/Vinitial = e –t/RC

R2C= -T/ln(Vth/Vdd)Push up

Vcap/Vfinal= 1-e-t/RC

(R1+R2)C= -T/ln(1-Vth/Vdd)Bounce time < T=20msec

4

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Synchronizer: Input may occur any time

• Asynchronous (for example, user) inputs might violate the dynamic discipline

CLK

tsetup thold

taperture

D

Q

D

Q

D

Q ???

Cas

e I

Cas

e II

Cas

e II

I

D Q

CLK

butt

on

Synchronizer: Metastability

• Metastability: A synchronizer failure that the voltage falls between 0 and 1.

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3-<7>

Metastability• Any bistable device has two stable states and a metastable state

between them

• A flip-flop has two stable states (1 and 0) and one metastable state

• If a flip-flop lands in the metastable state, it could stay there for an undetermined amount of time

metastable

stablestable

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Flip-flop Internals

R

S

Q

Q

N1

N2

• Because the flip-flop has feedback, if Q is somewhere between 1 and 0, the cross-coupled gates will eventually drive the output to either rail (1 or 0, depending on which one it is closer to).

• A signal is considered metastable if it hasn’t resolved to 1 or 0

• If a flip-flop input changes at a random time, the probability that the output Q is metastable after waiting some time, t, is:

P(tres > t) = (T0/Tc ) e-t/τ

tres : time to resolve to 1 or 0

T0, τ : properties of the circuit

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Metastability• Intuitively:

– T0/Tc describes the probability that the input changes at a bad time, i.e., during the aperture time

P(tres > t) = (T0/Tc ) e-t/τ

– τ is a time constant indicating how fast the flip-flop moves away from the metastable state; it is related to the delay through the cross-coupled gates in the flip-flop

P(tres > t) = (T0/Tc ) e-t/τ

• In short, if a flip-flop samples a metastable input, if you wait long enough (t), the output will have resolved to 1 or 0 with high probability.

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Synchronizers

D Q

CLK

SY

NC

• Asynchronous inputs (D) are inevitable (user interfaces, systems with different clocks interacting, etc.).

• The goal of a synchronizer is to make the probability of failure (the output Q still being metastable) low.

• A synchronizer cannot make the probability of failure 0.

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Synchronizer Internals

D

Q

D2 Q

D2

Tc

tsetup tpcq

CLK CLK

CLK

tres

metastable

F1 F2

• A synchronizer can be built with two back-to-back flip-flops.

• Suppose the input D is transitioning when it is sampled by flip-flop 1, F1.

• The amount of time the internal signal D2 can resolve to a 1 or 0 is (Tc - tsetup).

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Synchronizer: Shifter

D

Q

D2 Q

D2

Tc

tsetup tpcq

CLK CLK

CLK

tres

metastable

F1 F2

Allocate one clock cycle for logic to settle at 0 or 1.

For each sample, the probability of failure of this synchronizer is:

P(failure) = (T0/Tc ) e-(Tc

- tsetup

)/τ

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Synchronizer Mean Time Before Failure

• If the asynchronous input changes once per second, the probability of failure per second of the synchronizer is simply P(failure).

• In general, if the input changes N times per second, the probability of failure per second of the synchronizer is:

P(failure)/second = (NT0/Tc) e-(Tc

- tsetup

)/τ

• Thus, the synchronizer fails, on average, 1/[P(failure)/second]

• This is called the mean time between failures, MTBF:

MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc

- tsetup

)/τ

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Example Synchronizer

D D2 Q

CLK CLK

F1 F2

• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps

T0 = 150 ps tsetup = 100 ps

N = 1 events per second

• What is the probability of failure? MTBF?

P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps

= 5.6 × 10-6

P(failure)/second = 10 × (5.6 × 10-6 ) = 5.6 × 10-5 / second MTBF = 1/[P(failure)/second] ≈ 5 hours

State Assignment

• Binary Code: log2n flip-flops for n states

• Gray Code: log2n flip-flops for n states

• Johnson Code: n/2 flip-flops for n states

• “Don’t Care” State Encoding

• One Hot Code: n flip-flops for n states

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“Don’t Care” State Encoding• State i Qj= 0 for all j > i,

Qi= 1

Qj= x for all j < i.

Qn-1 Qn-2 … Q1 Q0

Sn-1 1 x x x x

Sn-2 0 1 x x x

… … … …

S1 0 0 0 1 x

S0 0 0 0 0 1

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State Assignment: One Hot Code

• For n states, we use n flip-flops.

• Each state corresponds to a flip-flop.

• Qi= 1 iff present state = state i. Thus, one and only one flip-flop contains a “1”.

• We use OR gate to collect input edges.

• We use Mux gate to distribute the output edges.

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State Assignment: One Hot

s0sS0 S1 S2

01

0

1

0

1

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3. Transformation from Mealy to Moore Machine

Moore Machine: y(t) = f(x(t), s(t))Mealy Machine: y(t) = f(s(t))

s(t+1) = g(x(t), s(t))

C1 C2

CLK

x(t)

y(t)

Mealy Machine

C1 C2

CLK

x(t) y(t)

Moore Machine

s(t) s(t)

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