CSE 140L-Lecture 6 - Computer Science and 140L-Lecture 6.pdf · 6 Vending Machine (Cont.) zSuitable...
Transcript of CSE 140L-Lecture 6 - Computer Science and 140L-Lecture 6.pdf · 6 Vending Machine (Cont.) zSuitable...
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CSE140 L
Instructor: Thomas Y. P. Lee
February 15, 2006
AgendaLab3
Counters are FSMFinite State MachineModels to represent FSM – Mealy Machine and Moore Machine
FSM Design ProcedureState DiagramState Transition TableNext State Logic Functions
Example One – Vending MachineMealy Machine ImplementationMoore Machine Implementation
Quartus II Tutorial – Finite State Machine ImplementationImproved Vending Machine
Moore Machine ImplementationMealy Machine Implementation
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Acknowledgement
Materials in this lecture are courtesy of the following people Randy H. Katz (University of California, Berkeley, Department ofElectrical Engineering &Computer Science)MIT Prof. Anantha Chandrakasan and Donald E. Troxel “Introduction to Digital System Design Lab”Professor C.K.Cheng, CSE140LJohn F. Wakerly, Digital Design, “Principles and Practices”, 3rd edition
Counters are FSM
010
100
110
011001
000
101111
3-bit up-counter
Countersproceed through well-defined sequence of states in response to enable
Many types of counters: binary Up/Down, BCD, Gray-code,Divide-by-3,…
3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
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Finite State MachineFinite State Machines (FSMs) are a useful abstraction for sequential circuits with “states” of operationAt each clock edge, combinational logic block computes outputs and next state as a function of inputs and present state
Two Types of FSM - Mealy and Moore
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Pipelined State Machine
Often used in PLD-based state machines.Outputs taken directly from flip-flops, valid sooner after clock edge.But the “output logic” must determine output value one clock tick sooner (“pipelined”).
Comparison of Mealy and Moore Machine
Mealy machines tend to have less statesdifferent outputs on arcs (n2) rather than states (n)
Moore machines are safer to useoutputs change at clock edge (always one cycle later)In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback may occur if one isn’t careful
Mealy machines react faster to inputsreact in same cycle – don't need to wait for clockin Moore machines, more logic may be necessary to decode stateinto outputs – more gate delays after clock edge
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State Machine Analysis Steps
Assumption: Starting point is a logic diagram.1. Determine next-state function and output function2. Construct state (transition) table
For each state/input combination, determine the excitation value.Using the characteristic equation, determine the corresponding next-state values (trivial with DFF’s)
3. Construct output tableFor each state/input combination, determine the output value (Can be combined with state table.)
4. Draw state diagram
VendingMachine
FSM
N
D
Reset
Clock
OpenCoinSensor
ReleaseMechanism
Example in Katz’s Book: Vending Machine
Release one item after 15 cents are depositedSingle coin slot for dimes, nickelsNo change.- not realisticThe controller’s cause a single item to be released down a chute to the customer -> how to choose different items?
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Vending Machine (Cont.)
Suitable abstract representationtypical input sequences:
3 nickelsnickel, dimedime, nickeltwo dimes
draw state diagram:inputs: N, D, resetoutput: open chute
assumptions:assume N and D assertedfor one cycleeach state has a self loopfor N = D = 0 (no coin)
S0
Reset
S2
D
S6[open]
D
S4[open]
D
S1
N
S3
N
S5[open]
N
S8[open]
D
S7[open]
N
Initial vending-machine state diagram
Minimized Vending Machine’s StatesMinimize number of states - reuse states whenever possibleS4,S5….,S8 have identical behavior=> combine into a single state
Minimized symbolic state transition table
present inputs next outputstate D N state open
0¢ 0 0 0¢ 00 1 5¢ 01 0 10¢ 01 1 X X
5¢ 0 0 5¢ 00 1 10¢ 01 0 15¢ 01 1 X X
10¢ 0 0 10¢ 00 1 15¢ 01 0 15¢ 01 1 X X
15¢ X X 15¢ 1
0¢
Reset
5¢
N
N
N + D
10¢
D
15¢[open]
D
Minimized vending-machine state diagram
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Vending Machine Encoded State Transition Table
Uniquely encode states
present state inputs next state outputQ1 Q0 D N D1 D0 open0 0 0 0 0 0 0
0 1 0 1 01 0 1 0 01 1 X X X
0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 X X X
1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 X X X
1 1 0 0 1 1 10 1 1 1 1
present state inputs next state outputQ1 Q0 D N D1 D0 open0 0 0 0 0 0 0
0 1 0 1 01 0 1 0 01 1 X X X
0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 X X X
1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 X X X
1 1 0 0 1 1 10 1 1 1 11 0 1 1 11 1 X X X
Moore Implementation of Vending Machine
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
Mapping to Truth Table
0 0 1 10 1 1 1X X X X1 1 1 1
Q1D1
Q0
ND
0 1 1 01 0 1 1X X X X0 1 1 1
Q1D0
Q0
ND
0 0 1 00 0 1 0X X X X0 0 1 0
Q1Open
Q0
ND
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Encoding in State Machine• State Machine Encoding Style:
Binary, One-hot, Two-hot, Gray code, Johnson Code
Binary encoding Requires the least number of FFs. With n FFs, 2n statescan be encoded. Disadvantages: require more logic, slower.One-hotencodingone FF per state, with n FFs, n states can be encoded. Require the least amount of extra logic and fastestTwo- hot encodingPresents two bits active per state. With n FFs, n(n-1)/2 states can be encoded.Gray code encodingAdjacent Gray codes are different in only one bit. n bits Gray code needs n FFs and can represent 2n states. Johnson code encodingUse the output pattern of Johnson counter to encode the states. n bits Johnson code needs n FFs and can represent 2n states.
Different State Encodings
In Lab3: We use Binary Code, One-Hot State Encoding
Different state encodings leads to different circuit implementation, and thus different hardware cost and performance of state machines
State encoding provides another dimension of optimizations
Number of FFsrequired
1000000001100111State7
0100000010010110State6
0010000001010101State5
0001000000110100State4
0000100010001011State3
0000010001001010State2
0000001000101001State1
0000000100011000State0
ONEHOT(8 bits)
TWOHOTBINARYSTATE
853Number of FFsrequired
1000000001100111State7
0100000010010110State6
0010000001010101State5
0001000000110100State4
00001000011State3
0000010001001010State2
0000001000101001State1
0000000100011000State0
TWOHOTBINARYSTATE
Encoding Style
JohnsonCode (4 bits)
GrayCode
(3 bits)
000
3
001
011
010
110
111
101
100
0000
0001
0011
0111
1111
1110
1100
1000
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Vending Machine (Cont.)
present state inputs next state outputQ3 Q2 Q1 Q0 D N D3 D2 D1 D0 open0 0 0 1 0 0 0 0 0 1 0
0 1 0 0 1 0 01 0 0 1 0 0 01 1 - - - - -
0 0 1 0 0 0 0 0 1 0 00 1 0 1 0 0 01 0 1 0 0 0 01 1 - - - - -
0 1 0 0 0 0 0 1 0 0 00 1 1 0 0 0 01 0 1 0 0 0 01 1 - - - - -
1 0 0 0 - - 1 0 0 0 1
D0 = Q0 D’ N’
D1 = Q0 N + Q1 D’ N’
D2 = Q0 D + Q1 N + Q2 D’ N’
D3 = Q1 D + Q2 D + Q2 N + Q3
OPEN = Q3
One-hot encoding
Equivalent Mealy and Moore State Diagrams
Moore machineoutputs associated with state
0¢[0]
10¢[0]
5¢[0]
15¢[1]
N’ D’ + Reset
D
D
N
N+D
N
N’ D’
Reset’
N’ D’
N’ D’
Reset
0¢
10¢
5¢
15¢
(N’ D’ + Reset)/0
D/0
D/1
N/0
N+D/1
N/0
N’ D’/0
Reset’/1
N’ D’/0
N’ D’/0
Reset/0
Mealy machineoutputs associated with transitions
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Mealy Implementation of Vending Machine
0¢
10¢
5¢
15¢
Reset/0
D/0
D/1
N/0
N+D/1
N/0
N’ D’/0
Reset’/1
N’ D’/0
N’ D’/0
Reset/0present state inputs next state output
Q1 Q0 D N D1 D0 open0 0 0 0 0 0 0
0 1 0 1 01 0 1 0 01 1 – – –
0 1 0 0 0 1 00 1 1 0 01 0 1 1 11 1 – – –
1 0 0 0 1 0 00 1 1 1 11 0 1 1 11 1 – – –
1 1 – – 1 1 1
D0 = Q0’N + Q0N’ + Q1N + Q1DD1 = Q1 + D + Q0NOPEN = Q1Q0 + Q1N + Q1D + Q0D
0 0 1 00 0 1 1X X 1 X0 1 1 1
Q1Open
Q0
ND
Mealy Implementation of Vending Machine (Cont.)
D0 = Q0’N + Q0N’ + Q1N + Q1DD1 = Q1 + D + Q0NOPEN = Q1Q0 + Q1N + Q1D + Q0D
make sure OPEN is 0 when reset– by adding AND gate
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Vending machine: Moore to Synch. Mealy
OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change in Moore implementationThis can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delayOPEN.d = (Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'DImplementation now looks like a synchronous Mealy machine
it is common for programmable devices to have FF at end of logic
Vending Machine: Mealy to Synch. Mealy
OPEN.d = Q1Q0 + Q1N + Q1D + Q0D OPEN.d = (Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D
0 0 1 00 0 1 11 0 1 10 1 1 1
Q1Open.d
Q0
ND
0 0 1 00 0 1 1X X 1 X0 1 1 1
Q1Open.d
Q0
ND
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FSM approach => tasks constitute a well-structured list so that All states can be easily enumerated
VHDL codingARCHITECTURE => user defined enumerated data type, containing a list of all possible system states
Combinational Logic
Sequential Logic Clock
Reset
nx_statepr_state
InputOutput
Hardware Description Languages (HDL) and Finite State Machine
Finite State Machine – VHDL (Cont.)LIBRARY ieee;USE ieee.std_logic_1164.all;---------------------------------------------------------------------ENTITY <entity_name> IS
PORT ( input: IN <data_type>;reset, clock: IN STD_LOGIC;output: OUT <data_type>);
END <entity_name>;---------------------------------------------------------------------ARCHITECTURE <arch_name> of <entity_name> IS
TYPE state IS (state0, state1, state2, state3,…);SIGNAL pr_state, nx_state: state:
BEGIN------------- lower section (sequential logic)----------------
PROCESS (reset, clock)BEGIN
IF (reset = ‘1’) THENpr_state <= state0;
ELSEIF (clock’EVENT AND clock=‘1’) THENpr_state <= nx_state;
END IF;END PROCESS;
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Finite State Machine – VHDL (Cont.)------------- Upper section (combinational logic) ---------
PROCESS (input, pr_state)BEGIN
CASE pr_state ISWHEN state0 =>
IF (input = …) THENoutput <= <value>;nx_state <= state1;
ELSE…END IF;
WHEN state1 =>IF (input = …) THEN
output <= <value>;nx_state <= state2;
ELSE…END IF;
WHEN state2 =>IF (input = …) THEN
output <= <value>;nx_state <= state3;
ELSE…END IF;
WHEN OTHERS =>nx_state <= state0;
….END CASE;
END PROCESS;END <arch_name>;
QuartusII Design Entry- Entering VHDL/VerilogLaunch QuartusIICreate a new Project (file->New Project Wizard), the project name (same as ENTITY)
Open the text editor((File -> New, or click on edit icon select VHDL/Verilog)Entering VHDL/Verilog code, save in the extension .vhd or .vCheck for syntax errors. Select Processing-> Analyze current File or click on analysis icon
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QuartusII - CompilationSelect the target device (Assignments -> Devices) To compile VHDL/Verilog Code, select Processing-> Start Compilation, fix all compilation error until successful message window appears
Examine the compilation reports (on the left of figure), check(1) Flow Summary: contain part number, the number of pins used,…etc(2) Resource Usage Summary (fitter->resource section-> resource usage summary)(3) Input/Output Pins (fitter->resource section-> Input pins, fitter-> resource section->output
pins), these two reports show the I/O pin assignments(4) Floorplan View (fitter->Floorplan View), shows layout of the logic cells, which logic cells
were used and how, etc.(5) Analysis and Synthesis Equations (Analysis and Synthesis ->Analysis and Synthesis
Equations)
QuartusII - Simulation
Open Waveform Editor, Select File-> New->Other File -> Vector Waveform File
In order to define the size of waveform,1. Edit -> End Time ( select 500ns, for example)2. Edit -> Grid Size ( select Period = 50ns, duty cycle = 50%)3. Select View -> Fit in Window Note: change default, go to Tools->Options->Waveform
Editor->general4. Add the input and output signals to the waveform window. Click the right mouse button
inside the white area under Name. Select Insert Node or Bus. In the next box, select Node Finder. Make sure that Filter is set to Pins: all. Click on Start, then on >>, and finally OK. The waveforms window contains all all signals in VHDL/Verilog code.
5. Set the values of the input signals. (clk, rst,d,….) To set up the clock signal, select the entire clk line. A setup box will be displayed, choose period = 100 ns
6. For rst, select only the first portion (from 0 to 25 ns), which will cause change from 0 to 1.7. Save the waveform file as *.vwf8. The system is now ready for simulation. Select Processing -> Start Simulation
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QuartusII – State Machine Viewer
The State Machine Viewer provides a high-level graphical representation of the states and state transitions, as well as a state transition table
After running Analysis & Synthesis, you can also view encoding information for the state transitions in the State Machine Viewer.
To view state machine nodes, transitions, and encoding in the State Machine Viewer:
Open Project,.On the Tools menu, click State Machine Viewer.
Or, In the RTL Viewer, in the hierarchy list, expand the design element that contains the state machine you want to view, and then expand the State Machines category to select the specific state machine and view it in the State Machine Viewer.Turn on the Highlight Fan-In and Highlight Fan-Out commands (View menu) to highlight node fan-in and fan-out, respectively.To view the transitions for a state machine, select the state machine in the schematic view and then click the Transitions tab.
To view the encoding for a state machine:Perform Analysis & Synthesis first, Select the state machine in the schematic
view and then click the Encoding tab.
Vending Machine – How to Improve?
Lab assistants demand a newsoda machine for school. You need to design the FSM controller.
All selections are $0.30The machine makes changes!
(Dimes and nickels only.)
Inputs: limit 1 per clockQ - quarter insertedD - dime insertedN - nickel inserted
Outputs: limit 1 per clockDC - dispense canDD - dispense dimeDN - dispense nickel
But, machine still has problem!Can machine select drinks? No !
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FSM States Encoding
Moore Machine Implementation
State Transition Diagram-Not minimized yet
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State Reduction (remove duplication)
Moore State Machine Implementation in VerilogCode of Vendor Machine
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Moore State Machine Implementation in VerilogCode of Vendor Machine (cont.)
Moore State Machine Simulation Result
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Combine Next-State and Output Logic
Mealy Machine Implementation
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Verilog Code for Mealy Machine Implementation
Verilog Code for Mealy Machine Implementation
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Simulation Result of Mealy Machine Implementation
State Encoding in Verilog Code
Binary (Decimal) encoding
parameter IDLE = 0;parameter GOT_5c = 1;parameter GOT_10c = 2;parameter GOT_15c = 3;parameter GOT_20c = 4;parameter GOT_25c = 5;parameter GOT_30c = 6;parameter GOT_35c = 7;parameter GOT_40c = 8;parameter GOT_45c = 9;parameter GOT_50c = 10;parameter RETURN_20c = 11;parameter RETURN_15c = 12;parameter RETURN_10c = 13;parameter RETURN_5c = 14;
One-hot Encoding
parameter IDLE = 16’b0000000000000001;parameter GOT_5c =16’b0000000000000010;parameter GOT_10c=16’b0000000000000100;parameter GOT_15c= ….;parameter GOT_20c= …;parameter GOT_25c= ..;parameter GOT_30c= … ;parameter GOT_35c= …;parameter GOT_40c= ..;parameter GOT_45c= …;parameter GOT_50c= ..;parameter RETURN_20c = ……..;parameter RETURN_15c = ……..;parameter RETURN_10c = ……..;parameter RETURN_5c = ………;
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Lab 3 Assignment
Two types of Finite State MachinesMoore – Outputs are a function of current state onlyMealy – Outputs a function of both the current state and
input function
Lab 3 assignment – please fix the problem in lecture! we need to have capability to select different drinks, and depense the selected drink and changes
We will cover how to fix Glitching in FSM? Timing Requirement in FSM, “String Pattern Recognizer” next week.
Final Exam – Tuesday, March 21, 2006, 9:00AM- 10:30AM, HSS1330
March 15- Oral exam by TA on Lab 4