CSD13381F4 12-V, N-Channel FemtoFET™ MOSFET (Rev. D)
13
D G S 0.60 mm 1.00 mm 0.35 mm Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CSD13381F4 SLPS448D – JULY 2013 – REVISED MAY 2015 CSD13381F4 12 V N-Channel FemtoFET™ MOSFET 1 Features Product Summary 1• Low On-Resistance T A = 25°C TYPICAL VALUE UNIT • Low Q g and Q gd V DS Drain-to-Source Voltage 12 V • Low Threshold Voltage Q g Gate Charge Total (4.5 V) 1060 pC Q gd Gate Charge Gate-to-Drain 140 pC • Ultra-Small Footprint (0402 Case Size) V GS = 1.8 V 310 mΩ – 1.0 mm × 0.6 mm R DS(on) Drain-to-Source On-Resistance V GS = 2.5 V 170 mΩ • Ultra-Low Profile V GS = 4.5 V 140 mΩ – 0.35 mm Height V GS(th) Threshold Voltage 0.85 V • Integrated ESD Protection Diode – Rated >4 kV HBM . Ordering Information (1) – Rated >2 kV CDM Device Qty Media Package Ship • Lead and Halogen Free CSD13381F4 3000 7-Inch Femto (0402) 1.0 mm x Tape and • RoHS Compliant Reel 0.6 mm SMD Lead Less Reel CSD13381F4T 250 (1) For all available packages, see the orderable addendum at 2 Applications the end of the data sheet. • Optimized for Load Switch Applications Absolute Maximum Ratings • Optimized for General Purpose Switching T A = 25°C unless otherwise stated VALUE UNIT Applications V DS Drain-to-Source Voltage 12 V • Single-Cell Battery Applications V GS Gate-to-Source Voltage 8 V • Handheld and Mobile Applications I D Continuous Drain Current, T A = 25°C (1) 2.1 A I DM Pulsed Drain Current, T A = 25°C (2) 7 A 3 Description Continuous Gate Clamp Current 35 This 140 mΩ, 12 V N-channel FemtoFET™ MOSFET I G mA Pulsed Gate Clamp Current (2) 350 technology is designed and optimized to minimize the P D Power Dissipation (1) 500 mW footprint in many handheld and mobile applications. Human Body Model (HBM) 4 kV This technology is capable of replacing standard ESD Rating Charged Device Model (CDM) 2 kV small signal MOSFETs while providing at least a 60% reduction in footprint size. T J , Operating Junction and –55 to 150 °C T stg Storage Temperature Range . Avalanche Energy, single pulse I D = 7.4 A, E AS 2.7 mJ L = 0.1 mH, R G = 25 Ω Typical Part Dimensions (1) Typical R θJA = 90°C/W on 1 inch 2 (6.45 cm 2 ), 2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB. (2) Pulse duration ≤300 μs, duty cycle ≤2% Top View . . . . 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
Transcript of CSD13381F4 12-V, N-Channel FemtoFET™ MOSFET (Rev. D)
D
G S
0.60 mm
1.00 m
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0.35 m
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Product
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Technical
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Tools &
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Support &Community
CSD13381F4SLPS448D –JULY 2013–REVISED MAY 2015
CSD13381F4 12 V N-Channel FemtoFET™ MOSFET1 Features
Product Summary1• Low On-Resistance
TA = 25°C TYPICAL VALUE UNIT• Low Qg and Qgd VDS Drain-to-Source Voltage 12 V• Low Threshold Voltage Qg Gate Charge Total (4.5 V) 1060 pC
Qgd Gate Charge Gate-to-Drain 140 pC• Ultra-Small Footprint (0402 Case Size)VGS = 1.8 V 310 mΩ– 1.0 mm × 0.6 mm
RDS(on) Drain-to-Source On-Resistance VGS = 2.5 V 170 mΩ• Ultra-Low ProfileVGS = 4.5 V 140 mΩ– 0.35 mm Height
VGS(th) Threshold Voltage 0.85 V• Integrated ESD Protection Diode
– Rated >4 kV HBM .Ordering Information(1)– Rated >2 kV CDM
Device Qty Media Package Ship• Lead and Halogen FreeCSD13381F4 3000 7-Inch Femto (0402) 1.0 mm x Tape and• RoHS Compliant Reel 0.6 mm SMD Lead Less ReelCSD13381F4T 250
(1) For all available packages, see the orderable addendum at2 Applicationsthe end of the data sheet.
• Optimized for Load Switch ApplicationsAbsolute Maximum Ratings• Optimized for General Purpose Switching
TA = 25°C unless otherwise stated VALUE UNITApplicationsVDS Drain-to-Source Voltage 12 V• Single-Cell Battery ApplicationsVGS Gate-to-Source Voltage 8 V• Handheld and Mobile ApplicationsID Continuous Drain Current, TA = 25°C(1) 2.1 A
IDM Pulsed Drain Current, TA = 25°C(2) 7 A3 DescriptionContinuous Gate Clamp Current 35This 140 mΩ, 12 V N-channel FemtoFET™ MOSFET IG mAPulsed Gate Clamp Current(2) 350technology is designed and optimized to minimize the
PD Power Dissipation(1) 500 mWfootprint in many handheld and mobile applications.Human Body Model (HBM) 4 kVThis technology is capable of replacing standard ESD
Rating Charged Device Model (CDM) 2 kVsmall signal MOSFETs while providing at least a 60%reduction in footprint size. TJ, Operating Junction and –55 to 150 °CTstg Storage Temperature Range. Avalanche Energy, single pulse ID = 7.4 A,EAS 2.7 mJL = 0.1 mH, RG = 25 Ω
Typical Part Dimensions(1) Typical RθJA = 90°C/W on 1 inch2 (6.45 cm2), 2 oz. (0.071
mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB.(2) Pulse duration ≤300 μs, duty cycle ≤2%
Top View
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1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD13381F4SLPS448D –JULY 2013–REVISED MAY 2015 www.ti.com
Table of Contents6.1 Trademarks ............................................................... 71 Features .................................................................. 16.2 Electrostatic Discharge Caution................................ 72 Applications ........................................................... 16.3 Glossary .................................................................... 73 Description ............................................................. 1
7 Mechanical Data..................................................... 84 Revision History..................................................... 27.1 Mechanical Dimensions ............................................ 85 Specifications......................................................... 37.2 Recommended Minimum PCB Layout...................... 95.1 Electrical Characteristics........................................... 37.3 Recommended Stencil Pattern ................................. 95.2 Thermal Information .................................................. 37.4 CSD13381F4 Embossed Carrier Tape5.3 Typical MOSFET Characteristics.............................. 4 Dimensions .............................................................. 10
6 Device and Documentation Support.................... 7
4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2014) to Revision D Page
• Corrected typo for IGSS Test Condition .................................................................................................................................. 3
Changes from Revision B (February 2014) to Revision C Page
• Corrected timing VDS to read 6 V ........................................................................................................................................... 3
Changes from Revision A (November 2013) to Revision B Page
• Added IG parameter ................................................................................................................................................................ 1• Lowered IDSS limit.................................................................................................................................................................... 3• Lowered IGSS limit ................................................................................................................................................................... 3
Changes from Original (July 2013) to Revision A Page
• Updated device ordering information...................................................................................................................................... 1• Changed test voltage conditions ............................................................................................................................................ 3• Changed Figure 4 Gate Charge graph................................................................................................................................... 5
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5 Specifications
5.1 Electrical Characteristics(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTATIC CHARACTERISTICSBVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 12 VIDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 9.6 V 100 nAIGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 8 V 50 nAVGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 0.65 0.85 1.10 V
VGS = 1.8 V, IDS =0.5 A 310 400 mΩDrain-to-SourceRDS(on) VGS = 2.5 V, IDS =0.5 A 170 225 mΩOn-Resistance
VGS = 4.5 V, IDS = 0.5 A 140 180 mΩgƒs Transconductance VDS = 6 V, IDS = 0.5 A 3.2 SDYNAMIC CHARACTERISTICSCiss Input Capacitance 155 200 pF
VGS = 0 V, VDS = 6 V,Coss Output Capacitance 47 62 pFƒ = 1 MHzCrss Reverse Transfer Capacitance 2.5 3.3 pFRG Series Gate Resistance 23 ΩQg Gate Charge Total (4.5 V) 1060 1400 pCQgd Gate Charge Gate-to-Drain 140 pC
VDS = 6 V, IDS = 0.5 AQgs Gate Charge Gate-to-Source 230 pCQg(th) Gate Charge at Vth 155 pCQoss Output Charge VDS = 6 V, VGS = 0 V 1120 pCtd(on) Turn On Delay Time 3.7 nstr Rise Time 1.5 nsVDS = 6 V, VGS = 4.5 V,
IDS = 0.5 A, RG = 2 Ωtd(off) Turn Off Delay Time 11.0 nstƒ Fall Time 3.8 nsDIODE CHARACTERISTICSVSD Diode Forward Voltage ISD = 0.5 A, VGS = 0 V 0.73 0.9 VQrr Reverse Recovery Charge 1550 pC
VDS= 6 V, IF = 0.5 A, di/dt = 300 A/μstrr Reverse Recovery Time 6 ns
5.2 Thermal Information(TA = 25°C unless otherwise stated)
THERMAL METRIC TYPICAL VALUES UNITJunction-to-Ambient Thermal Resistance (1) 90
RθJA °C/WJunction-to-Ambient Thermal Resistance (2) 250
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.(2) Device mounted on FR4 material with minimum Cu mounting area.
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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1VDS - Drain-to-Source Voltage (V)
I DS -
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ourc
e C
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nt (
A)
VGS =4.5VVGS =2.5V
VGS =1.8V
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I DS -
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ourc
e C
urre
nt (
A)
TC = 125°CTC = 25°CTC = −55°C
VDS = 5V
G001
CSD13381F4SLPS448D –JULY 2013–REVISED MAY 2015 www.ti.com
5.3 Typical MOSFET Characteristics(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
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0.7
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CSD13381F4www.ti.com SLPS448D –JULY 2013–REVISED MAY 2015
Typical MOSFET Characteristics (continued)(TA = 25°C unless otherwise stated)
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage
Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
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0.0
0.5
1.0
1.5
2.0
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3.0
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−50 −25 0 25 50 75 100 125 150 175TA - AmbientTemperature (ºC)
I DS -
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in-
to-
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rce
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Typical RthetaJA =90ºC/W(max Cu)
G001
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0.01 0.1 1 10 50VDS - Drain-to-Source Voltage (V)
I DS -
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ourc
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urre
nt (
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10ms100ms1s
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k A
vala
nche
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) TC = 25ºCTC = 125ºC
G001
CSD13381F4SLPS448D –JULY 2013–REVISED MAY 2015 www.ti.com
Typical MOSFET Characteristics (continued)(TA = 25°C unless otherwise stated)
Figure 10. Maximum Safe Operating Area (SOA) Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 TrademarksFemtoFET is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
6.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
6.3 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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7 Mechanical DataThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Mechanical Dimensions
(1) All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994).(2) This drawing is subject to change without notice.(3) This package is a PB-free solder land design.
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7.2 Recommended Minimum PCB Layout
(1) All dimensions are in millimeters.
7.3 Recommended Stencil Pattern
(1) All dimensions are in millimeters.
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7.4 CSD13381F4 Embossed Carrier Tape Dimensions
(1) Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocketholes.
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
CSD13381F4 PICOST AR
YJC 3 3000 178.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2
CSD13381F4 PICOST AR
YJC 3 3000 180.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2
CSD13381F4T PICOST AR
YJC 3 250 180.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD13381F4 PICOSTAR YJC 3 3000 220.0 220.0 35.0
CSD13381F4 PICOSTAR YJC 3 3000 182.0 182.0 20.0
CSD13381F4T PICOSTAR YJC 3 250 182.0 182.0 20.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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