CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009

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11 Mar 2009 G. Rakness (UCLA) 1 CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009 Wednesday spent replacing Global Trigger crate Started global running Wednesday late afternoon Reached 99.99kHz L1A rate Including CSC, DT, HB FMM errors from CSC FED 754 had to be masked out of the run FIFO overflow from CFEB problem on ME-1/1/7 combined with a specific error-handling deficiency in the DDU firmware To be fixed with DDU firmware upgrade… CSC Track Finder DAQ processes not properly killed by CSC Run Control Put “CSC” Function Manager into Error Trigger Supervisor Cell crashed occasionally Memory leak in Track Finder trigger supervisor cell used up all memory on this machine. Under investigation…

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CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009. Wednesday spent replacing Global Trigger crate Started global running Wednesday late afternoon Reached 99.99kHz L1A rate Including CSC, DT, HB FMM errors from CSC FED 754  had to be masked out of the run - PowerPoint PPT Presentation

Transcript of CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009

Page 1: CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009

11 Mar 2009 G. Rakness (UCLA) 1

CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009

• Wednesday spent replacing Global Trigger crate– Started global running Wednesday late afternoon

• Reached 99.99kHz L1A rate– Including CSC, DT, HB

• FMM errors from CSC FED 754 had to be masked out of the run– FIFO overflow from CFEB problem on ME-1/1/7 combined with a

specific error-handling deficiency in the DDU firmware– To be fixed with DDU firmware upgrade…

• CSC Track Finder– DAQ processes not properly killed by CSC Run Control Put

“CSC” Function Manager into Error– Trigger Supervisor Cell crashed occasionally– Memory leak in Track Finder trigger supervisor cell used up all

memory on this machine. Under investigation…

Page 2: CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009

11 Mar 2009 G. Rakness (UCLA) 2

Online Measurements of L1A Latency from CSC Point of View

L1A latency in MWGR 4 – 5 March 2009 = L1A latency at the end of CRAFT 2008

MWGR

With tmb_lct_cable_delay = 2 AFF to L1A Counter[127] = 0 AFF to L1A Counter[128] = 0 AFF to L1A Counter[129] = 3 AFF to L1A Counter[130] = 13 AFF to L1A Counter[131] = 34 AFF to L1A Counter[132] = 46 AFF to L1A Counter[133] = 4 AFF to L1A Counter[134] = 0 AFF to L1A Counter[135] = 0

average = 131.35

https://cmsdaq.cern.ch/elog/CSC/7818https://cmsdaq.cern.ch/elog/CSC/7062

CRAFT

With tmb_lct_cable_delay = 2 AFF to L1A Counter[127] = 0 AFF to L1A Counter[128] = 0 AFF to L1A Counter[129] = 3 AFF to L1A Counter[130] = 11 AFF to L1A Counter[131] = 38 AFF to L1A Counter[132] = 46 AFF to L1A Counter[133] = 2 AFF to L1A Counter[134] = 0 AFF to L1A Counter[135] = 0

average = 131.33

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11 Mar 2009 G. Rakness (UCLA) 3

HE readout with CSC trigger

https://cmsdaq.cern.ch/elog/Shift/4950

CRAFT

Nov 2008

MWGR

4-5 Mar 2009

https://cmsdaq.cern.ch/elog/CSC/6952

Pawel de Barbaro

Shift of 1-1.5 bx?

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11 Mar 2009 G. Rakness (UCLA) 4

Configuration Database Check• Performed a (nearly) comprehensive

check of the peripheral crate configuration database:– loading values to the database – extracting values from the database

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11 Mar 2009 G. Rakness (UCLA) 5

Peripheral Crate Configuration Procedure1. Load software with configuration values from xml file

(or database)• This is the function we need to check.

2. Write values from software onto the userPROM’s3. Hard Reset

• FPGA loads configuration values from userPROM

4. Check Configuration• Compares expected values (in software) with read values

(from hardware)

Note: if 2) is skipped, and a different set of values is loaded at 1) than what is on the userPROM, then 4)

will fail This is how we check consistency (or not) from one set

of parameters to another

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11 Mar 2009 G. Rakness (UCLA) 6

Configurations used in test• Work our way through 3 different

configurations…1. MWGR = xml config used in MWGR 4 – 5

March2. DB = Database Config ID = 2000001

• Supposed to be identical to MWGR

3. Test = xml• Differs from MWGR xml config by one parameter

per chamber using this ensures that we are not doing a “dummy” check

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11 Mar 2009 G. Rakness (UCLA) 7

Steps1. Load MWGR xml to userPROM2. Check Test xml vs. MWGR xml (on

userPROM) • Many differences expected Shook out some

bugs found in the configuration check function3. Load test xml to userPROM4. Check DB vs. test xml (on userPROM)

• Many differences expected inverse differences as seen in step 2

5. Load userPROM from DB6. check MWGR xml vs. DB (on userPROM)

Conclusion: it works.

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Caveats

• Number of parameters verified to be correct 140

• Parameters not checked include:– Firmware versions for all components

• I.e., did not load incorrect versions to the hardware nor the database

– TMB::ccb_ignore_startstop• Bug in original configuration check

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11 Mar 2009 G. Rakness (UCLA) 9

In other news, the RPC endcap folks have been working on their

analysis…

Following slide presented today at the CRAFT analysis workshop in Torino by C. Carrillo (Uniandes)

Agenda at: http://indico.cern.ch/conferenceDisplay.py?confId=50961

Page 10: CSC’s in the Mid-Week Global Run (MWGR) 4 – 5 March 2009

3/11/0911 Mar 2009 C. Carrillo (Uniandes)G. Rakness (UCLA)

10RP

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Efficiency RPC pad bit by G. Rakness(UCLA)

Run 67539

Run 70195

RE+1/2 RE+1/3

CSC Segment Extrapolation Efficiency for the EndCapCSC Segment Extrapolation Efficiency for the EndCaphttp://webcms.ba.infn.it/~webrpc/efficiency/rereco/70195/indexEndCap.html

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To do • Take a local run

– We have been ~off since the MWGR… this is not a good way to go

• Get the TMB – ALCT loopback software going here at CERN…– Self-frustration for not getting it going

• EMu meeting Sunday – Monday – Bora Akgun is giving the Commissioning

talk… I have been coaching him…