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Computer Systems Architecture
Dr Rob Williams
Course text:
"Computer Systems Architecture - a networ king approach"Edition 2
Prentice Hall, 2006
CSA Ch 01CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 01 - p 1Pearson Education (c) 2006
CSA Rob Williams CSA ch 01 - p 2Pearson Education (c) 2006
1. CSA - the Hardware / Software Interface
Computer Architecture?
h/w s/w Interaction of h/w & s/w
User code
OperatingSystems
Procedures
Hardware
Softwaremyprog.c
WIN32 API
O/S Ker nel
CPU Graphics Sound
Layered hierarchy of s/w on a h/w bed
CSA Rob Williams CSA ch 01 - p 3Pearson Education (c) 2006
1970 1975 1980 1985 1990 1995 2000
108
107
106
105
104
103
102
101
Number oftransistors
Design year10
1
0.1
Circuitline
width µm
1103 DRAM
NEC 64Mb DRAM
1 Mb DRAM
64kb DRAM
256kbb DRAM
Siemens 16Mb DRAM
Intel 4004
Intel PII
Intel 8086Motorola 68000
3µm
0.15µm
0.35µm0.4µm
1.0µm2.0µm
0.1µm ?
Moore’s Law of technological progress
ENTITY decoder8 ISPORT (sel: IN std_logic_vector (2 DOWNTO 0); -- select i/p signals
sig: out std_logic_vector (7 downto 0)); -- eight o/p signalsEND decoder8;
ARCHITECTURE rtl OF decoder8 ISBEGIN
s <= "0000_0001" WHEN (sel = X"0") ELSE"0000_0010" WHEN (sel = X"1") ELSE"0000_0100" WHEN (sel = X"2") ELSE"0000_1000" WHEN (sel = X"3") ELSE"0001_0000" WHEN (sel = X"4") ELSE"0010_0000" WHEN (sel = X"5") ELSE"0100_0000" WHEN (sel = X"6") ELSE"1000_0000";
END rtl;
Moder n h/w development: VHDL
CSA Rob Williams CSA ch 01 - p 4Pearson Education (c) 2006
ControlComputer
System BusTDM Voice Bus
TIC
LICLICLICLIC
Monitor ingter minal
Lineinterface
cards
2.048MbpsTr unk Lines
to other Switches
Telephone Switch showing the embedded computer
Windows’ file browser
CSA Rob Williams CSA ch 01 - p 5Pearson Education (c) 2006
DLL initialization failureC:\WINNT\System32\KERNEL32.DLL
The process is terminating abnormally
The local ATM gives an error message
% cat .cshrcumask 077limit core 0setenv TERM vt100setenv PRINTER lwset prompt = "‘hostname‘ > "set history = 25biff ymesg nalias tt99 ’setenv DISPLAY TT99:0’set path = ( . /usr/ucb /usr/bin/X11 /bin /usr/bin /usr/localset path = ($path /etc /usr/etc /usr/lang /usr/local $home/bin)
Unix set up script or batch file
CSA Rob Williams CSA ch 01 - p 6Pearson Education (c) 2006
WWWNetscape
WANs
email ftpPSTN
archie
hyper text
DARPA/NSF
WIMPinterfacesLANs
CERN
Unix + uucp
Or iginal sources of the WWW
Office Networ kISP
ISP
National/Inter nationalTr unk Line
ISP
Ser ver
Sun WWWSer viceProvider
Dialupmodem
DomesticPC
The Internet
CSA Rob Williams CSA ch 01 - p 7Pearson Education (c) 2006
ATMSwitch
ATMSwitch
EtherSwitch
EtherSwitch
Workstations
100MbpsEther net
Ser ver
Sun
Router Inter netGatewayMail server
Gateway
DB server
Hub
University LAN
Preamble DestinationAddress
SourceAddress Type data payload Error
Check
8 bytes 6 bytes 6 bytes 46 - 1500 bytes 4 bytes
Ether net packet str ucture
Williams R, Computer Systems Architecture, Prentice Hall,
Tanenbaum A S, "Str uctured Computer Organization", Prentice Hall,
Heur ing & Jordon, "Computer Systems Design and Architecture", Addison Wesley
Hamacher, Vranesic & Zaky, "Computer Organization", McGraw Hill
Patterson & Hennessy, "Computer Organization & Design: The Hardware/Software Interface",Morgan Kaufmann
Buchanan W, "PC Interfacing, Communications & Windows Programming", Addison Wesley
CSA Rob Williams CSA ch 01 - p 8Pearson Education (c) 2006
CSA Ch 02CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 02 - p 9Pearson Education (c) 2006
2. CSA - the von Neumann Interitance
Inputdata Process Output
data
All under program control
0010 00000011 10011101 00000001 00100000 00010001 00100011 01001101 00001011 1001
ProgramMemor y
instr uctions CentralProcessor
Unit
Stored program control
Computer Application
Smar t Card Telephone/credit cardMicrocontroller Washing machine controllerGames Console Interactive enter tainmentHome PC Web infor mation browsingWorkstation Design layouts for circuit boardsOffice Server Central filing on local networ kMainframe Corporate DatabaseSupercomputer Flight simulation studies
Common applications of computers
CSA Rob Williams CSA ch 02 - p 10Pearson Education (c) 2006
SemanticGap
from HLL: i = j + k;
to assembler mnemonics: mov EAX,[12011234]add EAX,[12011238]mov [1201123C],EAX
to machine binary: 0010 0000 0011 10010001 0010 0000 00010001 0010 0011 0100
1101 0000 1011 10010001 0010 0000 00010001 0010 0011 1000
0010 0011 1100 00000001 0010 0000 00010001 0010 0011 1100
HLL, assembler & machine code
1. Data Transfer and Manipulation2. Input / Output3. Transfer of Program Control4. Machine Control
Categor ies of machine instructions
CSA Rob Williams CSA ch 02 - p 11Pearson Education (c) 2006
Edit Compile Link Load
RUN
HLLsource
file
Binar yobjectfiles
Librar yfiles
Executablefile
Errors Errors
Phases of a HLL compiler
editCompile Link Build
RUN
Sourcefiles Macros
Objectlibrar ies
Dynamiclibrar ies
Code sharing at different phases
CSA Rob Williams CSA ch 02 - p 12Pearson Education (c) 2006
Mod. 1
Mod. 2
Mod. 3
Mod. 4
Call toSubroutine
Linking code modules
EditAnalysis
DecodeSelect
& Execute
CommandRoutinesHLL
sourcefile
Tokenisedinstr uctionErrors
Edit javaccompiler
javainter preter
Netscapebrowser
Java sourcefile
Javabytecodes
HTML textpage
java applet
Java language interpreters
CSA Rob Williams CSA ch 02 - p 13Pearson Education (c) 2006
weighting1248163264128256512102420484096
1001110101111
4096 + 2048 + 1024 + 512 + 128 + 32 + 16 + 8 + 1 = 7865
weighting0000000001000000101000011001001111101000
7932
0010 x 1111101000 + 0011 x 0001100100 + 1001 x 0000001010 + 0111 x 0000000001 = 100101011101
Binar y to decimal & decimal to binary conversion
1 1 1 1 1 1 0 1--------
2 ) 2 3 9 71 1 9 8
5 9 92 9 91 4 9
7 43 71 8
94210
remainders writtenfrom right to left
resu
lts w
ritte
n do
wn
0 00001 00012 00103 00114 01005 01016 01107 01118 10009 1001A 1010B 1011C 1100D 1101E 1110F 1111
Hex & binar y
CSA Rob Williams CSA ch 02 - p 14Pearson Education (c) 2006
\ b i t s 765 | 000 001 010 011 100 101 110 111\ |
b i t s \ de c | 0 16 32 48 64 80 96 1124321 \ hex | 0 10 20 30 40 50 60 70- - - - - - - - - - - - - - | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -0000 0 0 | NUL DLE SP 0 @ P ‘ p0001 1 1 | SOH DC1 ! 1 A Q a q0010 2 2 | STX DC2 " 2 B R b r0011 3 3 | ETX DC3 # 3 C S c s0100 4 4 | EOT DC4 $ 4 D T d t0101 5 5 | ENQ NAK % 5 E U e u0110 6 6 | ACK SYN & 6 F V f v0111 7 7 | BEL ETB ’ 7 G W g w1000 8 8 | BS CAN ( 8 H X h x1001 9 9 | TAB EM ) 9 I Y i y1010 10 A | LF SUB * : J Z j z1011 11 B | VT ESC + ; K [ k 1100 12 C | FF FS , < L \ l |1101 13 D | CR GS - = M ] m 1110 14 E | SO HOM E . > N ˆ n 1111 15 F | SI NL / ? O _ o DE L
NUL Null DLE Data Link EscapeSOH Start of Heading DC1 Device Control 1STX Start of Text DC2 Device Control 2ETX End of Text DC3 Device Control 3EOT End of transmission DC4 Device Control 4ENQ Enquiry NAK Negative AcknowledgeACK Acknowledge SYN Synchronization characterBEL Bell ETB End of Transmitted BlockBS Back Space CAN CancelHT Horizontal Tab EM End of MediumLF Line Feed SUB SubstituteVT Ver tical Tab ESC EscapeFF For m Feed FS File SeparatorCR Carriage Return GS Group SeparatorSO Shift Out RS Record SeparatorSI Shift In US Unit SeparatorSP Space DEL Delete
http://www.unicode.org
ASCII code table
CSA Rob Williams CSA ch 02 - p 15Pearson Education (c) 2006
#include <stdio.h>
void main() putchar(7);
Ring the bell
char letter;
short count;unsigned int uk_population;long world_population;
float body_weight;double building_weight;long double world_weight;
Data types
AIX OS/2 CDOS PICKCICS PRIMOS CMS RSTOSCP/M RSX/11 MSDOS RTL/11George TDS IDRIS THEISIS UNIX LYNXOS UltrixMINIX VERSADOS MOP VMMSDOS VMS MVS MS WINDOWSMultics XENIX OS-9 Linux
Operating Systems
1. Command line interpreter (CLI), shell script or desktop selections
2. Function calls from within user programs (API)
Access to O/S facilities
CSA Rob Williams CSA ch 02 - p 16Pearson Education (c) 2006
rob[66] stty -icanon min 1 time 0 ; menu_prog
Are you ready to proceed? [ Y / N ] :
Unix unbuffered, nonblocked keyboard
#include <errno.h>#include <stdio.h>#include <sys/termios.h>#include <unistd.h>#define TIMEOUT -1
extern int errno;int sys_nerr;extern char * sys_errlist[];
void setterm(void) struct termios tty;int status;
status = ioctl(0,TCGETS, &tty);tty.c_lflag &= ˜ICANON;tty.c_cc[VTIME] = 0;tty.c_cc[VMIN] = 1;
status = ioctl(0,TCSETS, &tty);if ( status == -1 )
printf("ioctl error \n");perror(sys_errlist[errno]);exit();
CSA Rob Williams CSA ch 02 - p 17Pearson Education (c) 2006
hardware
kernel
dr ivers
CLI
User Applications
Onion layered model for Operating Systems
sh - the original Bourne shell, still popular with administrators for scriptscsh - the C shell, more C-like syntax, and is better for interactive sessionstcsh - Tenex shell, perhaps the most used interactive shell, emacs keyingksh - Kor n shell, normal issue with Hewlett Packard wor kstationsbash - bour ne-again-shell, a free-ware rework of sev eral shells
Unix command shells
CSA Rob Williams CSA ch 02 - p 18Pearson Education (c) 2006
Screen Server
Pr int Ser ver File Server
Client-ser ver computing
Client
Ser ver
RequestMessage Reply
RequestReplies
Request
time
Xter m
atar i@pong [50] xterm &atar i@pong [51] rlogin milly -l rwilliamLast login: Tue Jul 1 09:22:21 sisterrwilliam@milly >
CSA Rob Williams CSA ch 02 - p 19Pearson Education (c) 2006
CSA Ch 03CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 03 - p 20Pearson Education (c) 2006
3. CSA - the Fetch-execute Cycle
Computer
MainMemor y
I/OUnitsCPU
Computer subsystems
Socket 462
PCI Slots
ISA SlotAGP Slot
ChipSet
Sound I/O
ChipSet
VGA
BIOS+
Pentium CPUand Heatsink
Slots forMemor yModules
Cr ystal
Slots forI/O
Expansion Cards ATX Pow erConnector
Ke yboardsocket
MousesocketUSB
socketsLAN
socket
MODEMsocket
Pr interConnector
Hard DiskIDE
Connectors
Floppy diskConnector
CPU FanConnector
LithiumBatter y
Fig 3.2PC ATX Motherboard,showing the locations ofthe CPU, memor y and I/Ocard sockets Motherboard from a PC
CSA Rob Williams CSA ch 03 - p 21Pearson Education (c) 2006
CPU
Interr uptRequest
Main Memory
System Bus
I/O Subsystem
System Clock
Subsystems joined by a bus highway
Bus
Point-to-point vs. bus interconnect schemes
CPU
ControlUnitALU
CPU has two main component parts
CSA Rob Williams CSA ch 03 - p 22Pearson Education (c) 2006
ns µs ms1
1 000 000 0001
1 000 0001
1 000
fetch-execute light human reaction10 ns 300 m/µs 300 ms
logic gate delay tv line scan tv frame5 ns 60 µs 20 ms
SRAM access interr upt hard disk access15 ns 2-20 µs 10 ms
engine spark car engine (3000 rpm)10 µs 20 ms
Comparative speeds
CSA Rob Williams CSA ch 03 - p 23Pearson Education (c) 2006
The Fetch part of the Fetch-Execute Cycle
AX IR
IP
CPU
System Clock
MAR
10111000
00000000
00000001
Main Memory
System Bus
AX IR
IP
CPU
MAR
10111000
00000000
00000001
Main Memory
Addressbus
Instr uctionAddress
AX IR
IP ++
CPU
MAR
10111000
00000000
00000001
Main Memory
Databus
Instr uctionCode
CSA Rob Williams CSA ch 03 - p 24Pearson Education (c) 2006
The execute part of the Fetch-Execute Cycle
AX IR
IP
CPU
MAR
10111000
00000000
00000001
Main Memory
DataAddress
AX IR
IP ++
CPU
MAR
10111000
00000000
00000001
Main Memory
OperandData: 256
CPU activity for a Sun wor kstation
CSA Rob Williams CSA ch 03 - p 25Pearson Education (c) 2006
Data bus - typically 32 bits wide, but will be increased to 64 bits,Address bus - 32 bits wide, but will require more ver y soon,Control bus - about 15 lines for starting and stopping activities.
System bus has three parts
A B C
System Clock
Addr1 Addr2 Addr3Address
Read Read Wr iteR/W
Fetch Execute
Instr Data ResultData
10 ns time-base
Timing of synchronous bus activity
CSA Rob Williams CSA ch 03 - p 26Pearson Education (c) 2006
Addr1 Addr2 Addr3Address
Avalid
Cvalid valid
ALE
Fetch Read Wr iteR/W
Instr Data ResultData
Bok ok ok
DTA10 ns time-base
Timing of asynchronous bus activity
Readinstr uction
Decodeinstr uction
Readoperand
Executeop
Wr iteresult
A SingleInstr uction
Cycle
Timing of multi-phase instructions cycle
CSA Rob Williams CSA ch 03 - p 27Pearson Education (c) 2006
Rober t
1 0 1 1 0 1 1
Musical interference on FM receivers
Clock speed limitationideal pulse real pulse
CSA Rob Williams CSA ch 03 - p 28Pearson Education (c) 2006
Prefetcher
unitExecution
unit
IP
queue
Prefetching instructions
fetch 1 execute 1 fetch 2 execute 2 fetch 3 execute 3 fetch 4 execute 4
fetch 1 fetch 2 fetch 3 fetch 4 fetch 5 fetch 6
execute 1 execute 2 execute 3 execute 4 execute 5 execute 6
Time
Winning margin
fetch 7 fetch 8 fetch 9
Over lapped operations gives greater throughput
16MByte
0000 0000 0000 0000 0000 0000 Bottom
1111 1111 1111 1111 1111 1111 Top
memor ylength
Address Width
memor y width
Address width determines memory lengthCSA Rob Williams CSA ch 03 - p 29Pearson Education (c) 2006
16 bit addresses can access 216, 65536, 64K locations20 bit addresses can access 220, 1048576, 1M locations24 bit addresses can access 224, 16777216, 16M locations32 bit addresses can access 232, 4294967296, 4G locations64 bit addresses can access 264, 4398046511104, 4E locations
dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15bin 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111hex 0 1 2 3 4 5 6 7 8 9 A B C D E F
CSA Rob Williams CSA ch 03 - p 30Pearson Education (c) 2006
Intel Pentium
Motorola 68030
Address Memory Contents In Hex0FE032 0102 0304 0506 0708 090A FBFC FDFE FF00
0FE042 0001 0002 0003 0004 0005 00FE 00FF 0100
0FE052 0101 FFFC FFFD FFFE FFFF 0000 0001 0000
0FE062 0002 0000 0003 0000 0004 0000 0005 0000
0FE072 00FE 0000 00FF 0000 0100 0000 0FFF 0000
0FE082 1000 0000 1001 FFFF FFFF 0000 0A00 0000
0FE092 0000 0020 0000 0000 0000 0000 000F E0C0
b1[0]b2[0] b4[0]
Compare these
Byte ordering: big endian, little endianunsigned char b1[ ] = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 251, 252, 253,
254, 255;unsigned short b2[ ] = 1, 2, 3, 4, 5, 254, 255, 256, 257, 65532,
65533, 65534, 65535;unsigned int b4[ ] = 1, 2, 3, 4, 5, 254, 255, 256, 4095, 4096,
4097, 4294967295;
CSA Rob Williams CSA ch 03 - p 31Pearson Education (c) 2006
Data Bus
ChipSelect
AddressDecoder
R / W
Addressbus
Data Bus
ChipSelect
AddressDecoder
R / W
Addressbus
Parallel data input & output ports
CSA Rob Williams CSA ch 03 - p 32Pearson Education (c) 2006
CSA Ch 04CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 04 - p 33Pearson Education (c) 2006
4. CSA - the Control Unit (CU)
891011121314
1 2 3 4 5 6 7
5v
0v
Inputs CA B A AND B0 0 00 1 01 0 01 1 1
InputsA B A OR B0 0 00 1 11 0 11 1 1
InputsA B A XOR B0 0 00 1 11 0 11 1 0
InputA NOT A0 11 0
AND
AB
C
OR XOR NOT
Basic logic gates with truth tables
111
1
1101
110
0
Detect: 111 Detect: 101 Detect: 010
Using AND for pattern recognition
D X Out0 0 00 1 01 0 01 1 1
DData in
Data Out
XOff/On control line
D X Outd 0 0d 1 d
Using AND as a data valve
CSA Rob Williams CSA ch 04 - p 34Pearson Education (c) 2006
Control DataW X Y Z A B C D Out0 0 0 1 a b c d a0 0 1 0 a b c d b0 1 0 0 a b c d c1 0 0 0 a b c d d
W
X
Y
Z
Data linesA B C D
OutputControl
lines
O = (A AND Z ) OR (B AND Y ) OR (C AND X ) OR (D AND W )
Data selector, 1 from 4
Selector LineY X d c b a0 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0
O = (A AND (X AND Y ) ) OR (B AND (X AND Y ) ) OR (C AND (X AND Y ) ) OR (D AND (X AND Y ) )
2-to-4 line decoder, 1-out-of-4 line selector
CSA Rob Williams CSA ch 04 - p 35Pearson Education (c) 2006
2 Line DecoderY X
InputData lines
D C B A
A1 a
A2 b
A3 c
A4 d
Data
Output
a
b
c
d
A
B
C
D
Output A B C D
O1 = (i3 AND i2 AND i1) OR (i4 AND i3 AND i2) OR (i4 AND i3 AND i2 AND i1)
Data multiplexor, 1 from 4CSA Rob Williams CSA ch 04 - p 36Pearson Education (c) 2006
inputs O1 2 3 40 0 0 0 00 0 0 1 00 0 1 0 10 0 1 1 00 1 0 0 00 1 0 1 10 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 11 1 0 1 11 1 1 0 01 1 1 1 0
i1 i2 i3 i4
O1
O1 = (i3 • i2 • i1) + (i4 • i3 • i2) + (i4 • i3 • i2 • i1)
Sum of Products solution
X Y NAND0 0 10 1 11 0 11 1 0
The 2 input NAND gate
CSA Rob Williams CSA ch 04 - p 37Pearson Education (c) 2006
i1
i2
i3
i4
O1
O2
O3
O4
O5
O6
O7
O8
Programmable Logic Array (PLA)
CSA Rob Williams CSA ch 04 - p 38Pearson Education (c) 2006
Level Crossing Cross Roads
Inputs LightsX Y R A G0 0 1 0 00 1 1 1 01 0 0 0 11 1 0 1 0
Inputs LightsX Y Z R A G r a g
W-E N-S0 0 0 1 0 0 1 0 00 0 1 1 1 0 1 0 00 1 0 0 0 1 1 0 00 1 1 0 1 0 1 0 01 0 0 1 0 0 1 0 01 0 1 1 0 0 1 1 01 1 0 1 0 0 0 0 11 1 1 1 0 0 0 1 0
W E
N
S
EW
X Y
R
A
G
R = X
A = Y
G = X AND Y
X Y Z
R
A
G
r
a
g
W-E
N-S
R = (X AND Y )
A = (X AND Z )
G = (X AND Y AND Z )
r = (X AND Y )
a = (X AND Z )
g = (X AND Y AND Z )
Tr affic light controllers
CSA Rob Williams CSA ch 04 - p 39Pearson Education (c) 2006
Inputs OutputsEnable Select YG
1G
2C B A 0 1 2 3 4 5 6 7
X 1 X X X 1 1 1 1 1 1 1 10 X X X X 1 1 1 1 1 1 1 11 0 0 0 0 0 1 1 1 1 1 1 11 0 0 0 1 1 0 1 1 1 1 1 11 0 0 1 0 1 1 0 1 1 1 1 11 0 0 1 1 1 1 1 0 1 1 1 11 0 1 0 0 1 1 1 1 0 1 1 11 0 1 0 1 1 1 1 1 1 0 1 11 0 1 1 0 1 1 1 1 1 1 0 11 0 1 1 1 1 1 1 1 1 1 1 0
3 to 8
line
decoder
ABC
Y0Y1Y2Y3Y4Y5Y6Y7
G1 G2 G3
Y0
Y1
Y2
Y3
Y4
Y5A
Y6B
Y7C
3 to 8 line decoder
CSA Rob Williams CSA ch 04 - p 40Pearson Education (c) 2006
Inputs LEDsW X Y Z a b c d e f g0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 0 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 1 0 1 1
a
bg
cde
f
a = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR
(W AND X AND Y AND Z )
b = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z )
c = W AND X AND Y AND Z
d = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR
(W AND X AND Y AND Z )
e = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR
(W AND X AND Y AND Z ) OR (W AND X AND Y AND Z )
f = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR
(W AND X AND Y AND Z ) OR (W AND X AND Y AND Z )
g = (W AND X AND Y AND Z ) OR (W AND X AND Y AND Z ) OR
(W AND X AND Y AND Z )
Z Y X W
a
Binar y to 7-segment decoderCSA Rob Williams CSA ch 04 - p 41Pearson Education (c) 2006
READY
DRAIN
HEATDRAIN
FILLSPIN
WASHRINSE
1 rev per12
hr → 2rph →2
3600rps →
11800
Hz →10001800
mHz → 0. 55mHz
Washing machine Finite State Diagram (FSD)
CSA Rob Williams CSA ch 04 - p 42Pearson Education (c) 2006
000
001
010
011
100
101
110
111
READY
FILL
HEAT
WASH
DRAIN
RINSE
DRAIN
SPIN
0 0 0 0 0
1 0 0 0 0
0 1 0 0 0
0 0 0 1 0
0 0 0 0 1
1 0 0 1 0
0 0 0 0 1
0 0 1 0 1
Valve
Open
Heat
On
Motor
F S
Pump
On
Control Lines
IR
1
01
01
01
0Micro
switch
from micro-switch 0
micro-switch 1micro-switch 2
0.55 mHz
Washing machine sequence controller (FSM)
CSA Rob Williams CSA ch 04 - p 43Pearson Education (c) 2006
0 0 0 0 01 0 0 0 00 1 0 0 00 0 0 1 00 0 0 0 11 0 0 1 00 0 0 0 10 0 1 0 1
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
3 bit codefrom micro-switches
Program Counter
Control Store
5 bit
control word
Valve
Open
Heat
On
F S
Motor
Pump
On
Control Lines
0 0 0 0 0
1 0 0 0 0
0 1 0 0 0
0 0 0 1 0
0 0 0 0 1
1 0 0 1 0
0 0 0 0 1
0 0 1 0 1
Control
Store
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
JMP flag
addr select
JMP addr
CounterClock
Reset
temperature
water level high
water level low
JMP load
decoder
Washing machine controller with conditional branching
CSA Rob Williams CSA ch 04 - p 44Pearson Education (c) 2006
ControlLogic
Gate Array
StatusBits
CondnFlags
DecoderBinar yCounter
reset
System Clock
Pre-Decode
Instr uction Register
Addr Gen
0 0 00 0 10 1 00 1 1
0 0 0 0 10 0 0 1 00 0 1 0 00 1 0 0 01 0 0 0 0
dedicatedcontrol signals
inter nal data bus
Hardware logic Control Unit (RISC)
CSA Rob Williams CSA ch 04 - p 45Pearson Education (c) 2006
ControlStore
PROM
AddressGenerator
Logic
IR
CondnFlagsBinar y
Counter
reset
System Clock
Microaddr Reg
Micro IR
0 0 00 0 10 1 00 1 1
dedicatedcontrol signals
inter naldata bus
Microcoded Control Unit (CISC)
CSA Rob Williams CSA ch 04 - p 46Pearson Education (c) 2006
CSA Ch 05CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 05 - p 47Pearson Education (c) 2006
5. CSA - the Arithmetic & Logic Unit (ALU)
(X AND Y ) ≡ (X OR Y )
(X OR Y ) ≡ (X AND Y )
≡
≡
while ( ! dog && ! cat )
plant_flowers( ) ;
while (! (dog || cat ))
plant_flowers( ) ;
De Morgan’s equivalences
ADDX Y C S0 0 0 00 1 0 11 0 0 11 1 1 0
Carr y
X Y
Sum
Carr y
X Y
Sum
Alter native Half Adder (2 inputs) circuitsCSA Rob Williams CSA ch 05 - p 48Pearson Education (c) 2006
Carr y
X Y
Sum
Carr y
X Y
Sum
More Half Adder circuits
1/2Adder
X
YC1
1/2AdderZ
C2
Carr y
SumFull-adder
X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
Full Adder (3 inputs) circuit
CSA Rob Williams CSA ch 05 - p 49
Pearson Education (c) 2006
A
3 2 1 0
B
3 2 1 0
Add0
Add1
Add2
Add3
Cin
Cout S0S1S2S3
C = A + B
C
4 bit parallel adder circuit
CSA Rob Williams CSA ch 05 - p 50
Pearson Education (c) 2006
Negative integers usingTw os Compliment for mat
0 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 01 1 1 11 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 0
+ 7+ 6+ 5+ 4+ 3+ 2+ 1
0- 1- 2- 3- 4- 5- 6- 7- 8
posi
tive
negative
To for m a two’s compliment negative:Take the positive number,invert all the bits,add 1.
A B
31 310 0
31 • • • • • 0
Carr y in
1 - subtract
0 - add
control linesCU
IR
C
32 bit
ALU
(Parallel
Adder)
31 0
ALU with positive and negative capabilityCSA Rob Williams CSA ch 05 - p 51
Pearson Education (c) 2006
Input, xx7 . . . . . x0
x7 . . . . . . . x0Output
Diagonal closed switch patterncontrolled by the CU
No shift in this position
x6 . . . . . x0 0
Input, xx7 . . . . . x0
Output, x <<= 1x5 . . . x0 0 0
Input, xx7 . . . . . . x0
Output, x <<= 2
Input, xx7 . . . . . x0
Output, x >>= 30 0 0 x7 . . x3
Input, xx7 . . . . . x0
Output, ROL x,5
x2 1 0 7 6 5 4x3
Input, xx7 . . . . . x0
Output, ROR x,5
x4 3 2 1 0 7 6x5
Barrel Shifter circuit for Shifts & Rotates
CSA Rob Williams CSA ch 05 - p 52
Pearson Education (c) 2006
1 7 3 1 0 1 0 1 1 0 15 7 x 0 0 1 1 1 0 0 1 x
-------- --------------------1 2 1 1 1 0 1 0 1 1 0 18 6 5 0 0 0 0 0 0 0 0 0-------- 0 0 0 0 0 0 0 09 8 6 1 1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 11 0 1 0 1 1 0 1
0 0 0 0 0 0 0 00 0 0 0 0 0 0 0------------------------------------
1 0 0 1 1 0 1 0 0 0 0 0 1
Integer multiplication by Shift and Add
/* function to multiply two 16 bit positive integersreturning a 32 bit result, using only integer additionand shift operators */
int multiply(int a, int c)
int i;
c = c << 16;
for (i=0; i<16; i++)
if (a & 1) a += c ;a = a >>1;
return a;
CSA Rob Williams CSA ch 05 - p 53Pearson Education (c) 2006
0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1
Test LS bit1
0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0
A
C
0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1
0 0 1 0 1 1 0 1
+0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0
0 0 1 0 1 1 0 1 shift right
0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0
Test LS bit00 0 1 0 1 1 0 1
0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0
0 0 1 0 1 1 0 1
0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0
0 0 1 0 1 1 0 1 shift right
0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0
Test LS bit00 0 1 0 1 1 0 1
0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0
0 0 1 0 1 1 0 1
0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1
0 0 1 0 1 1 0 1 shift right
0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1
if (A & 1)10 0 1 0 1 1 0 1
0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 1
0 0 1 0 1 1 0 1
A += C
0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1
0 0 1 0 1 1 0 1 A = A >>1
0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1
Test LS bit10 0 1 0 1 1 0 1
0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1
0 0 1 0 1 1 0 1
+0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1
0 0 1 0 1 1 0 1 shift right
0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1
Test LS bit10 0 1 0 1 1 0 1
0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1
0 0 1 0 1 1 0 1
+0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0
0 0 1 0 1 1 0 1 shift right
0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0
Test LS bit00 0 1 0 1 1 0 1
0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0
0 0 1 0 1 1 0 1
0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1
0 0 1 0 1 1 0 1 shift right
0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0
Test LS bit00 0 1 0 1 1 0 1
0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0
0 0 1 0 1 1 0 1
0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1
0 0 1 0 1 1 0 1 shift right
Result
8 x 8 multiply using two 16 bit registers
CSA Rob Williams CSA ch 05 - p 54
Pearson Education (c) 2006
Carr y in
control linesCU
C
ALU
A B
CPU Flags
D0D1D2D3D4D5
RegistersD6DataD7
Inter nal CPU Data Bus
Register select
ALU with data registers
CSA Rob Williams CSA ch 05 - p 55
Pearson Education (c) 2006
Output Values, F
S3 - S0 M = 1 M = 0
Logic Arithmetic
Cin = 0 Cin = 1
0 0 0 0 F = A F = A F = A + 1
0 0 0 1 F = A OR B F = A OR B F = (A OR B) + 1
0 0 1 0 F = A AND B F = B OR A F = (A OR A) + 1
0 0 1 1 F = 0 F = − 1 F = 0
0 1 0 0 F = A AND B F = A + (B AND A) F = A + (B AND A) + 1
0 1 0 1 F = B F = (A OR B) + (B AND A) F = (A OR B) + (B AND A) + 1
0 1 1 0 F = A XOR B F = A − B − 1 F = A − B
0 1 1 1 F = B AND A F = B AND A − 1 F = (B + A)
1 0 0 0 F = A OR B F = A + (B AND B) F = A + (A AND B) + 1
1 0 0 1 F = A XOR B F = A + B F = A + B + 1
1 0 1 0 F = B F = (B OR A) + (A AND B) F = (B OR A) + (A AND B) + 1
1 0 1 1 F = A AND B F = (A AND B) − 1 F = (A AND B)
1 1 0 0 F = 1 F = A << 1 F = (A << 1) + 1
1 1 0 1 F = B OR A F = (A OR B) + A F = (A OR B) + A + 1
1 1 1 0 F = A OR B F = A + (B OR A) + A F = (B OR A) + A + 1
1 1 1 1 F = A F = A − 1 F = A
74xx181
A0A1A2A3
B3B2B1B0
F0F1F2F3
Cin
Cout
A=B
Data in Data out
Control
S3S2S1S0 M
Example integer ALU component
CSA Rob Williams CSA ch 05 - p 56
Pearson Education (c) 2006
float net_cost, tot_cost, price;
float vat = 0.175;
int items;
net_cost = price * items;
tot_cost = net_cost + net_cost * vat;
Floats & integers in HLL programming
CSA Rob Williams CSA ch 05 - p 57
Pearson Education (c) 2006
Nor mal Exponential
1234.5625 1.2345625 x 103
-3.3125 -3.3125 x 100
0.065625 6.5625 x 10-2
1234.5625 10011010010.1001 1.00110100101001 x 21010
unnor malized normalized for mat
-3.3125 -11.0101 -1.10101 x 21
0.065625 0.00011 1.1 x 2-4
Mantissa
Exponent
Floating-point numbers, in IEEE 754 32 bit for mat, appear in memory as:
S exponent mantissa
022233031
0 10001001 00110100101001000000000
1 10000000 10101000000000000000000
0 01111011 10000000000000000000000
To manually converting a decimal float into a IEEE binary float:
1. Convert the integer part into binary.2. Convert the fractional part into binary, noting the 1/2, 1/4, 1/8, 1/16 pattern!
... 128 64 32 16 8 4 2 1 • 0.5 0.25 0.125 0.0625 0.03125 ...
3. Normalize by moving the binary point to produce the for mat: 1.something witha positive or negative shift number.
4. Delete the leading 1, and extend the left bits with 0s to give a 23 bit mantissa.5. Add 127 to the shift number to give the 8 bit exponent.
CSA Rob Williams CSA ch 05 - p 58Pearson Education (c) 2006
/* floatit.c - to write a real number into a file for viewing */
#include <stdio.h>
int main( )
FILE *fp;
float f = 231.125;
if (fp = fopen ("float_data", "w"))
fwrite(&f, 4, 1, fp);
;
return 0;
rob@olveston [78] cc floatit.c -o floatit
rob@olveston [79] floatit
rob@olveston [80] od -x float_data
0000000 4367 2000
0000004
rob@olveston [129] od -f float_data
0000000 2.3112500e+02
0000004
rob@olveston [130]
CSA Rob Williams CSA ch 05 - p 59Pearson Education (c) 2006
The hex value 43 67 20 00 is the 32 bit floating-point number :
0 100 0011 0110 0111 0010 0000 0000 0000| | |
sign 8 bit 23 bits of the 24bitbit exponent mantissa
in 127offsetformat
The range and precision of the var ious floating-point for mats are as follows:
Range Precision32 bit 8 bit 24 bit, (1 in 16 x 106)
64 bit 11 bit 53 bit, (1 in 8 x 1015)
128 bit 15 bit 64 bit, (1 in 16 x 1018)
CSA Rob Williams CSA ch 05 - p 60Pearson Education (c) 2006
CSA Ch 06CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 06 - p 61Pearson Education (c) 2006
6. CSA - the Memory
1 bit data out
1 bit data in
Stored data out
1
0
1
0
Wr ite-once, Read-many memor y cell
S
R
_Q
Q
Qt St Rt Q t+1 Q t+1
0 0 0 1 00 0 1 1 00 1 0 0 10 1 1 illegal1 0 0 0 11 0 1 1 01 1 0 0 11 1 1 illegal
S
R
Q
_Q
S-RLatch
S
R
_Q
Q
S-R Latch, 1 bit static memory
CSA Rob Williams CSA ch 06 - p 62Pearson Education (c) 2006
10 kOhm
5v
Cat flapswipe switch
0 V
LED
200 Ohm
5v
INOUT
Cat IN-OUT indicator using an S-R latch
RAM 10ns DRAM, Dynamic Random Access Memory - read & write, random access1ns SRAM, Static Random Access Memory
ROM Read Only Memory, factor y wr itten - random accessPROM Programmable ROM, writable, but only once.EPROM 150ns UV erasable PROM, with a window in the package to admit the UV photonsEEPROM electrically erasable PROM, useful for semi-permanent programmingFLASH similar to EEPROM, reprogrammable, non-volatile ROM
M5L27512K-2
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 Gnd
5v A14 A13 A0 A9 A1 OE A10 CS D7 D6 D5 D4 D3
MT46V128M8TG-6T
3v D0 3v D1 0 D2 3v D3 0 3v WE CAS RAS CS B0 B1 A10 A0 A1 A2 A3 3v
D7 0 D6 3v D5 0 D4 3v 0 DQ Clk Cke A11 A9 A8 A7 A6 A5 A4 0
Mitsubishi, M5L27512K-2 Micron, MT46V128M8TG-6T64 kbytes EPROM 128 Mbyte Dynamic RAM200 nsec access time 167 MHz operation, 6 ns access
Different types of memory
CSA Rob Williams CSA ch 06 - p 63Pearson Education (c) 2006
Flip-Flop
Flip-Flop
Flip-Flop
Flip-Flop
Clock, ff/2 f/4 f/8
f
f/2
f/4
f/8
Clock
Flip-flops used for frequency division
CSA Rob Williams CSA ch 06 - p 64Pearson Education (c) 2006
Word line
Bit line
Tr ansistor switch
1 bit storage capacitor~ 20 fF
64MbitMemor y Cell
array
Bit line drivers
Multiplexor
Column decoder
Row
deco
der
RowAddress
latch
RASCAS
Wr ite Enable
Address
Address
Row number Column number
031
015 015
CAS cycleRAS cycle
Row AccessRAS
Column AccessCAS
Row C0 C1 C2 C3Addr
D0 D1 D2 D3Data
60 ns access time
Dynamic ram (DRAM) single cell and memory arrayCSA Rob Williams CSA ch 06 - p 65Pearson Education (c) 2006
16 MByte, 50ns access, 32 bit, 72 pin SIMM card
64 MByte, 100 MHz clock, 64 bit, 168 pin DIMM card
72 pin SIMM and 168 pin DIMM, DRAM Modules
Remember : 220 = 1M, so: 222 = 4M
CSA Rob Williams CSA ch 06 - p 66Pearson Education (c) 2006
1 Vss 43 Vss 85 Vss 127Vss2 DQO 44 NC 86 DQ32 128CKEO3 DQ1 45 CS2 87 DQ33 129NC4 D02 46 DQM2 88 DQ34 130DQM65 DQ3 47 DQM3 89 DQ35 131DQM76 Vcc 48 NC 90 Vcc 132NC7 DQ4 49 Vcc 91 DQ36 133Vcc8 DQ5 50 NC 92 DQ37 134NC9 DQ6 51 NC 93 DQ38 135NC10 DQ7 52 NC 94 DQ39 136 NC11 DQ8 53 NC 95 DQ40 137 NC12 Vss 54 Vss 96 Vss 138 Vss13 DQ9 55 DQ16 97 DQ41 139 DQ4814 DQ10 56 DQ17 98 DQ42 140 DQ4915 DQ11 57 DQ18 99 DQ43 141 DQ5016 D012 58 DQ19 100 DQ44 142 DQ5117 DQ13 59 Vcc 101 DQ45 143 Vcc18 VCC 60 DQ20 102 Vcc 144 DQ5219 DQ14 61 NC 103 DQ46 145 NC20 DQ15 62 NC 104 DQ47 146 NC21 NC 63 NC 105 NC 147 NC22 NC 64 Vss 106 NC 148 Vss23 Vss 65 DQ21 107 VSS 149 DQ5324 NC 66 DQ22 108 NC 150 D05425 NC 67 D023 109 NC 151 DQ5526 Vcc 68 Vss 110 VCC 152 Vss27 WE 69 DQ24 111CAS 153 DQ5628 DQM0 70 DQ25 112 DQM4 154 DQ5729 DQM1 71 DQ26 113 DQM5 155 DQ5830 CSO 72 DQ27 114 NC 156 D05931 NC 73 Vcc 115RAS 157 Vcc32 Vss 74 DQ28 116 VSS 158 DQ6033 AO 75 DQ29 117Al 159DQ6134 A2 76 DQ30 118 A3 160 DQ6235 A4 77 DQ31 119 A5 161 DQ6336 A6 78 Vss 120 A7 162 Vss37 A8 79 CLK2 121 A9 163 CLK338 A10/AP 80 NC 122 BAO 164 NC39 BA1 81 NC 123 All 165 SAO40 Vcc 82 SDA 124 VCC 166 SA141 Vcc 83 SCL 125 CLK1 167 SA242 CLKO 84 Vcc 126NC 168Vcc
Pin assignments for a 168 pin SDRAM DIMM
CSA Rob Williams CSA ch 06 - p 67Pearson Education (c) 2006
A0-31
CPU
A0-31
4 GBSRAM
Ideal memory configuration
Device Size Pins 32 bit address bus Address range
PROM1 1MB 20 0000 0000 xxxx ++++ ++++ ++++ ++++ ++++ 0000 0000 - 000F FFFFRAM1 16MB 24 0000 0001 ++++ ++++ ++++ ++++ ++++ ++++ 0100 0000 - 01FF FFFFRAM2 16MB 24 0000 0010 ++++ ++++ ++++ ++++ ++++ ++++ 0200 0000 - 02FF FFFFRAM3 16MB 24 0000 0011 ++++ ++++ ++++ ++++ ++++ ++++ 0300 0000 - 03FF FFFFRAM4 16MB 24 0000 0100 ++++ ++++ ++++ ++++ ++++ ++++ 0400 0000 - 04FF FFFF
+ address line used directly for internal selectionx line ignored, indicates partial (degenerate) addressimg0 must be 0 for chip selection1 must be 1 for chip selection
Memor y map for a small computer system
A0-31
CPU
A24A25A26
100011010001000
A27A28A29A30A31
c/sc/sc/sc/sc/s
3 line Decoder(1 out of 8 selector)
A0-23
RAM416MB
System Bus A0 - A31, D0 - D7
A0-23
RAM316MB
A0-23
RAM216MB
A0-23
RAM116MB
A0-19
PROM11MB
Memor y Schematic showing the Decoding CircuitCSA Rob Williams CSA ch 06 - p 68Pearson Education (c) 2006
RAM116MB
RAM216MB
RAM316MB
RAM416MB
Page 25516MB
PROM11MB
0000 0000 0000 0000 0000 0000 0000 0000 00 00 00 00
0000 0001 0000 0000 0000 0000 0000 0000 01 00 00 00
0000 0010 0000 0000 0000 0000 0000 0000 02 00 00 00
0000 0011 0000 0000 0000 0000 0000 0000 03 00 00 00
0000 0100 0000 0000 0000 0000 0000 0000 04 00 00 00
0000 0000 0000 1111 1111 1111 1111 1111 00 0F FF FF
0000 0001 1111 1111 1111 1111 1111 1111 01 FF FF FF
0000 0010 1111 1111 1111 1111 1111 1111 02 FF FF FF
0000 0011 1111 1111 1111 1111 1111 1111 03 FF FF FF
0000 0100 1111 1111 1111 1111 1111 1111 04 FF FF FF
Binar y Hexadecimal
A31 - A24 address linesfor memor y decoder
4 Gbyte Memory Organisation
CSA Rob Williams CSA ch 06 - p 69Pearson Education (c) 2006
Motherboard
CPU
I/O Dev1
I/O Dev2
I/O Dev3
RAM2
RAM1
ROM
00 0000 -01 FFFF
10 0000 -2F FFFF
80 0000 -80 002F
MEMORY MAP
Memor y layout for a Memory-mapped I/O Scheme
or i.b #bmask,OP_reg ; logical OR a mask to set a port bitandi.b #$f7,OP_reg ; logical AND a mask to clear a port bitasl.b (a5) ; shift port bits left for display pur posesnot.b OP_reg ; shift port bits right for display pur posesbclr #1,OP_reg ; test a port bit and leave it 0bset #2, (a2) ; test a port bit and leave it 1
CSA Rob Williams CSA ch 06 - p 70Pearson Education (c) 2006
I/O Dev1
I/O Dev2
I/O Dev3
RAM2
RAM1
ROM
00 0000 -01 FFFF
10 0000 -2F FFFF
MEMORY MAP I/O PORT MAP
380 -400
Memor y and I/O layout for an I/O-mapped scheme
CSA Rob Williams CSA ch 06 - p 71Pearson Education (c) 2006
CSA Ch 07CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 07 - p 72Pearson Education (c) 2006
7. CSA - the Intel Pentium
123456789101112131415161718192021222324252627282930313233343536
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z AA BB CC DD EE FF GG HH II JJ KK
FG13054USA HF
Socket 478 for the Pentium 4
Slot A processor card with a Pentium II
CSA Rob Williams CSA ch 07 - p 73Pearson Education (c) 2006
Bus Interface
ControlUnit
CPU Registers
vpipe upipedecode decode
Prefetchbuffers
Level ID cache8kBytes
TLB
MMUAddr Trans
MMUAddr Trans
Level ICode cache
8kbytesTLB
Floatingpoint
pipeline
BTB
BPL
MicrocodeROM
Pentium subsystems schematic
CSA Rob Williams CSA ch 07 - p 74Pearson Education (c) 2006
Name ProcessorP24T 486 Pentium OverDr ive, 63 or 83MHz, Socket 3P54C Clossic Pentium 75-200MHz, Socket 517, 3.3vP55C Pentium NWX 166-266MHz, Socket 7, 2.8vP54CTB Pentium MMX OverDr ive 125+, Socket 517, 3.3vTillomook Mobile Pentium MMX 0.25 µm, 166-266MHz, 1.8vP6 Pentium Pro, Socket 8Klamath Original Pentium II, 0.35 µm, Slot-IDeschutes Pentium 11, 0.25 µm, Slot 1, 256 Kbyte LII cacheCovington Celeron PII, Slot-I, with no L2 cacheMendocino Celeron, PII with 28 Kbyte L2 cache on dieDixon Mobile Pentium IIPE, 256 Kbyte on-die L2 cacheKatmai Pentium III, PII with SSE instructionsWillamette Pentium III, on-die L2Tanner Pentium 111 XeonCascades PIll, 0.18 µm, on-die L2Merced P7, First IA-64 processor, on-die 12, 0.18 µmMcKinley 1 GHz, Improved Merced, IA-64, 0.18 µm, copper interconnectsFoster Improved PIII, IA-32Madison Improved McKinley, IA-64, 0.13 µm
CSA Rob Williams CSA ch 07 - p 75Pearson Education (c) 2006
AH AL EAXBH BL EBXCH CL ECXDH DL EDX
SI ESIDI EDIBP EBP
IP EIPSP ESP
Flags EFlags
CSSSDSESFSGS
CSDCRSSDCRDSDCRESDCRFSDCRGSDCR
TSS base address TSS limit TRTSS selectorLDT base address LDT limit LDTRLDT selectorIDT base address IDT limit IDTRGDT base address GDT limit GDTR
CR0CR1
Page Fault Service Routine CR2Page Dir Base Reg CR3
31 015
31 019 015 063 019205152
Access Base Address Limit
31 012
i80x86/Pentium CPU Register Set
CSA Rob Williams CSA ch 07 - p 76Pearson Education (c) 2006
MOV EAX,1234H ; load constant value 4660 into 32 bit accumulatorINC EAX ; add 1 to accumulator valueCMP AL,’Q’ ; compare the ASCII Q with the LS byte value in EAXMOV maxval,EAX ; store accumulator value to memory var iable "maxval"DIV DX ; divide accumulator by value in 16 bit D register
EBX: Base registers hold addresses pointing to data structures, such as arrays inmemor y.
LEA EBX,marks ; initialize EBX with address of the var iable "marks"MOV AL,[EBX] ; get byte value into AL using EBX as a memory pointerADD EAX,EBX ; add 32 bits from EBX into accumulatorMOV EAX,table[BX] ; take 32 bit value from the "table" array using
the value in BX as the array index
ECX: The Count register has a special role as a counter in loops or bit shiftingoperations.
MOV ECX,100 ; initialize ECX as the FOR loop index. . . . .
for1: ;symbolic address label. . . . .LOOP for1 ; decrement ECX, test for zero, JMP back if non-zero
EDX: The Data register can be involved during input/output data transfers or whenexecuting integer multiplication and division. Otherwise it is generally available forholding var iables.
IN AL,DX ; input byte value from port, with 16 bit port address in DXMUL DX ; multiply A by value in D
ESI: Source Index register is a pointer for string or array operations within the DataSegment.
LEA ESI,dtable ; initialize SI with memory address of var iable "dtable"MOV AX,[EBX+ESI] ; get word using Base address and Index register
EDI: Destination Index register is a pointer for string or array operations within theData Segment.
MOV [EDI],[ESI] ; moves a 32 bit word from source to destination locations in memory
CSA Rob Williams CSA ch 07 - p 77Pearson Education (c) 2006
EBP: The Stack Base Pointer register is used as the stack frame pointer to supportHLL procedure operations. It is taken as an offset within the Stack Segment.
ENTER 16 ; saves EBP on stack, copies ESP into EBP, and subtracts 16 from ESP
EIP: The Instruction Pointer (Program Counter) holds the offset address of the nextinstr uction within the current Code Segment.
JMP errors ; forces a new address into EIP
ESP: The Stack Pointer holds the offset address of the next item available on thestack within the current Stack Segment.
CALL subdo ; call a subroutine (subdo), storing return address on stackPUSH EAX ; save 32bit value in accumulator on stack
EFLAG: Flag Register contains CPU status flags, implicated in all conditionalinstr uctions.
JGE back1 ; tests sign flag for conditional jumpLOOP backagin ; tests zero flag for loop exit condition
CS - GS: These 16 bit Segment Selector registers were originally introduced toexpand the addressing range of the i8086 processor while maintaining a 16 bit IP.The Segment Register is added to the EIP register to for m a 32 bit address.
CSDCR - GSDCR: 64 bit Code Segment Descriptor Cache Register holds thecurrent Code Segment Descriptor, which includes: Base address, size Limit andAccess permissions. The Segment Descriptor is obtained from either the Global orLocal Descriptor Tables.
TR: The Task Register holds the 16 bit segment selector, the 32 bit base address,the 16 bit size limit and the descriptor attributes for the current task. It references aTSS descriptor in the Global Descriptor Table (GDT). When a task switch occurs,the Task Register is automatically reloaded.
IDTR: The 48bit Interrupt Descriptor Table Register holds the base address andsize limit of the current Interrupt Vector Table (IVT).
GDTR: The Global Descriptor Table Register holds the segment descriptors whichpoint to universally available segments and to the tables holding the LocalDescr iptors.
LDTR: Each task can use a Local Descriptor Table in addition to the GlobalCSA Rob Williams CSA ch 07 - p 78Pearson Education (c) 2006
Descr iptor Table. This register indicates which entry in the Local SegmentDescr iptor Table to use.
CR3: This Control Register points to the directory table for the Paging Unit.
CR2: This Control Register points to the routine which handles page faults whichoccur when the CPU attempts to access an item at an address which is located ona non-resident memory page. The service routine will instigate the disk operation tobr ing the page back into main memory from disk.
CSA Rob Williams CSA ch 07 - p 79Pearson Education (c) 2006
Flags AB CD EH L
SPPC
7 015
i8080 CPU Register Set from 1975
1. data movement (copying)2. data input/output operations3. data manipulation4. transfer of control5. machine supervision
Classes of CPU instructions
MOV copies data from location to location, register or memory
LEA load effective address
CALL calls to a subroutine
RET return from a subroutine
PUSH push an item onto the stack, possibly as a subroutine parameter
POP pop an item off the stack
INC/DEC increment or decrement
ADD arithmetic integer addition
SUB arithmetic subtraction for 2s complement integers
CMP compare 2 values, a subtract with no result, only setting flags
AND/OR/XOR logical operators
TEST bit testing
JZ conditional jump
LOOP implements a FOR loop by decrementing the CX register
ENTER sets up a subroutine (procedure) stack frame
LEAVE cleans up a stack frame on exit from a subroutine
JMP a dreaded jump instruction
INT software interrupt to get into an operating system routine
CSA Rob Williams CSA ch 07 - p 80Pearson Education (c) 2006
1. the action or operation of the instruction,2. the "victims" or operands involved,3. where the result is to go.
Prefix
0 - 3 bytes
Opcode D W
1 - 2 bytes
OperandMOD REG R/M
0 - 1 bytes
S I B
0 - 1 bytes
Displacement /Immediate Data
0, 1, 2 or 8 bytes
2EH
3EH
36H
26H
64H
65H
66H
B8H
F0H
F3H
CSEG
DSEG
SSEG
ESEG
FSEG
GSEG
32bit mode
16bit mode
Lock
REP
00
01
10
11
Memor y
Memor y+d8
Mem+d32/d16
Register
0 REG is source
1 REG is destination
000
001
010
011
100
101
110
111
W=0
AL
CL
DL
BL
AH
CH
DH
BH
W=1
AX
CX
DX
BX
SP
BP
SI
DI
R/M
000
001
010
011
100
101
110
111
MOD=00
(BX+SI)
(BX+DI)
(BP+SI)
(BP+DI)
(SI)
(DI)
direct
(BX)
MOD=01
(BX+SI+d8)
(BX+DI+d8)
(BP+SI+d8)
(BP+DI+d8)
(SI+d8)
(DI+d8)
(BP+d8)
(BX+d8)
MOD=10
(BX+SI+d16)
(BX+DI+d16)
(BP+SI+d16)
(BP+DI+d16)
(SI+d16)
(DI+d16)
(BP+d16)
(BX+d16)
EAX ECX EDX EBX ESP ESI EDI
00
08
10
18
20
28
30
38
01
09
11
19
21
29
31
39
02
0A
12
1A
22
2A
32
3A
03
0B
13
1B
23
2B
33
3B
04
0C
14
1C
24
2C
34
3C
05
0D
15
1D
25
2D
35
3D
06
0E
16
1E
26
2E
36
3E
07
0F
17
1F
27
2F
37
3F
[EAX]
[ECX]
[EDX]
[EBX]
[EBP]
[ESI]
[EDI]
d8 - a byte of data
d16 - a 2 byte word
Pentium instruction code fields
CSA Rob Williams CSA ch 07 - p 81Pearson Education (c) 2006
03 C3 ADD AX,BX_____________________________________0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1- - - - - - - - - - - - | | - - - - - - - - - - - - -
ADD op | Wo r d | AX BXDe s t | | |
Re g-Reg | |mo d e | |
de s t i na t i on sou r ce
66 B8 00 00 00 00 00 00 12 00 MOV EAX,12H____________________________________________________________________________0 1 1 0 0 1 1 0 1 0 1 1 1 0 0 0 0000 0000 0000 0000 0000 0000 0001 0010- - - - - - - - - - - - - - - - - - - - - - | - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -32b i t prefix MOV op Word AX imm ed i a te da ta
3C 71 CMP AL,’q’__________________________________0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 1- - - - - - - - - - - - - | - - - - - - - - - - - - - - - -
CM P A op By te Imm ed i a te da ta31
ID VIP VI AC VM R N IOP O D I T S Z A P C
0
ID identification flag for CPUID availability
VIP vir tual interr upt pending
VI vir tual interr upt active
AC alignment check
VM vir tual 8086 mode active
RFR resume task after breakpoint interrupt
NT nested task
IOPL i/o privilege level
O ar ithmetic overflow error
D direction of accessing string arrays
IE exter nal interr upt enable
T trap, single step debugging, generates an INT #1 after each instruction
S sign, MS bit value
Z zero, result being zero
A auxiliar y carr y, used by BCD arithmetic on 4 LS bits
P par ity, operand status
C carr y, indicates an arithmetic carry or borrow result
CPU status flag register
CSA Rob Williams CSA ch 07 - p 82Pearson Education (c) 2006
CMP AL,’q’
JZ end
.
.
.
.
.
.
.
.
.
ZCPU EFLAG
Register
CMP sets the Z flag
JZ tests the Z flag
Data Register Direct
MOV EAX,EBX+++ +++
Immediate Operand (IP indirect)
MOV EAX,1234++++
Memor y Direct
MOV EAX,[var1] The assembler distinguishes 1234 from [1234]++++++
Address Register Direct
LEA EBX,var1++++
Register Indirect
MOV EAX,[EBX]+++++
Indexed Register Indirect with displacement
MOV EAX,[table+EBP+ESI]+++++++++++++++
MOV EAX,table[ESI]++++++++++
CSA Rob Williams CSA ch 07 - p 83Pearson Education (c) 2006
Prefetcher
unitControlInstr uctions
Decoder logicBranch Detector
PC
prefetchbuffer
decoderstage 1
operandread
executestoreresult
IntegerALU
Data
JMP ADD - - -
NOP JMP ADD - -
NOP NOP JMP ADD -
NOP NOP NOP JMP ADD
NOP NOP NOP NOP JMP
AND NOP NOP NOP NOP
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
System Clock
Fetch Decode1 Readin Execute Wr iteback
Parallelization by pipelined operation
CSA Rob Williams CSA ch 07 - p 84Pearson Education (c) 2006
8kBData Cache
8kBCode Cache
LI
From Main Memory
U-pipedecoder
V-pipeF/Point
CSA Rob Williams CSA ch 07 - p 85Pearson Education (c) 2006
Editor Windowwith source codebreakpoint mark
and IP index mar k
CPU Registers
Output Window
Memor y Windowwith hex dump
of memory
Debugger tool-bar RMB click here
MS VC++ Developer Studio debugger screen
CSA Rob Williams CSA ch 07 - p 86Pearson Education (c) 2006
/* demo of assembler within a C prog*/#include <stdio.h>#include <stdlib.h>
int main (void)char format[] = "Hello World\n" //declare variables in C
__asm ;switch to inline assemblermov ecx,10 ;initialize loop counter
Lj: push ecx ;loop count index saved on stacklea eax,formatpush eax ;address of string, stack parametercall printf ;use library code subroutineadd esp,4 ;clean 4 byte parameter off stackpop ecx ;restore loop counter ready for testloop Lj ;dec ECX, jmp back IF NZ
;back to Creturn 0;
[F1] HELP[F4] go to next error[ˆ F5] run the program[F7] build executable code[ˆ F7] compile only[F9] set breakpoint[F10] single step (over funtions)[F11] single step into functions[ALT][TAB] toggled windows backwards/forwards
CSA Rob Williams CSA ch 07 - p 87Pearson Education (c) 2006
1. CPU registers2. Program memor y with labels and disassembled mnemonics3. Data memory with ASCII decode table4. Output screen for your program under test5. Stack, but only for the return addresses.
Debug x
DisassemblyDisplay
StackDisplay
Memor yDisplay
RegistersDisplay
Variables
Watch
Quick Watch
Restar t
debuggerStop
debuggerBreak
executionShow
instr uction
Step into
Step over
Step out of
Run to
cursor
Debug Toolbar in VC++ Dev Studio
CSA Rob Williams CSA ch 07 - p 88Pearson Education (c) 2006
ˆ [ESC] open the Start Menu on the Taskbar. You can the nopen applications[Tab] on the desktop, this switches between desktop, Taskbar and Start menu
If you already have the Start menu, [Tab] switches between Applications.Alt [F4] ter minate current application
This can also terminate Windows if you are on the desktop!Alt [Tab] switch to next windowShift Alt [Tab]switch to preceding window[ESC] this sometimes cancels the previous action[F1] display the On-line Help for applicatioonsShift [F1] context sensitive help[F2] If an icon is highlighted you can change its name[F3] get Find
Ke yboard Shortcuts for Windows
CSA Rob Williams CSA ch 07 - p 89Pearson Education (c) 2006
CSA Ch 8CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 8 - p 90Pearson Education (c) 2006
8. CSA - Subroutines
.
.
.average(&maths);.
.
.average(&english);
.
.
.
average( ) ...
1
2retur n 1
retur n 2
Main Program
Subroutine?
.
.
.average(&maths);.
.
.average(&english);
.
.
.
average( ) ...
1
2retur n 1
retur n 2
Program A
DLLSubroutine
?
.
.
.average(&ages);.
.
.average(&taxes);
.
.
.
3
4retur n 3
retur n 4
Program B
The "where to return to?" problem
.
.
.average(&m);.
.
.
.
.
.
average( ) ...
.
.
.
call
retur n
Main Program Subroutine
ret addr
Stack area
EIP
callret
The Stack solution
CSA Rob Williams CSA ch 8 - p 91Pearson Education (c) 2006
ESP EAX
EIPCPU
Stack
MainMemor y
System Bus
System stack in main memory, SP register in CPU
CSA Rob Williams CSA ch 8 - p 92Pearson Education (c) 2006
#include <stdio.h>#define NCLASS 10
int maths_scores[NCLASS];int tech_scores[NCLASS];
float average(int x, int * y) int i;float av;for (i=0; i<x; i++)
av += *y++ ;return av /= x;
void main( void) int i;
. . . . .
pr intf("Average of maths = %3.1f\n", average( NCLASS, maths_scores));. . . . .
pr intf("Average of technology = %3.1f\n", average( NCLASS, tech_scores));. . . . . .
Stack growingdownwardsin memory
ESP
EAX EBX
PUSH POP
StackPUSH EAX ;push 32bit word in A onto stackCALL printf ;do somethingPOP EBX ;pop the 32bit word from stack
Stack operation
CSA Rob Williams CSA ch 8 - p 93Pearson Education (c) 2006
ADD ESP,4 ;scrub a longword off the stack
SUB ESP,256 ;open up 256 bytes of space on stack
1. to save the return address dur ing PROCEDURE calls2. to pass parameters into PROCEDURES3. to allocate Local Variable storage space (stack frame)4. as temporar y scratch-pad storage for register values
Uses of the system stack
CSA Rob Williams CSA ch 8 - p 94Pearson Education (c) 2006
setting up the stack frame
<-- clear ing down the stack frame
Disassembled C program with stack operations
CSA Rob Williams CSA ch 8 - p 95Pearson Education (c) 2006
Stackgrowing
stac
kar
ea
Stack Growing73 10 40 00 retur n address0A 00 00 00 NCLASS30 5A 41 00 maths_scores
CSA Rob Williams CSA ch 8 - p 96Pearson Education (c) 2006
params 1
ret add 1ESP
params 1
ret add 1EBP 1EBP
loc vars
ESP
params 1
ret add 1EBP 1
loc vars
params 2
ret add 2EBP 2EBP
loc vars
ESP
params 1
ret add 1EBP 1EBP
loc vars
ESP
params 1ESP
EBP
0000 0000
FFFF FFFF
Stackgrows
Mainprogramsets up
parametersand returnaddress
subr tn 1installslocal
variables
callssubr tn 2
callssubr tn 1
retur nsMain
programretur ns
stac
kfra
me
1
stac
kfra
me
2
02 00 00 00 space for av - current Head of Stack80 31 41 00 space for i80 FF 12 00 old EBP value
Stack Growing
Subroutine calls with stack frame data
CSA Rob Williams CSA ch 8 - p 97Pearson Education (c) 2006
#include <stdio.h>
char* getname(void) char nstring[25];
printf("Please type your name: ");gets( nstring);putchar(’\n’);
return nstring; //SERIOUS ERROR IN THIS PROGRAM
int main(void) char* myname;myname = getname();printf("%s\n", myname);
return 0;
Spot the error here!
.
.
.add EAX,3);.
.
.mov eax,10;
.
.
.
ser ial_isr:...
IRETretur n
Main Program
Interr uptSer viceRoutine
Interr uptarr ives
Interr upt Ser vice Routines (ISR) ash/w triggered subroutines
call filter1 lea esi,filter1• • • •call [esi]
Late bindingCSA Rob Williams CSA ch 8 - p 98Pearson Education (c) 2006
CSA Ch 09CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 09 - p 99Pearson Education (c) 2006
9. CSA - Simple I/O
CPU
Interr uptRequest
Main Memory
System Bus
I/O Subsystem
System Clock
I/O subsystem
1. Dedicated and Per iodic polling2. Interrupt dr iven3. Direct Memory Access (DMA)
Different Input/Output Techniques
CSA Rob Williams CSA ch 09 - p 100Pearson Education (c) 2006
Hardware
HAL
O/S Routines
HLLlibrar y
User Code
Software Access to Hardware
1. Command Registers2. Status Registers3. Data Registers
Categor ies of Per ipheral chip register
CSA Rob Williams CSA ch 09 - p 101Pearson Education (c) 2006
Data Sheet (page 3) for a Harris 82C55AParallel Por t I/O Chip
3
Functional Description
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interfacethe 82C55A to the system data bus. Data is transmitted orreceived by the buffer upon execution of input or outputinstructions by the CPU. Control words and status informa-tion are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal andexternal transfers of both Data and Control or Status words.It accepts inputs from the CPU Address and Control bussesand in turn, issues commands to both of the Control Groups.
(CS) Chip Select. A “low” on this input pin enables thecommuncation between the 82C55A and the CPU.
(RD) Read. A “low” on this input pin enables 82C55A to sendthe data or status information to the CPU on the data bus. Inessence, it allows the CPU to “read from” the 82C55A.
(WR) Write. A “low” on this input pin enables the CPU towrite data or control words into the 82C55A.
(A0 and A1) Port Select 0 and Port Select 1. These inputsignals, in conjunction with the RD and WR inputs, controlthe selection of one of the three ports or the control wordregister. They are normally connected to the least significantbits of the address bus (A0 and A1).
(RESET) Reset. A “high” on this input initializes the controlregister to 9Bh and all ports (A, B, C) are set to the inputmode. “Bus hold” devices internal to the 82C55A will holdthe I/O port inputs to a logic “1” state with a maximum holdcurrent of 400µA.
Group A and Group B Controls
The functional configuration of each port is programmed bythe systems software. In essence, the CPU “outputs” a con-trol word to the 82C55A. The control word containsinformation such as “mode”, “bit set”, “bit reset”, etc., that ini-tializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts“commands” from the Read/Write Control logic, receives“control words” from the internal data bus and issues theproper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read asshown in the “Basic Operation” table. Figure 4 shows thecontrol word format for both Read and Write operations.When the control word is read, bit D7 will always be a logic“1”, as this implies control word mode information.
82C55A BASIC OPERATION
A1 A0 RD WR CSINPUT OPERATION
(READ)
0 0 0 1 0 Port A → Data Bus
0 1 0 1 0 Port B → Data Bus
1 0 0 1 0 Port C → Data Bus
1 1 0 1 0 Control Word → Data Bus
OUTPUT OPERATION(WRITE)
0 0 1 0 0 Data Bus → Port A
0 1 1 0 0 Data Bus → Port B
1 0 1 0 0 Data Bus → Port C
1 1 1 0 0 Data Bus → Control
DISABLE FUNCTION
X X X X 1 Data Bus → Three-State
X X 1 1 0 Data Bus → Three-State
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,READ/WRITE, GROUP A & B CONTROL LOGICFUNCTIONS
GROUP APORT A
(8)
GROUP APORT CUPPER
(4)
GROUP BPORT CLOWER
(4)
GROUP BPORT B
(8)
GROUP BCONTROL
GROUP ACONTROL
DATA
READWRITE
CONTROLLOGIC
RDWRA1A0
RESET
CS
D7-D0
POWERSUPPLIES
+5VGND
BI-DIRECTIONALDATA BUS
I/OPA7-
I/OPC7-
I/OPC3-
I/OPB7-
BUFFERBUS
PB0
PC0
PC4
PA0
8-BITINTERNALDATA BUS
82C55A
CSA Rob Williams CSA ch 09 - p 102Pearson Education (c) 2006
Mode 0 - basic byte-wide input and output portsMode 1 - bytes passed by strobed (asynchronous) handshakeMode 2 - tri-state bus action
D0D1D2D3D4D5D6D7 Control Register
C0 - C3: 1 - input, 0 - output
B0 - B7: 1 - input, 0 - output
Mode: 0 - basic, 1 - strobed
C4 - C7: 1 - input, 0 - output
A0 - A7: 1 - input, 0 - output
Mode: 00 - basic, 01 - strobed, 10 - bus
1 - set port modes
Control Register for the 8255 PIO
Alter native I/O or Memory mapping
// Win-98. Initializes 8255 at 0x1f3: Port A IN; B OUT; C OUT
outp((short)0x1F3, 0x90); // init 8255 cmnd reg
Initialization using C
CSA Rob Williams CSA ch 09 - p 103Pearson Education (c) 2006
CPU
Interr upt Request
A0-A19
PROM Memory
System Bus
D0-D7A0-A1
data regs
command reg
status reg
I/OSubsystem
I/O C/S
C/SRAM
A21-A23
Memor y decoder
0
7
Accessing Registers in Memory-mapped I/O
AddressDevice Size Pins Address bus Address range
PROM1 1MB 20 000x ++++ ++++ ++++ ++++ ++++ 00 0000 - 0F FFFFRAM1 2MB 21 001+ ++++ ++++ ++++ ++++ ++++ 20 0000 - 3F FFFFRAM2 2MB 21 010+ ++++ ++++ ++++ ++++ ++++ 40 0000 - 5F FFFFRAM3 2MB 21 011+ ++++ ++++ ++++ ++++ ++++ 60 0000 - 7F FFFFI/O 4B 2 111x xxxx xxxx xxxx xxxx xx++ E0 0000 - E0 0003
E0 0004 - E0 0007aliases E0 0008 - E0 000B
E0 000C - E0 000F. . .
CSA Rob Williams CSA ch 09 - p 104Pearson Education (c) 2006
Polling LoopRxRDY
LOOP: IN AX,RXSTATUS ;read status portTEST AL,RXRDY ;test device statusJZ LOOP ;if no data go back again
DATIN: IN AX,RXDATA ;get Rx data & clear RXRDY flagOR AL,AL ;test for end markerJZ COMPLETE ;jmp out if finishedMOV [DI],AL ;save character in data bufferINC DIJMP LOOP ;back for more input
COMPLETE: .... ;character string input complete
do while (!(*(BYTE*)RXSTATUS & RXRDY)) ;/* wait for data */
while (*pch++ = *(BYTE*)RXDATA) ; /* check for a NULL */
Polled I/O in ASM & C
Dedicatedspin polling
Inter mittanttimed polling
CSA Rob Williams CSA ch 09 - p 105Pearson Education (c) 2006
System buses operate at 500 Mbyte/secBlocks of characters can be moved at100 Mbyte/secEther net transfers data at 10 Mbytes/secTelephone call needs 8 Kbyte/secSer ial lines frequently run at 1 Kbyte/secEpson printers operate at 100 byte/secKe yboards send at 4 byte/sec
Relative device speeds
CSA Rob Williams CSA ch 09 - p 106Pearson Education (c) 2006
/* io.h 68k header file with h/w definitions */
/* messages */#define PAPER_OUT -1#define DE_SELECT -2#define YES 0#define NO -1#define OK 0
/* address, offsets and setting for M68681 DUART */#define DUART 0XFFFF80 /*base address*/#define ACR 9 /*aux control reg */#define CRA 5 /*command reg A */#define MRA 1 /*mode reg A */#define CSRA 3 /*clock select A */#define SRA 3 /*status reg A */#define RBA 7 /*rx reg A*/#define TBA 7 /*tx reg A */#define RXRDY 1 /*bit mask for rx ready bit */#define TXRDY 4 /*bit mask for tx ready bit */
/*Settings for the Motorola M68230 Parallel Interface TimerThese only deal with mode 0.0, and for ports B and CNo details about the timer.
*/
/* PI/T offsets and adresses, PIT registers are all on odd addresses */#define PIT 0Xffff40 /*address of PI/T */#define BCR 0Xf /*offset for port B cntrl Reg*/#define BDDR 7 /*offset for B data direction*/#define BDR 0X13 /*offset port B data reg */#define CDR 0X19 /*offset port C data reg */
/* Parallel port settings masks and modes */#define MODE0 0X20 /* mode 0.0, 2X buff i/p, single buff o/p */#define MODE01X 0X80 /* mode 0.1X, unlatch i/p, 1X buff o/p */#define OUT 0XFF /* all bits output: 0 - i/p, 1 - o/p*/#define STROBE_MINUS 0X28 /* strobe printer -ve */#define STROBE_PLUS 0x20 /* strobe printer +ve */#define PRINT_ST 1 /* paper out pin 00000001 */#define PAPER_ST 2 /* paper out pin 00000010 */#define SELECT_ST 4 /* selected pin 00000100 */
CSA Rob Williams CSA ch 09 - p 107Pearson Education (c) 2006
/*Initialization and data transfer for 68k SBC */
#include "io.h"
/* set up Mc68681 DUART serial port A only */void dinit()
register char *p;register int i;
p = (char *)DUART;*(p+ACR) = 128; /* set baud rate */*(p+CRA) = 16; /* reset Rx */*(p+MRA) = 19; /* no modem, no PARITY, 8 bits */*(p+MRA) = 7; /* no ECHO, no modem cntrl, 1 STOP */*(p+CRA) = 5; /* enable Rx & Tx */*(p+CSRA)= 187; /* Rx & Tx at 9600 */
p = ( char *) PIT; /* set to base address of PI/T */*(p + BCR ) = MODE0; /* mode 0.0 */*(p + BDDR ) = OUT;
for(i=0; i != 1000;i++) ;/* init delay*/
/* set up 68230 PIT for print out on port B */void pinit()
char *p;p = ( char *) PIT; /* set to base address of PI/T */*(p + BCR ) = MODE0; /* mode 0.0 */*(p + BDDR ) = OUT;
/* get char from serial port A returns character */char get()
register char *p;
p = (char *)DUART;while ( !( *(p+SRA) & RXRDY )) ; /* block here */return *(p+RBA);
/* put character c to serial port A */void put( char c)
register char *p;
p = (char *)DUART;while ( !( *(p+SRA) & TXRDY )) ; /* block here */*(p+TBA) = c;
/* put string to serial port A using put routine */void puts(char* p)
while( *p )put(*p++);
put(’\n’); Continues
CSA Rob Williams CSA ch 09 - p 108Pearson Education (c) 2006
/*put character to parallel port */int print(int c)
register char * p ;
p = ( char *) PIT;while ( *(p + CDR) & PRINT_ST )
if ( !( *(p + CDR) & PAPER_ST) )return (PAPER_OUT) ;
if ( !( *(p + CDR) & SELECT_ST) )return ( DE_SELECT);
*(p + BDR) = c; /*send data */*(p + BCR) = STROBE_MINUS;/* strobe positive */*(p + BCR) = STROBE_PLUS;/* strobe negative */return OK ;
CSA Rob Williams CSA ch 09 - p 109Pearson Education (c) 2006
Brr BrrBrr Brr!
TelephonicInterr uptions
CPU Interr upt Request
Main Memory
System Bus
I/O A I/O B I/O C
CPUInterr upt Request
PIC
Main Memory
System Bus
I/O A I/O B I/O C
Alter native interr upt arrangements
CSA Rob Williams CSA ch 09 - p 110Pearson Education (c) 2006
PIC 2
IRQ8IRQ9
IRQ10IRQ11IRQ12IRQ13IRQ14IRQ15
PIC 1
IRQ0IRQ1
IRQ3IRQ4IRQ5IRQ6IRQ7
to CPUinterr upt
Int Function SourceNumber77 Hard Disk2 IRQ1576 Hard Disk1 IRQ1475 8087 IRQ1374 PS/2 Mouse IRQ1273 Soundcard IRQ1172 Networ k IRQ1071 Redirected IRQ270 RTC IRQ8. . . . . . . . . . .
18 BIOS/TOD INT17 BIOS/softboot INT16 BIOS/print INT15 BIOS/KBD INT14 BIOS/comms INT13 BIOS/disk INT12 BIOS/msize INT11 BIOS/check INT10 BIOS/Video INT0F LPT1: IRQ70E FDC IRQ60D SoundCard IRQ50C COM1: IRQ40B COM2: IRQ30A ---- IRQ209 KBD: IRQ108 System Timer IRQ0070605 Screen dump to printer04 Numeric Overflow03 Breakpoint02 NMI, Po wer fail01 Single Step Trace00 Integer Divide Error
Part of the PC Interrupt Vector Table (IVT)
CSA Rob Williams CSA ch 09 - p 111Pearson Education (c) 2006
Displaying PC IRQs using Windows NT
CSA Rob Williams CSA ch 09 - p 112Pearson Education (c) 2006
CPU
Interr uptrequest
PICIVR table
Memor y
main()
isr
IVT
I/O chip
IVR
Locating the Interrupt Service Routine
1. I/O data transfer request2. Software TRAP (SVC)3. Machine Failure4. Real-time Tick5. Run-time Software Error6. System Reset or Watchdog
Possible Sources of Interrupts
CSA Rob Williams CSA ch 09 - p 113Pearson Education (c) 2006
Imposing access controls using interrupts
SystemPr ivilegedfacilities
Interr upt request
UserPr ivilege
mouseactivity
Interr upts per second
CSA Rob Williams CSA ch 09 - p 114Pearson Education (c) 2006
Data Var iablesin Memory
990msecs
59secs
59mins
01hrs
msecs++
?
msecs=0secs++
?
secs = 0mins++
?
mins = 0hrs++
?
hrs = 0
rte
ISR Interr uptrequest
Display secs
Display mins
Display hrs
Display Routines
Hours Mins Secs
Shared data corruption problem
1.disable interrupts2. serialise the access3. use a semaphore
Cr itical region protection
CSA Rob Williams CSA ch 09 - p 115Pearson Education (c) 2006
Data Var iablesin Memory
990msecs
59secs
59mins
01hrs
?
tickF=0msecs++
?
msecs=0secs++
?
secs = 0mins++
?
mins = 0hrs++
?
hrs = 0
Display secs
Display mins
Display hrs
No tick
N
N
N
N
N
tickF++
ISR
Interr uptrequest
Tick Flag
Ser ialized access to shared data
CSA Rob Williams CSA ch 09 - p 116Pearson Education (c) 2006
UART
Tx data
Rx data
RxISR
TxISR
Rx Interruptrequest
Tx Interruptrequest
Tr ansmitData Buffer
ReceiveData Buffer
RxDev
Dr iver
TxDev
Dr iver
getc( )
putc( )
UserApplication
Operating system managed I/O
CPU
Main Memory
System Bus
I/O Subsystem source
destination
count
DMA Controller
data
Using DMA to Transfer Data
Channel Function Width0 DRAM refresh 8 bits1 SoundBlaster 8 bits2 Floppy Drive34 cascaded to second DMA controller5 SoundBlaster 16 bits67
CSA Rob Williams CSA ch 09 - p 117Pearson Education (c) 2006
Designation of the PC DMA channels
Input
Process
Output
1 2 3
1 2 3
1 2 3
Input
Process
Output
1 2 3
1 2 3
1 2 3
time
The importance of overlapping operations
#include <stdio.h>
int main(void) int answer;
do printf("please enter a single letter: ");answer = getchar();putchar(’\n’);printf("%c\n",answer); while (answer != ’E’);
return 0;
Problems with keyboard input
CSA Rob Williams CSA ch 09 - p 118Pearson Education (c) 2006
please enter a single letter: AA
please enter a single letter:
please enter a single letter: BB
please enter a single letter:
please enter a single letter:
?
?
please enter a single letter: A
41please enter a single letter:0aplease enter a single letter: B
42please enter a single letter:0aplease enter a single letter:
CR
CR
A
B
Ke y codes in hex
#include <stdio.h>
int main(void) int answer;
do printf("please enter a single letter: ");answer = getchar();getchar( );putchar(’\n’);printf("%c\n",answer); while (answer != ’E’);
return 0;
scanf("%c%*c", &answer);CSA Rob Williams CSA ch 09 - p 119Pearson Education (c) 2006
CSA Ch 10CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 10 - p 120Pearson Education (c) 2006
10. CSA - Serial Communications
data - compression and coding schemes, quantitytiming - synchronization of rx with tx: frequency and phasesignaling- error handling, flow control, and routing
Three key issues for communication
Tx Rx
100µs 50µs
Receiver must sample near the middle of an incoming bit
CSA Rob Williams CSA ch 10 - p 121Pearson Education (c) 2006
wr ite data bit to line
sample data now
Tx Clock
Rx Clock
Data
Clock drift problems for asynchronous receivers
SYN - special flag Byte to assist receiver with Byte-level synching.only used when the channel is operating in Synchronous mode
SOH - Start of a message headerSTX - Start of message text blockETX - End of message text block. Messages can be split into multiple blocks.EOT - End of message transmission
Parity Bits - simple to apply, not ver y secureBlock Checksums- simple to apply, not ver y helpfulPolynomial Division- more complex, better security
Error Detection and Correction Techiques
CSA Rob Williams CSA ch 10 - p 122Pearson Education (c) 2006
XOR00000000 000000001 100000010 100000011 000000100 100000101 000000110 000000111 100001000 100001001 000001010 000001011 100001100 0
etc
1
1
0
1
0
1
0
1
Parity bit
Dat
a w
ord
Using XOR gates to compute parity
Data Par ity is Computed New Par ityto be and appended Tr ansmit valuesent to make EVEN computed
for transmission and compared
0110_0111 0110_0111 1 No errors 0110_0111 1
Error ↓0111_0110 0111_0110 1 0111_1110 1 0111_1110 0
Errors↓ ↓0111_0100 0111_0100 0 0111_1101 0 0110_0101 0
no errordetected
errordetected
no errordetected !
Error detection using single appended parity bit
CSA Rob Williams CSA ch 10 - p 123Pearson Education (c) 2006
p1 p2
p3
d1 d2
d3d4
p1 = d 1 XOR d 3 XOR d 4p2 = d 2 XOR d 3 XOR d 4p3 = d 1 XOR d 2 XOR d 4
Tr iple Par ity Bit Assignment
8 7 6 5 4 3 2 1p4 p3 p2 p1P d4 d3 d2 P d1 P P
Assigning Par ity Bits to Longer Words
p 1 2 3 4 5 6 7 82p 2 4 8 16 32 64 128 256d 0 1 4 11 26 57 120 247
4d-3p
Parity bits
Data bits
d = 2p − (p + 1)
Data and parity bits to achieve single error correction
[ 1 0 1 0 1 0 0 ] x = [ 0 0 1 ]1111000
1100110
1010101
giving [ 1 0 1 0 1 0 1 ] for transmission
7 6 5 4 3 2 1d d d p d p p So p3 = 0, p2 = 0, and p1 = 1
Calculating a 4d-3p Syndrome (Transmitter)
CSA Rob Williams CSA ch 10 - p 124Pearson Education (c) 2006
[ 1 0 0 0 1 0 1 ] x = [ 1 0 1 ]↓ error here
1111000
1100110
1010101
The 4d-3p syndrome (receiver) with 1 bit error
No Single Double
error error error
p0 agrees error agrees
Syndrome 0 nonzero nonzero
-> error confused
Single error correction, double error detectionby multiple parity
CSA Rob Williams CSA ch 10 - p 125
Pearson Education (c) 2006
Type
2 bytes
Length
2 bytes
Address
6 bytes
Data
< 256 bytes
Checksum
2 bytes
Motorola S-Record for mat with trailing checksum
S0 03 0000 FC
S2 24 010400 46FC26002E7C000808006100005E610000826100033C46FC270023FC00010678 6B
S2 24 010420 000C011023FC00010678000C011423FC00010678000C011823FC00010678000C 6D
S2 24 010440 011C610003A4303C271053406600FFFC46FC21006100057A4E4B000000004E75 3B
. . . . . . .
S2 24 012200 0968584F4878004C4EB900010928584F206EFFFC524810BC0004602248790001 7D
S2 24 012220 21CA4EB900010968584F487800484EB900010928584F206EFFFC524842104E5E 84
S2 08 012240 4E750000 D1
S8 04 000000 FB
Example Fragment of a Motorola S Record For mat File
08 + 01 + 22 + 40 + 4E + 75 + 00 + 00 = 12Eforget the 1 as overflow, leaving 2E ( 0010 1110 )invert the bits 1101 0001 ( D1 ) THE CHECKSUM !
CSA Rob Williams CSA ch 10 - p 126Pearson Education (c) 2006
1 1 1 0 0 1 1 1 1 0______________ _______________
1 0 1 | 1 1 0 0 1 0 0 1 0 1 |1 1 0 0 1 1 01 0 1 1 0 1----- -----
1 1 0 1 1 01 0 1 1 0 1----- -----
1 1 1 1 1 11 0 1 1 0 1----- -----
1 0 0 1 0 11 0 1 1 0 1----- -----
0 0 0 -> indicatesno errors
Sender Receiver
1 0 = Remainderto send
Calc. of a CRC at sender and receiver for data item 110011. All error bursts of 16 bits or less,2. All odd numbers of bits in error,3. 99.998% of all error bursts of any length.
CRC Generation using Shift Registers and XOR gates
CSA Rob Williams CSA ch 10 - p 127Pearson Education (c) 2006
Echo backHardware Control lines, RTS/CTSSoftware Control Codes, ˆS/ˆQFr ame-based Handshake Codes, ACK/NAK
Flow control techniques
hardware handshake
Rx and Tx data Rx and Tx data
CTS RTS
RTS CTS
software handshake
Xon / Xoff
control
RS232 flow control techniques
Ser ial links dedicated route, no addressing neededLAN broadcast transmission, receiver does the identificationWAN selective routing can be dynamically changed
Data routing methods for serial communications
Idle / marklogic 1 / -9v
Star t lsb msbParityStop
space / logic 0+9v
RS232 voltages representing ASCII ’1’ (31H)
CSA Rob Williams CSA ch 10 - p 128Pearson Education (c) 2006
DCE ( 9 pin D-type) IBM COM1 Modem Por t
→ 2 Rx Data← 3 Tx Data← 4 DTR Data Terminal Ready--- 5 Ear th
← 7 RTS Ready to Send→ 8 CTS Clear to Send
159 6
Socket Number ing
RS232 9-way D-type Pin Functions (COM1 & COM2)
Setting COM1 port Parameters with Hyperter minal
CSA Rob Williams CSA ch 10 - p 129Pearson Education (c) 2006
/* Transmitter.c */#include <stdio.h>
int main(void)FILE *dp;int c;
if ((dp = fopen("COM2", "w"))==NULL)
printf("fail to open COM port\n");return 1;
while ((c=getch()) != EOF)fputc( c, dp);fflush(dp);return 0;
===============================================
/* Receiver.c */#include <stdio.h>
int main(void)FILE *dp;int c;
if ((dp = fopen("COM2", "r"))==NULL)
printf("fail to open COM port\n");return 1;
while ((c= fgetc(dp)) != EOF)putch( c);return 0;
Exchanging messages across an RS232 link on a PC
CSA Rob Williams CSA ch 10 - p 130Pearson Education (c) 2006
PentiumCPU PIC
IRQ 4
ReceiveTr ansmit
RS232 Serial link
16550UART
Attaching a UART, ser ial line interface
CSA Rob Williams CSA ch 10 - p 131Pearson Education (c) 2006
/* Filetrans.c */#include <stdio.h>#include <conio.h>#define CNTRLZ 0x1A
int main(void) FILE * fpFILE * dp;int c;
if ((fp=fopen("C:\TEMP\text.dat", "rt"))==NULL)
printf("fail to open data file\n");return 1;
if ((dp = fopen("COM2", "wt")) == NULL)
printf("fail to open COM port\n");return 1;
while ((c = fgetc(fp )) != EOF)fputc( c, dp);fputc(CNTRLZ, dp);fflush(dp);fclose(fp);
/* Filereceive.c */#include <stdio.h>#include <conio.h>#define CNTRLZ 0x1A
int main(void) FILE *fp;FILE *dp;int c;
if ((fp=fopen("C:\TEMP\text.dat", "w"))==NULL)
printf("fail to open data file\n");return 1;
if ((dp = fopen("COM2", "r")) == NULL)
printf("fail to open COM port\n");return 1;
while ((c= fgetc(dp)) != CNTRLZ)fputc( c, fp);fflush(fp);fclose(fp);return 0;
Slow inter-PC file transfers vis COM2CSA Rob Williams CSA ch 10 - p 132Pearson Education (c) 2006
#include <stdio.h>#include <conio.h>#include <windows.h>#include <winbase.h>HANDLE hCom;char inpacket[16], outpacket[16];BOOL fSuccess;////////////////////////////////////////////////////// Initializes PC COM2 port to non-blocking mode//void initcomm(void)COMMTIMEOUTS noblock;DCB dcb;
hCom=CreateFile("COM2", GENERIC_READ | GENERIC_WRITE,0, NULL, OPEN_EXISTING, 0, NULL );
if (hCom == INVALID_HANDLE_VALUE) dwError = GetLastError();printf("INVALID_HANDLE_VALUE()");
fSuccess = GetCommTimeouts(hCom, &noblock);
noblock.ReadTotalTimeoutConstant = 1;noblock.ReadTotalTimeoutMultiplier = MAXDWORD;noblock.ReadIntervalTimeout = MAXDWORD;
fSuccess = SetCommTimeouts(hCom, &noblock);
fSuccess = GetCommState(hCom, &dcb);if(!fSuccess) printf("GetCommState Error!");dcb.BaudRate = 9600;dcb.ByteSize = 7;dcb.fParity = TRUE;dcb.Parity = EVENPARITY;dcb.StopBits = TWOSTOPBITS;dcb.fRtsControl = RTS_CONTROL_HANDSHAKE;dcb.fOutxCtsFlow = TRUE;
fSuccess = SetCommState(hCom, &dcb);if(!fSuccess) printf("SetCommState Error!");else printf("Comm port set OK!0);
Continues
CSA Rob Williams CSA ch 10 - p 133Pearson Education (c) 2006
//////////////////////////////////////////////////// Reads COM2, single character// IF !char on COM2 return 0, ELSE return ASCII char//char readcomm()
char item;int ni;
fSuccess = ReadFile( hCom,&item,1,&ni,NULL
);if (ni >0 ) return item;else return 0;
//////////////////////////////////////////////////// tests and reads keyboard// IF !char on kbd return 0, ELSE return ASCII char//char readkbd()if (kbhit() ) return _getch();else return 0;
Using COM2 in Non-blocking Mode
CSA Rob Williams CSA ch 10 - p 134Pearson Education (c) 2006
Mouse ball
Y roller
X roller
Optical disksensors
IR emitterand sensor
Optical disk direction and speed sensing
Mouse UART
MouseButtons
X Y
-6v, Txdata+6v, RTS
Rxdata
1200kHz Crystal
X & Y wheels
Arrangement for a PC Serial Mouse with UART
Ser ial por tSdio
Sclk
Oscillator
Sensor& DSP
Po wer onreset
LEDdr ive
Qua
drat
ure
outp
utXBYA
XA
YB
Volta
ge re
gula
tor
Desk top
LED light sourceSensor array
& DSP
Optical mouse image sensor DSP
CSA Rob Williams CSA ch 10 - p 135Pearson Education (c) 2006
hardware issuesplugs & sockets don’t fit: 25/9 pin, sockets/pinsTx and Rx pins confused - crossed vs uncrossed leaddifferent plug configurationsincorrect wiring of h/w flow controls (CTS/RTS)reversed internal IDC ribbon cablesincorrectly assembled IDC ribbon cablesincorrectly installed interface card (IRQ, dma, port no.)ser ial por t hardware not initialized
incompatible transmission for matsASCII vs EBCDIC or Unicodeline speed setting: 1200, 2400, 9600 bpserror checks: odd/even/none parityASCII char length: 7 vs 8 bitsnumber of stop bitsuser defined packet lengthsCR-LF line terminator differences in filestab vs multiple SP differencesWord Processor control characters (Word)EOF problems
flow control failureCTS input uncontrolled by receiverRTS/CTS talking to XON/XOFFinter mediate buffers on end-to-end flow controlunread echo characters on serial linesRAM buffer threshold problems
software problemssending/receiving data through wrong channelincorrect device driver installeduninstalled device driver
Tips and hints on serial connection failure
CSA Rob Williams CSA ch 10 - p 136Pearson Education (c) 2006
Control - used by the root hub to pass on configuration instructions and datato the devices, especially used during the initialization period.
Isochronous - timed data transfers for devices with real-time data streams.Bulk - simple non-time sensitiveInterr upt - USB is not an interrupt system, it depends on timed polling from
the hub to pick up data, such as keyboard input.
host
USB devices
Hub
1H
ub 2
Hub
3
Hub
4 Hub
5
Hub
6
upstream downstream
Universal Serial Bus Connectivity
RAM ROMIP
SP
DP
USBinterface
Periphs
CU ALU
upstream port
downstream ports
Intel 8x931 USB Per ipheral MicrocontrollerCSA Rob Williams CSA ch 10 - p 137Pearson Education (c) 2006
Localanalogue
line
directdigital
connection
Digital trunk lines
Localanalogue
line
Inter nalmodemExter nal
modem
Using modems to transfer data on the telephone networ k
0 0 01 1
01 1
01
Data
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ON / OFFCarr ier
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FSKFrequency
Shift Keying
Frequency Modulation Technique
ITU Cat Capacity Type
V.21 300/600 bps Frequency shift
V.22 1200 bps Phase shift
V.22bis 2400 bps Amplitude & Phase shift
V.29 9600 bps Phase shift
V.32 9600 bps Amplitude & Phase shift
V.32bis 14.4 kbps Amplitude & Phase shift
V.17 14.4 bps Fax
V.34 28.8 kbps Amplitude & Phase shift
Modem Standards and Coding Schemes
CSA Rob Williams CSA ch 10 - p 138Pearson Education (c) 2006
Command FunctionATA Answer incoming call
ATDnnn-nnnn Tone dials the phone number nnn-nnnnATL Redials last number dialed
ATPDnnn-nnnn Pulse dial nnn-nnnnATW Wait for dial toneATH0 Hang upATM0 Speaker offATM1 Speaker is on until a carrier is detectedATM2 Speaker is always onAT O0 Puts modem in data modeAT O1 Takes modem out of data modeATY0 Disable disconnection on pauseATY1 Enable disconnection on pause
Some of the Hayes Modem AT Command Set
0 0 01 1
01 1
01
Data
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........................................................................................................................................................................................................................................................................................................................... 2B1Q
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3B1O
00 01 10 11
000 011 011 010
Phase Modulation Increases the Bit Signalling Rate
CSA Rob Williams CSA ch 10 - p 139Pearson Education (c) 2006
0π
π /2
- π /2
θr
r - Amplitudeθ - Phase
Phase shift modem with asingle carrier frequency
signalling 0 or 1 with0 or π phase shift
Quad Phase, Single Amplitudeπ/4, -π/4, 3π/4, -3π/44 lev el QAM, 2B1Q
Oct Phase, Dual Amplitude0, π/4, π/2, -π/4, -π/2, 3π/4, -3π/4, π
8 lev el QAM, 3B1O
Oct Phase, Quad Amplitude,32 level QAMV32 modems
Amplitude Phase Diagrams Illustrating someModulation Schemes
CSA Rob Williams CSA ch 10 - p 140Pearson Education (c) 2006
CSA Ch 11CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 11 - p 141Pearson Education (c) 2006
11. CSA - Parallel connections
SPP Standard Parallel Por t 100 kbytes/sec Output software operatedEPP Enhanced Parallel Por t 1 Mbytes/sec Input/Ouput h/w handshake circuitsECP Extended Capability Por t 5 MBytes/sec Input/Ouput DMA with FIFO
PC Parallel Por t (Centronics) Standards
Pr inter Busy
Data lines
Strobe>0.1µs
>4µs ACK
114
Pin SPP Host PrinterD-25
1 Strobe →2 data bit 0 →3 data bit 1 →4 data bit 2 →5 data bit 3 →6 data bit 4 →7 data bit 5 →8 data bit 6 →9 data bit 7 →
10 ACK ←11 BUSY ←12 PE Paper Out ←13 SLCT ←14 auto LF →15 Error ←16 INIT →17 SLCT IN →
18-25 GRND
The Centronics Standard Interface (SPP)
Computer Pr inter
Ready set
Data byteStrobeBusy set
AcknowledgeReady set
Sequence of Events within a Centronics Data TransferCSA Rob Williams CSA ch 11 - p 142Pearson Education (c) 2006
Busfree Arbit Device
select Tr ansfer
Sequence of Phases within a SCSI Transfer
Pin EPP Computer PrinterD-25
1 Write →2 data bit 0 ←→3 data bit 1 ←→4 data bit 2 ←→5 data bit 3 ←→6 data bit 4 ←→7 data bit 5 ←→8 data bit 6 ←→9 data bit 7 ←→
10 Interrupt ←11 Wait ←12 user def ←13 user def ←14 Strobe ←15 user def ←16 Reset →17 Addr Strobe ←→
18-25 GRND
The Centronics Enhanced Interface (EPP / ECP)
1. fitting a large memory buffer inside the printer2. run a background print spooler3. use a full multi-tasking system
How to prevent delays caused by a slow printer
CSA Rob Williams CSA ch 11 - p 143Pearson Education (c) 2006
Pin Master Slave2 data bit 0 ←→4 data bit 1 ←→6 data bit 2 ←→8 data bit 3 ←→
10 data bit 4 ←→12 data bit 5 ←→14 data bit 6 ←→16 data bit 7 ←→18 PARITY ←→32 ATN →36 BSY ←38 ACK →40 RST →42 MSG ←44 SEL →46 C /D ←48 REQ ←50 I / O ←
Group Command
LUN (MSB)
Disk Logical block addr
(LSB)
No of blocks
Vendor reser ved FlagLnk
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
7
0
1 50
Small Computer Systems Interface (SCSI)and Command Packet
BSY - Busy indicates that someone is currently using the bus.
SEL - Select allows the initiator to select a target and by the target to resumean interrupted session.
C /D - Control / Data is controlled by the target to indicate whether controlor data items are being transferrred on the data bus.
I /O - Input / Output allows the target to definethe direction of the data transfer.
ATN - Attention is used by the master to tell the slave that data is availableon the bus.
MSG - Message, activated by the target during the message phase of transfer.
REQ - Request, used by the target device, signals to the master that data can betransmitted. It is part of the REQ / ACK handshake pair.
ACK - Acknowledge, controlled by the initiator to confirm a transfer.
RST - Reset bus, forces all attached devices to stop activity and reset the hardware.
CSA Rob Williams CSA ch 11 - p 144Pearson Education (c) 2006
Group 100 Test unit ready 13 Ver ify01 Rezero unit 14 Recover buffer03 Request sense 15 Mode select04 For mat unit 16 Reser ved unit05 Read block limits 17 Release unit07 Reassign blocks 18 Copy08 Read 19 Erase0A Write 1A Mode sense0B Seek 1B Start / stop0F Read reverse 1C Receive diagnostic10 Write file mark 1D Send diagnostic11 Space 1E Lock media12 Inquiry
Group225 Read capacity 30 Search data high26 Extend addr rd 31 Search data equal2A Extend addr wr 32 Search data low2E Write 7 ver ify 33 Set limits2F Ver ify 39 Compare
3A Copy & ver ify
SCSI Message Codes
HM82C117400
7400
7400
PC 8 bit Bus EdgeConnector
An 8 bit PC/ISA-bus Printer Interface CardCSA Rob Williams CSA ch 11 - p 145Pearson Education (c) 2006
i8255i8255i8253
ManualPort address
set up switchesISA 16 bit Bus Edge Connector
An extended 16 bit PC/ISA-bus Parallel I/O Card
EISA
A B
D C
A BD C
Stacking three 96x90mm PC/104 cards
GND I /OCHCKRESET SD7
+5V SD6IRQ2 SD5
-5v SD4DQQ2 SD3
-12v SD2SRDY SD1
+12v SD0KEY IOCHRDY
SMEMW AENSMEMR SA19
IOW SA18IOR SA17
DAK 3 SA16DRQ3 SA15DAK 1 SA14DRQ1 SA13
REFRESH SA12BCLK SA11IRQ7 SA10IRQ6 SA9IRQ5 SA8IRQ4 SA7IRQ3 SA6
DAK 2 SA5TC SA4
BALE SA3+5v SA2
OSC SA1GND SA0GND GND
GND GNDMEMCS16 SBHE
IOCS16 LA23IRQ10 LA22IRQ11 LA21IRQ12 LA20IRQ15 LA19IRQ14 LA18DAK 0 LA17DRQ0 MEMRDAK 5 MEMWDRQ5 SD08DAK 6 SD09DRQ6 SD10DAK 7 SD11DRQ7 SD12
+5v SD13MASTER SD14
GND SD15GND KEY
GND I /OCHCKReset DRV D7
+5V D6IRQ2 D5
-5v D4DQQ2 D3
-12v D2OWS D1+12v D0GND I/O Ch Rdy
SMEMW AENSMEMR A19
IOW A18IOR A17
DAK 3 A16DRQ3 A15DAK 1 A14DRQ1 A13DAK 0 A12
CLK A11IRQ7 A10IRQ6 A9IRQ5 A8IRQ4 A7IRQ3 A6
DAK 2 A5T/C A4
ALE A3+5v A2
14.3MHz A1GND A0
MEMCS16 SBHEIOCS16 LA23
IRQ10 LA22IRQ11 LA21IRQ12 LA20IRQ15 LA19IRQ14 LA18DAK 0 LA17DRQ0 MEMRDAK 5 MEMWDRQ5 SD08DAK 6 SD09DRQ6 SD10DAK 7 SD11DRQ7 SD12
+5v SD13MASTER SD14
GND SD15
A compar ison of ISA Bus and PC/104 connectors
The PCI bus can operate in two modes:
Multiplexed Mode A single 32 bit bus is shared by address and datainfor mation. This increases the effective bus width, but reduces thedata rate.
Burst Mode This is the same trick that EDO DRAM employs. After anaddress has been sent, several data items will follow in quicksuccession. The bridge is capable of assembling "packets" of data andbursting it through to the PCI bus when ready.
PentiumCPU
System bus, 66MHz, 64bits
PCINor th Br idge
PCI Bus, 33MHz, 32bits
ISASouth Bridge
ISA bus, 8.33MHz, 16bits
DiskControllerGraphics
Relationship of the PCI Bridge to Main Bus
CPU System
Bus
PCI
Bus
Prefetchbuffer
Postingbuffer
Postingbuffer
Prefetchbuffer
The PCI Bridge
CSA Rob Williams CSA ch 11 - p 147Pearson Education (c) 2006
1
12V TRSTTCK +12vGND TMSTDO TDI+5v +5v+5V INTA
INTB INTCINTD +5v
PRSTN1 resres +5v I/O
PRSTN2 resGND GNDGND GNO
res resGND RSTCLK +5v I/OGND GNTREQ GND
5v I/O resAD31 AD30AD29 +3.3VGND AD28
AD27 AD26AD25 GND+3.3v AD24
C/BE 3 IDSELAD23 +3.3vGND AD22
AD21 AD20AD19 GND+3.3v AD18AD17 AD16
C/BE 2 +3.3vGND FRAME
IRDY GND+3.3V TRDY
DEVSEL GNDGND STOP
LOCK +3.3vPERR SDONE+3.3v SBO
SERR GND+3.3v PAR
C/BE 1 AD15AD14 +3.3vGND AD13
AD12 AD11ADIO GNDGND AD9
AD8 C/BE 0A07 +3.3V
+3.3v AD6AD5 AD4AD3 GNDGND AD2AD1 ADO
+5v I/O +5v I/OACK 64 REQ64
+5V +5v+5v +5v
PCI Socket
CSA Rob Williams CSA ch 11 - p 148Pearson Education (c) 2006
Card Serial NumberA B C D E F G H
1 0 0 0 0 0 0 0 12 0 0 0 0 0 0 1 03 0 0 0 0 0 0 1 14 0 0 0 0 0 1 0 05 0 0 0 0 0 1 0 16 0 0 0 0 0 1 1 07 0 0 0 0 0 1 1 18 0 0 0 0 1 0 0 09 0 0 0 0 1 0 0 1
10 0 0 0 0 1 0 1 011 0 0 0 0 1 0 1 112 0 0 0 0 1 1 0 013 0 0 0 0 1 1 0 114 0 0 0 0 1 0 1 115 0 0 0 0 1 1 1 1
Plug ’n Play Sequence
Manufacturer MID PIDAdaptec 9004 36868Compaq 1032 4146Creative 10F6 4342Cyr ix 1078 4216Epson 1008 4104HP 103C 4156Intel 8086 32902Matsushita 10F7 4343Mitsubishi 1067 4199Motorola 1057 4183NCR 1000 4096Toshiba 102F 4143Tseng Labs 100C 4108
Example Plug and Play Identity NumbersCSA Rob Williams CSA ch 11 - p 149Pearson Education (c) 2006
GND GNDD3 CD DET 1D4 D11D5 D12D6 D13D7 D14
CD EN 1 D15A10 CD EN 2
OUT EN REFRESHA11 IOR
A9 IOWA8 A17
A13 A18A14 A19
WE /PRG A20READY /BUSY A21
+5v +5vV
pp1 V
pp2
A16 A22A15 A23A12 A24
A7 A25A6 RFUA5 RESETA4 WAITA3 INPACKA2 REG SELA1 SPKRA0 STSCHGD0 D8D1 D9D2 D10
IOIS16 CD DET 2GND GNDPCMCIA Interface
CSA Rob Williams CSA ch 11 - p 150Pearson Education (c) 2006
CSA Ch 12CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 12 - p 151Pearson Education (c) 2006
12. CSA - Memory hierarchy
CPU
4 GbyteMemor y
A0-A31
Fully populated main memory
CPU registers - 0.5 ns
LI Cache Memory - 1 ns
LII Cache Memory - 2.5 ns
Main Memory - 10 ns
Disk Cache - 10 ns
Disk Storage - 10 ms
Tape Backup - 10 min
words - 2 / 4 bytes
lines - 32 bytes
lines - 32 bytes
pages - 4 Kbytes
blocks - 4 Kbytes
files - Mbytes
CPU Control Unit
Pr imary Cache Controller
Secondar y Cache Controller
Memor y Management Unit
Device Controller
Administrative staff
256 bytes
16 Kbytes
256 Kbytes
512 Mbytes
16 Mbyte
80 Gbytes
20 Tbytes
Memor y Perfor mance Hierarchy
CSA Rob Williams CSA ch 12 - p 152Pearson Education (c) 2006
Facility Size device Unitcost, £ £ / Mbyte
DRAM 64 MB SDRAM 168 pin DIMM 40 0.632 MB EDO 72 pin SIMM 50 1.6
SRAM 256 KB/10ns SRAM chip 2 64SCSI PCI card 180
Hard Disk 10GB IDE 110 0.0110GB SCSI 250 0.025
CD-ROM 650 MB 32x IDE 60 0.12 R
CD-RW 650 MB 2x IDE 200 0.3 R
WORM disk 0.75RW disk 2.50
Jazz 1 GB drive 2001 GB disk 65 0.25 R
Zip 100 MB drive 60100 MB disk 15 0.75 R
DAT 4 GB SCSI dr ive 3504 GB tape 2.5 0.09 R
Floppy 1.4 MB dr ive 151.4 MB disk 0.5 11 R
Memor y costs
CPU time
Memor ylocation
Memor y access plot, showing locality effects
CSA Rob Williams CSA ch 12 - p 153Pearson Education (c) 2006
0 1 2 3 4 5 6 7 8 9 10 . . . .Column index
0123456789
10...
Row
inde
x
row 0 row 1 row 2 row 3 row 4
Array indexing with memory lay out of array data
CSA Rob Williams CSA ch 12 - p 154Pearson Education (c) 2006
#include <stdio.h>#include <sys/times.h>#include <limits.h>#define MAX 1000
clock_t times(struct tms* b);
main () int i, j;int big[MAX][MAX];int sum, start, middle, end;struct tms tbuff;
times( &tbuff); start = tbuff.tms_utime;for(i=0; i<MAX; i++)
for(j=0; j<MAX; j++) sum += big[i][j]; /* <------------ i, j here */
;;times( &tbuff); middle = tbuff.tms_utime;for(i=0; i<MAX; i++)
for(j=0; j<MAX; j++) sum += big[j][i]; /* <------------ j, i here */
;;times( &tbuff); end = tbuff.tms_utime;printf("First run time is %d \n",(middle - start)*1000/CLK_TCK);printf("Second run time is %d \n",(end - middle)*1000/CLK_TCK);
Demonstrating cache action
rob [80] cc cache .c -o cacherob [81] cacheFirst run time is 150Second run time is 310rob [82]
Results from the Cache Test
Estimate: 21 x 5ns x 106 + 13 x 5ns x 103 = 105ms
CSA Rob Williams CSA ch 12 - p 155Pearson Education (c) 2006
Accessing alongeach row[ i ] [ j ]
Accessing alongeach column
[ j ] [ i ]
Alter native access patterns (strides) for a 2-D array
CSA Rob Williams CSA ch 12 - p 156Pearson Education (c) 2006
! 19 for(i=0; i<MAX; i++) mov0,%l0st%l0,[%fp-8]ld[%fp-8],%l0cmp%l0,1000bge.L118nop! block 2
.L119:
.L116:! 20 for(j=0; j<MAX; j++)
mov0,%l0st%l0,[%fp-12]ld[%fp-12],%l0cmp%l0,1000bge.L122nop! block 3
.L123:
.L120:! 21 sum += big[i][j];
sethi%hi(-4000016),%l0or%l0,%lo(-4000016),%l0ld[%fp+%l0],%l4sethi%hi(-4000012),%l0or%l0,%lo(-4000012),%l0add%fp,%l0,%l3ld[%fp-8],%l0sll%l0,12,%l2sll%l0,5,%l1sub%l2,%l1,%l2sll%l0,6,%l1sub%l2,%l1,%l1add%l3,%l1,%l2ld[%fp-12],%l0sll%l0,2,%l1add%l2,%l1,%l0ld[%l0+0],%l1add%l4,%l1,%l1sethi%hi(-4000016),%l0or%l0,%lo(-4000016),%l0st%l1,[%fp+%l0]
! 22 ;ld[%fp-12],%l0add%l0,1,%l0st%l0,[%fp-12]ld[%fp-12],%l0cmp%l0,1000bl.L120nop! block 4
.L124:
.L122:! 23 ;
ld[%fp-8],%l0add%l0,1,%l0st%l0,[%fp-8]ld[%fp-8],%l0cmp%l0,1000bl.L116nop! block 5
.L125:
.L118:
A Fragment of asm outputfrom SPARC compiler
CSA Rob Williams CSA ch 12 - p 157Pearson Education (c) 2006
Cache Control Unit
CPU
256 Kbyte2nsSRAM Cache
512Mbyte15ns DRAM
Main Memory
System Bus
I/O Subsystem
Cache Memory and Controller Unit
1. Folded address space, also known as Direct Mapping2. Associative (content addressable) memory3. Hashed mapping
Mapping Addresses from Main to Cache Memory
CSA Rob Williams CSA ch 12 - p 158Pearson Education (c) 2006
11 10 01 00
111110101100011010001000
11111 111 1111111 111 1011111 111 0111111 111 0011111 110 1111111 110 1011111 110 0111111 110 00
10100 101 1110100 101 1010100 101 0110100 101 0010100 100 1110100 100 1010100 100 0110100 100 00
00000 111 0000000 001 1100000 001 1000000 001 0100000 001 0000000 000 1100000 000 1000000 000 0100000 000 00
Address
Cache Memory
Main Memory
TA G Memor y
4 0
Address Folding for Direct Mapped Cache
CSA Rob Williams CSA ch 12 - p 159Pearson Education (c) 2006
11 10 01 00
11111 111 1111111 111 1011111 111 0111111 111 0011111 110 1111111 110 1011111 110 0111111 110 00
10100 111 1110100 110 1010100 101 0110100 100 0010100 011 1110100 010 1010100 001 0110100 000 00
00000 111 0000000 001 1100000 001 1000000 001 0100000 001 0000000 000 1100000 000 1000000 000 0100000 000 00
Address
Cache Memory
Main Memory
TA G Memor yStatus
7 0
Associative Cache
A31-A24
TA G 01
Checking the Address in Associative Memor y
CSA Rob Williams CSA ch 12 - p 160Pearson Education (c) 2006
1. on start-up of a new program2. when the cache is too small to hold the active execution set3. cache line conflict in a direct mapped cache.
Causes of Cache Misses
CSA Rob Williams CSA ch 12 - p 161Pearson Education (c) 2006
Fr ames
Overflow
pages
Retr ieval
of pages
Swap Area
MainMemor y
Disk
Vir tual memor y scheme for main memory overflow
Page TableRegister
User Code
Page Table
User Data
Page# Offsetlogical addr
Fr ame# Offsetphysical addrMemor y
0
0
31
31
Vir tual memor y logical page into physical frame addresstranslation
CSA Rob Williams CSA ch 12 - p 162Pearson Education (c) 2006
CPU
MMU
SRAMCache
DRAMMain Memory
System Bus
I/O Subsystem
vir tual address
physical address
CPU
SRAMCache
MMU
DRAMMain Memory
System Bus
I/O Subsystem
vir tual address
physical address
Physical addressing cache (Pentium) Vir tual addressing cache (ARM)
Alter native positions for the memory management unit
4 GbyteCode
SegmentData
Segment
StackSegment
Logical AddressingProgrammers’ View
StackSegment
FFFF FFFF
DataSegment
CodeSegment
0000 0000
Vir tual AddressingO/S View
CS Base
DS Base
SS Base
FFF FFFF
000 0000
frame
Physical AddressingHardware View
page
The relation between different address designations
CSA Rob Williams CSA ch 12 - p 163Pearson Education (c) 2006
Oxide Layer 2.5µm
Human Hairabout 50µm
Read/wr ite headFlying height 0.5µm
Finger print Smear3µm
Smoke Par ticle5µm
100km/hr
Environmental obstacles with R/W disk heads
Voice Coilactuator
Data sectorsalong a track
Read/wr ite head
Schematic Diagram of Hard Disk Unit
dr ive_capacity =
no_of_surfaces x no_of_tracks x no_of_sectors x size_of_sector
CSA Rob Williams CSA ch 12 - p 164Pearson Education (c) 2006
A computer system having 2 Mbytes of RAM has hard disks with thefollowing character istics:
Rotational speed: 3600 rpmTr ack capacity: 16384 bytesHeads/cylinder : 10Head movement time, track to track:20 msAv erage seek time: 50 ms
How long does it take to dump memory onto disk? Assume the disk is empty.
3600r pm = 60 rpsrotational period = 1/60 secs = 1000/60 msec = 16.66 msec = 17 mseclatency = 8.5 msec
data rate = 16 Kbytes / 17 msec = 1 Mbyte/secflow time for 2 Mbyte = 2000 msec = 2 sec
2 Mbyte needs 128 tracks or 12.8 cylinders ie 13 head movements
tot time = head movement (seeks) + rotnl delays (latencies) + data flow time= 1 x 50 + 12 X 20 + 13 X 8.5 + 2000= 2314 msec
Estimating Hard Disk Data Retrieval TimeDisk Perfor mance SpecificationTr ack to Track Seek 1 msAv erage Seek < 9 msMaximum Seek 20 ms
Av erage Latency 5.77 msRotation 5400 rpm
Controller overhead < 0.3 msStar t time 7.3 sec
Computer interface rate < 66.7 Mbytes/secMedia read/write rate < 27.8 Mbytes/sec
Sectors per track 266 - 462Cylinders (tracks per surface) 17549Bytes per sector 512Data zones per surface 16
Integrated buffer size 2 MbytesMemor y type SDRAM
Model 90650U2 90845U 91020U3 91360U4 92040U6 92040U8Capacity (Gbytes) 6.5 8.45 10.21 13.61 20.42 27.23
Heads 2 3 3 4 6 8Disks 1 2 2 2 3 4
A Specification Table for Maxtor Hard DisksCSA Rob Williams CSA ch 12 - p 165Pearson Education (c) 2006
Time
Tr ackNumber
20406080
100120140160180200
97179358012
1905051
121122
Queue
FCFS
SSTF
SCAN
Disk Access Scheduling Techniques
81
34
29
FCFS SSTF SCAN
Av erage inter-trackseek distances
Compar ison of Disk Scheduling Techniques
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CD data Spiral and Magnetic Disk Concentric TracksCSA Rob Williams CSA ch 12 - p 166Pearson Education (c) 2006
lacquercoating (30µm)
Polycarbonatedisk (1.2mm)
metaliclayer
bit pit(0.12µm)
lacquercoating (30µm)
Polycarbonatedisk (1.2mm)
metaliclayer
bit pit(0.12µm)
focusing
tracking
Laseremitter
lightdetector
beamsplitter
rotating(1000r pm)
Optical disk read head
Hard Coating
PolycarbonateDisk
Lower dielectr ic
Recording layerUpper dielectric
Reflective coatingLacquer
Paper Label
Tr ackgrooves
1.2 mm
Laser beam
1.6 µm
CD-RW disk structure
CSA Rob Williams CSA ch 12 - p 167Pearson Education (c) 2006
Discrete Cosine Transfor m (DCT) base functionsas used with MPEG image compression
CSA Rob Williams CSA ch 12 - p 168Pearson Education (c) 2006
CSA Ch 13CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 13 - p 169Pearson Education (c) 2006
13. CSA - Programmer’s Viewpoint
Application User
Systems Admin
HLL Programmer
Systems Programmer
H/W Engineer
Different jobs, different viewpoints
the switch is closed can the valve open
FABWrite(num, B_8255); printf("switch
move EAX, 04H lea EBX,string call pr
92 E6 EA 0F C2 66 3F A1 92 E6 EA 0F C2
1001 0010 1110 0110 1110 1010 0000 1111
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Same device, many different viewpoints
CSA Rob Williams CSA ch 13 - p 170Pearson Education (c) 2006
Graphical representation of a directorydesigned for application users
rob@milly [80] ls -alttotal 6702
drwx--x--x 76 rob csstaff 7168 Aug 7 17:57 ..
drwx--x--x 3 rob csstaff 3072 Aug 7 15:55 .
-rwx------ 1 rob csstaff 42544 Aug 6 14:57 #testparam.c#
-rwx------ 1 rob csstaff 42545 Aug 5 14:55 sort.c
-rwx------ 1 rob csstaff 9503 Aug 5 14:35 jeffsm.c
-rwx------ 1 rob csstaff 9525 Aug 5 14:31 jeffsm.c˜
-rwx------ 1 rob csstaff 5144 Aug 3 14:31 a.out
-rwx------ 1 rob csstaff 17851 Aug 3 14:31 ch_9c.txt
-rwx------ 1 rob csstaff 17890 Aug 3 14:30 ch_9c.asc
-rwx------ 1 rob csstaff 21180 Aug 2 17:28 ntime.c
rob@milly [81]
Tr aditional text-only Unix directory listing using lsCSA Rob Williams CSA ch 13 - p 171Pearson Education (c) 2006
Chapt7 cat
Header
eqn pic troff lpr Pr inter
cat header ch_13c|geqn|gpic|groff -fH|lp -dps -oduplex
A Unix process pipeline to for mat and print textused by systems administrators
rob@milly [80] /etc/mknod pipe1 prob@milly [80] /etc/mknod pipe2 prob@milly [80] /etc/mknod pipe3 prob@milly [81] ls -al pipe*
prw------- 1 rob csstaff 0 Oct 14 18:39 pipe1prw------- 1 rob csstaff 0 Oct 14 18:39 pipe2prw------- 1 rob csstaff 0 Oct 14 18:39 pipe3
rob@milly [82] cat letter.tmp >! pipe1 &rob@milly [82] cat pipe1 >! pipe2 &rob@milly [82] cat pipe2 >! pipe3 &
Demonstrating Unix named pipes
CSA Rob Williams CSA ch 13 - p 172Pearson Education (c) 2006
#!/bin/sh## Script converts sar data into graphs - PJN 20/10/1998## Extend the PATH to include gnuplotPATH=$PATH:/usr/local/bin ; export PATH
# Procedure to remove non-data lines from log file.remclutter()
grep : |grep -v free |grep -v % |grep -v / |grep -v restarts# Procedure to pad numbers with zeroes to 2 digits.padnum()
NUM=$1while [ `/bin/echo "$NUM\c" | wc -c` -lt 2 ]; do
NUM="0$NUM"doneecho $NUM
# Procedure to convert time of day timestamps to decimal days.parsetimes()
DAY=0OLDHOUR=23while read TIME DATA; do
if [ "$DATA" = "" ]; thenDATA="0 0 0 0 0 0 0 0 0 0 0 0"
fiHOUR=`echo $TIME | cut -f1 -d:`MIN=`echo $TIME | cut -f2 -d:`if [ $HOUR -lt $OLDHOUR -a "$MIN" = "00" ]; then
DAY=`expr $DAY + 1`fi
PTIME=`expr \( \( \( $HOUR \* 60 \) + $MIN \) \* 100 \)/1440`PTIME=$DAY.`padnum $PTIME`echo "$PTIME $DATA"OLDHOUR=$HOUR
done# Procedure to get data from a named column.getcol()
tr -s ’ ’ ’ˆ’ | cut -f1,$1 -d\ˆ | tr ’ˆ’ ’ ’ Continues
CSA Rob Williams CSA ch 13 - p 173Pearson Education (c) 2006
# Determine the i/p and o/p files (for last week’s data).WEEK=`date +%W`WEEK=`expr $WEEK - 1`if [ $WEEK -eq -1 ]; then
WEEK=52fiWEEK=`padnum $WEEK`DATAFILE=/var/adm/sa/sa$WEEKOUTFILE=/tmp/$$.graphs
# Process virtual memory data from sar log.echo "VM usage"sar -f $DATAFILE -r > /tmp/$$.sarcat /tmp/$$.sar | remclutter | parsetimes > /tmp/$$.sar-frm /tmp/$$.sarcat /tmp/$$.sar-f | getcol 2 > /tmp/$$.freememcat /tmp/$$.sar-f | getcol 3 > /tmp/$$.freeswap(cat << EOF
set term postscriptset timeset xtic 0,0.5set title "`hostname` virtual memory usage"f(x) = (x * 512 ) / 1048576g(x) = (x * `pagesize` ) / 1048576plot [0:7] []\"/tmp/$$.freemem" thru g(x) title "Free RAM MB" with lines,\"/tmp/$$.freeswap" thru f(x) title "Free Swap MB" with linesEOF
) | gnuplot > $OUTFILErm /tmp/$$.freemem /tmp/$$.freeswap /tmp/$$.sar-f
lp -d ps $OUTFILEsleep 60; rm $OUTFILEexit
A Unix administration script for perfor mance statistics
CSA Rob Williams CSA ch 13 - p 174Pearson Education (c) 2006
#include <stdio.h>
int bsort(char* pc[ ], int n ) int gap, i, j;char* pctemp;
for (gap = n/2; gap > 0; gap /= 2)for (i = gap; i < n; i++)
for(j = i-gap; j>= 0; j -= gap) if (strcmp(pc[j], pc[j+gap]) <= 0) break;pctemp = pc[j]; pc[j] = pc[j+gap]; pc[j+gap] = pctemp;
void main(void) int i;char* names[ ] =
"Monday", "Tuesday", "Wednesday", "Thursday","Friday", "Saturday","Sunday";
i = bsort(names, 7);for(i=0; i<7; i++)
printf("%s0, names[i] );;
Example HLL algorithm - Bubble Sor tfor the software engineer
CSA Rob Williams CSA ch 13 - p 175Pearson Education (c) 2006
SEQ
IT
SEL
do A do B do C
do D
do F do E
* 10
X>0
Str ucture Char t representations of SEQ, IT & SEL
void doitall(void) doA( );doB( );doC( );
for( i=0; i<10; i++ ) doD( );
x = 0;while (x < 10)
doD( );x++;
if (x > 0) doE( );
else doF( );
BOOL unsigned 1 bit valuechar unsigned 8 bit valueWCHAR unsigned 16 bit valueBYTE unsigned 8 bit integershor t signed 16 bit integerWORD unsigned 16 bit integerint signed 32 bit integerLONG signed 32 bit integerunsigned unsigned 32bit integerDW ORD unsigned 32 bit integerfloat IEEE 32 bit realdouble IEEE 64 bit real
Data types for C/C++, popular languageswith systems programmers
CSA Rob Williams CSA ch 13 - p 176Pearson Education (c) 2006
do ASEQ
do B
do C
?IT
do D
?SEL
do E do F
y
n
y n
Flow Char t representation of SEQ, IT & SEL
CALL doACALL doBCALL doC
---------------------------
L1: JZ L2
. . . .
CALL doDJMP L1
L2:- - - - - - - - - - - - - - -
MOV CX,10L3:
. . . .
CALL doDLOOP L3
---------------------------
CMP EAX,12JGE L4CALL doEJMP L5
L4 CALL doFL5
CSA Rob Williams CSA ch 13 - p 177Pearson Education (c) 2006
Circuit schematic diagram for the electronic engineer
User Program
HLL Librar y Routines
Operating SystemProcedures
Microcode Interpreter Co-processor Units
Digital Logic Circuits
Electronic Devices
A multi-level computerfunctional interaction
CSA Rob Williams CSA ch 13 - p 178Pearson Education (c) 2006
1. instruction mnemonics into binary codes2. user defined symbols into constant numbers3. numbers from base to base, nor mally decimal to binary4. symbolic position labels into physical addresses
Tr anslation activities of an assembler
Symbol Type Value
ADD opcode $FF
ADDA opcode
SUB opcode
MOVE opcode
star t defined
exit undefin
loop1 defined
spx defined
spr ite defined
Symbol Table Entries
CSA Rob Williams CSA ch 13 - p 179Pearson Education (c) 2006
Sourcefile
Pre-processor
Errorrepor t
Sourcefile
Lexicalanalysis
Errorrepor t
Tokenlist
Symboltable
Syntacticanalysis
Errorrepor t
Inter mediatecode
CodeGen
Machinecode
CodeOptim
BetterMachine
code
Stages of Compilation
CSA Rob Williams CSA ch 13 - p 180Pearson Education (c) 2006
CSA Ch 14CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 14 - p 181Pearson Education (c) 2006
14. CSA - Local Area Networks
IBM
Front-endprocessor
ColdWater
DEC
Mainframecomputer
Minicomputer
Personalcomputer
LocalArea Networ k
Evolution of computing provision
emailfile transfer
using ftp
Displaying LAN traffic using Sun’s perfmeterCSA Rob Williams CSA ch 14 - p 182Pearson Education (c) 2006
802.3 CSMA/CD802.4 Token Bus802.5 Token Ring802.6 MAN802.11 Wireless LAN802.12 100 Mbps LAN
Some of the IEEE 802 standards committees
Workstations
Ser ver
10Mbps Ethernet
//////// \\\\\\\\Packet signal70Ω
Terminator70Ω
Terminator
Tr aditional office bus LAN facility
SwitchingHub
workstationSer ver
Star topology, switched hub, ether net
CentralHub
SwitchingHub
SwitchingHub
workstations
Star topology with hierarchical hubsCSA Rob Williams CSA ch 14 - p 183Pearson Education (c) 2006
12345678 1236
4578
Cat 5 twistedpair cable
Connections to an RJ45 LAN Plug
SMCUltraChip
70 Ω stubter minator
BNCTee piececonnector
ThinEther net
10Base2 cable
RJ45 socket10BaseT
BNC10Base2socket
10Base5socket
A networ k interface card with 10Base2 &10BaseT connectors
CSA Rob Williams CSA ch 14 - p 184Pearson Education (c) 2006
Ser ialNetwor kinterface
Networ kController
Device Driver
TCP/IP
Application
Hardware
Software
H/w and s/w layers to manage the LAN Interface
CSA Rob Williams CSA ch 14 - p 185Pearson Education (c) 2006
20MHzClock
Data
DataOut
10Mbps
0 1 0 0 1 1 0 1
+0.7v
-0.7v
XOR
Manchester Encoding for Data and Clock
rising edge - 0, dropping edge - 1
10101010 10101010 10101010 101010100 101010100 101010100 10101010
Flag Bytes
10101010 10101010 10101010 10101010 10101011 [Ethernet_packet_body....]↓
CSA Rob Williams CSA ch 14 - p 186Pearson Education (c) 2006
10Base5 10Mbps, Thick Ether net500m segment length,minimum tap separation 2.5m,maximum of 4 repeaters,50 Ω coax cablevampire tap (Media Access Unit)
10Base2 10 Mbps, Thin Ethernet200m (165m) segment length,minimum tap separation 0.5m,maximum of 4 repeaters,70 Ω coax cableBNC T-piece bayonet connection
10BaseT 10 Mbps, Switched Ethernet100m segment length,end-to-end, simplex100 Ω AWG24 twisted pairs cableRJ45 telecom jack
100BaseT 100 Mbps,205m segment length,end-to-end, simplex100 Ω AWG24 twisted pairs cable
100BaseF 100 Mbps Fibre Ether net2000m segment lengthend-to-end, simplexoptic fibres
Various ethernet media standards
CSA Rob Williams CSA ch 14 - p 187Pearson Education (c) 2006
Tpacket =500 x 5 x 2
1 x 108 = 50µs
tbit = 0. 1µs
Npacket =500. 1
= 500 bits
NBytes =500
8= 62. 5 ~ = 64 Bytes
Time, µsec
LANLengthmetres
S1
S2
Tr ansmitted
Received
Star t End
Star t End
Collisionwarning
Tr ansitTime
Collision
Collision Detection and Transit Times for Ethernet
CSA Rob Williams CSA ch 14 - p 188Pearson Education (c) 2006
Binar y Tr inar y0000_0000 +-00+-T0000_0001 0+-+-+T0000_0010 +-0+-0T0000_0011 -0++-0T0000_0100 -0+0+-T0000_0101 0+--0+T0000_0110 +-0-0+T0000_0111 -0+-0+T0000_1000 -+00+-T0000_1001 0-++-0T0000_1010 -+0+-0T0000_1011 +0-+-0T0000_1100 +0-0+-T0000_1101 0-+-0+T0000_1110 -+0-0+T0000_1111 +0--0+T
. . . . . . .1111_1111 +0-+00T
8B6T Coding
CSA Rob Williams CSA ch 14 - p 189Pearson Education (c) 2006
Sync Preamble(56 bits)
SFD
Destination
Address
(48 bits)
Source
Address
(48 bits)
Length ofData Field
Data0-1500
Padding0-46
CRC
error detection
15 07
Inter nal Str ucture of an Ethernet Data Packet
CSA Rob Williams CSA ch 14 - p 190Pearson Education (c) 2006
0 HostSubnetNetwor k
1 0 HostSubnetNetwor k
1 1 0 HostNetwor k
Multicast Address1 1 1 0
Reser ved1 1 1 1
0 1 1 1 1 1 1 1
Class A
Class B
Class C
Class D
Class E
Localloopback
31 023
15
7
1•0•0•0 -127•255•255•255
128•0•0•0 -191•255•255•255
192•0•0•0 -223•255•255•255
224•0•0•0 -239•255•255•255
240•0•0•0 -247•255•255•255
127•0•0•0
The 5 For ms of IP v4 numbers and their ranges
rob@milly [20]/usr/sbin/arp -aNet to Media Table
Device IP Addr Mask Flags Phys Addr
----------------------------------------------------
hme0 lentil 255.255.255.255 00:00:8e:06:07:cf
hme1 pb4 255.255.255.255 00:80:5f:cc:5c:20
hme0 rice 255.255.255.255 00:00:8e:06:07:e9
hme0 beans 255.255.255.255 00:00:8e:06:07:c4
hme1 ivor 255.255.255.255 08:00:20:1a:9d:16
hme0 carrot 255.255.255.255 00:00:8e:06:07:e6
hme1 router8 255.255.255.255 08:00:20:19:1c:9a
hme0 hops 255.255.255.255 00:00:8e:06:07:e3
rob@milly [21]
ARP table, translating IP addresses into MAC numbers
CSA Rob Williams CSA ch 14 - p 191Pearson Education (c) 2006
rob@olveston [20]cat /etc/hosts
# Internet host table#127.0.0.1 localhost164.11.10.206 olveston loghost164.11.8.16 egg ns0164.11.253.2 sister ns1164.11.8.99 ada ns2164.11.10.5 riff ns3
rob@olveston [21]
Host table, translating acronym into IP addresses
user data
user dataApplnheader
Appln dataTCPheader
TCPheader Appln dataIP
header
Etherheader
IPheader
TCPheader Appln data Ether
trailer
Appln
TCP
IP
Etherdr iver
Ether net
A Lay ered description of networ king software
CSA Rob Williams CSA ch 14 - p 192Pearson Education (c) 2006
Inspecting the state of a Unix file systems using df
rob@olveston [20]df/ (/dev/dsk/c0t0d0s0 ): 751760 blocks 216981 files
/usr (/dev/dsk/c0t0d0s3 ): 292766 blocks 177111 files
/proc (/proc ): 0 blocks 915 files
/dev/fd (fd ): 0 blocks 0 files
/var (/dev/dsk/c0t0d0s4 ): 264238 blocks 97421 files
/tmp (/dev/dsk/c0t0d0s5 ): 165454 blocks 100191 files
/cache (/dev/dsk/c0t0d0s6 ): 53882 blocks 48381 files
/local (/dev/dsk/c0t0d0s7 ): 4730618 blocks 1264846 files
/usr/misc (thalia:/usr/misc ): 938032 blocks 273054 files
/tutorials (milly:/tutorials ): 282752 blocks 93369 files
/home/staff/cs (sister:/home/staff/csm/csstaff): 4942096 blocks 513071
/var/mail (mailhub:/var/spool/mail): 3582944 blocks 974994 files
/projects/staff (ada:/projects/staff): 1408240 blocks 729518 files
/projects/rob (ada:/projects/rob ): 218704 blocks 95166 files
/WWW/Documents (www:/var/htdocs ): 2032720 blocks 582750 files
/WWW/Servlets (www:/opt/local/JSDK/servlets): 3539408 blocks 344000 files
rob@olveston [21]
local disk driveremote hosts
CSA Rob Williams CSA ch 14 - p 193Pearson Education (c) 2006
Other computerson the networ k
Next availablevir tual dr ive letter
Installing a virtual drive using Windows XP
LAN 2
Gateway
LAN 1
Workstations
Ser ver
Interconnecting LANs using a gateway
CSA Rob Williams CSA ch 14 - p 194Pearson Education (c) 2006
socket to socketcommunication
Linux Windows-XP
Socket communication between remote processes
CSA Rob Williams CSA ch 14 - p 195Pearson Education (c) 2006
socket( )create a socket
bind( )name the socket
listen( )specify queue
accept( )wait for call
accept connectionspawn new socket
send( )/recv( )transfer data
closesocket( )close socket
socket( )create a socket
connect( )connect to server
send( )/recv( )transfer data
closesocket( )close socket
ClientSer ver
Communication with Client-Server connection-based(STREAM) sockets
CSA Rob Williams CSA ch 14 - p 196Pearson Education (c) 2006
SOCKET socket(int af, int typesock, int protocol)
int bind(SOCKET mysock, const struct sockaddr "psock, int nlength)
int listen(SOCKET mysock, int qmax)
int connect(SOCKET yoursock, const struct sockaddr *sname, int nlength)
SOCKET accept(SOCKET mysock, struct sockaddr *psock, int *addrlen)
int send(SOCKET yoursock, const char *pdbuff, int dblen, int flags)
int recv(SOCKET mysock, char *pdbuff, int dblen)
int closesocket(SOCKET mysock)
Win32 Socket Function Calls
CSA Rob Williams CSA ch 14 - p 197Pearson Education (c) 2006
socket( )create a socket
bind( )name the socket
recvfrom( )waiting
accept data
sendto( )retur n data
closesocket( )close socket
socket( )create a socket
bind( )name the server
sendto( )transfer data
recvfrom( )waiting
accept data
closesocket( )close socket
ClientSer ver
Communication with Client - Server connection-less(DGRAM) sockets
CSA Rob Williams CSA ch 14 - p 198Pearson Education (c) 2006
CSA Ch 15CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 15 - p 199Pearson Education (c) 2006
15. CSA - Wide Area Networks
LAN1
LAN2
LAN3
4
5
6 WANWAN
WANs give long distance interconnection for LANs
TCP/IP - are the essential protocols for the Internet
CSA Rob Williams CSA ch 15 - p 200Pearson Education (c) 2006
TCP
IP
EtherDr iver
Networ kInterface
ftp
telnetsmtp
http
user
payload type0800
ARP
UDP
ICMP
bifftalk
17
0806
0206
20/21
23 8025
517512
por t
protocol
Port map(cat /etc/services)
Routing Table/usr/sbin/netstat -rn
ARP Table(/usr/sbin/ar p -a)
Hosts Table(cat /etc/hosts)
The TCP/IP Stack at Wor k
Number Protocol02 ICMP06 TCP17 UDP
IP Protocol Field Values
CSA Rob Williams CSA ch 15 - p 201Pearson Education (c) 2006
> cat /etc/servicestcpmux 1/tcpecho 7/tcpecho 7/udpdiscard 9/tcp sink nulldiscard 9/udp sink nullsystat 11/tcp usersftp-data 20/tcpftp 21/tcptelnet 23/tcpsmtp 25/tcp mailtime 37/udp timservername 42/udp nameserverwhois 43/tcp nicname # usually to sri-nicgopher 70/tcp #Internet Gopherfinger 79/tcpwww 80/tcp http # World Wide Webwww 80/udphostnames 101/tcp hostname # usually to sri-nicsunrpc 111/udp rpcbindsunrpc 111/tcp rpcbind
TCP port numbers and their services from /etc/services
CSA Rob Williams CSA ch 15 - p 202Pearson Education (c) 2006
Sync Preamble
SFD
Destination
Address
(48 bits)
Source
Address
(48 bits)
Length ofData Field
Pa yload Type
IP Frame(Data Payload)
CRC
error detection
Ether net Packet
15 07
VersionHeaderlength TOS
Length (Bytes)
Sequence count(Identity)
Flags
TTLmax hops Protocol
Header checksum
IP Source
address (32 bits)
IP Destination
address (32 bits)
TCP Frame(Data Payload)
IP Header Structure
15 07 Source port
Destination Por t
Tr ansmitted
Sequence number
Acknowledged
Sequence number
Headerlength Flags
Tx windowsize
TCP checksum
Urgent pointer
Optionalfacilities
UserPa yload
15 07
TCP Header Structure
Ether net header IP header TCP header User Data
Ether net, IP, TCP encapsulation
CSA Rob Williams CSA ch 15 - p 203Pearson Education (c) 2006
single datapacket sentimmediately
ACKed
multiple datapackets sent
all ACKed
data sentno ACKs
so Tx pauses
ACKs receivedso Tx resumes
Tr ansmitter Receiver
Datapacket
ACK
Flow control using afour packet buffer
Router
Networ k 5Networ k 1
Br idge
Networ k 2Networ k 1
Repeater Networ k 2Networ k 1
Differentiating Repeaters,Br idges, and Routers
CSA Rob Williams CSA ch 15 - p 204Pearson Education (c) 2006
rob@olveston [20] cat /etc/hosts# Internet host table#127.0.0.1 localhost164.11.253.47 olveston loghost164.11.8.16 egg ns0164.11.253.2 sister ns1164.11.8.99 ada ns2164.11.10.5 riff ns3rob@olveston [21]rob@olveston [21] netstat -rnRouting Table:
Destination Gateway Flags Ref Use Interf-----------------------------------------------------127.0.0.1 127.0.0.1 UH 0 503 lo0164.11.253.0 164.11.253.47 U 3 228 hme0224.0.0.0 164.11.253.47 U 3 0 hme0default 164.11.253.1 UG 0 14297rob@olveston [22]
Destinationhost ornetwor k
Recommendedfirst hop
Status FlagsU - up and OKG - gateway / direct connectionH - host / networ k address
LocalEther net
por t
Unix netstat utility showing the routing table
CSA Rob Williams CSA ch 15 - p 205Pearson Education (c) 2006
Tr affic flooding without routing decisions
RIPOperation
IPNumber
# routerhops
# ticks(56ms)
1st hop
IPNumber
# routerhops
# ticks
2nd hop
RIP packet fields
Region IP Numbers ReservedEurope 194•000•000•000 - 195•255•255•255
N Amer ica 198•000•000•000 - 199•255•255•255S Amer ica 200•000•000•000 - 201•255•255•255Pacific Asia 202•000•000•000 - 203•255•255•255
CIDR IP number allocations
Username
addressbook user
host id
DNSIP number
ar ptable MAC number
Rober t WilliamsUWE, Bristol, UK
rob.williamsolveston.uwe.ac.uk 164.11.253.47 08:00:20:8E:86:5F
Identifier translation required for transmitters
CSA Rob Williams CSA ch 15 - p 206Pearson Education (c) 2006
rob@milly [10] ypcat hosts | more164.11.13.5 gecko164.11.9.89 TT89164.11.235.52 saar164.11.243.225 valdoonican164.11.10.56 StaffPC56164.11.11.73 blackwell164.11.253.47 olveston164.11.8.203 dialin63164.11.8.200 dialin60164.11.13.15 wallaby164.11.235.87 shannon164.11.253.158 new_pb2164.11.243.249 naqqara164.11.194.4 linux04164.11.10.45 drjones164.11.11.71 wesley164.11.235.122 siphon--more--
Inspecting the local hosts file
•mil•gov•edu•com•net•org •fr •de •uk •us
•ac
•uwe
•csm
•gov •co
Hierarchical Domain Naming Structure (DNS)
CSA Rob Williams CSA ch 15 - p 207Pearson Education (c) 2006
rob@milly [33] cat /etc/resolv.confdomain csm.uwe.ac.uksearch csm.uwe.ac.uk uwe.ac.uknameserver 164.11.8.16nameserver 164.11.253.2nameserver 164.11.253.11nameserver 164.11.8.99
rob@milly [34] /usr/sbin/nslookupDefault Server: egg.csm.uwe.ac.ukAddress: 164.11.8.16
> smilodon.cs.wisc.eduServer: egg.csm.uwe.ac.ukAddress: 164.11.8.16
Non-authoritative answer:Name: smilodon.cs.wisc.eduAddress: 128.105.11.80
> ˆDrob@milly [35]
Using the DNS name look-up facility
CSA Rob Williams CSA ch 15 - p 208Pearson Education (c) 2006
Netscape Navigator Web Browser
URL = Protocol identifier/Machine name/file path
CSA Rob Williams CSA ch 15 - p 209Pearson Education (c) 2006
Introducing wor ld.html to Netscape on UnixTags Functions
<HTML>. . . </HTML> Page delimiters<HEAD>. . . </HEAD> Page heading<TITLE>. . .</TITLE> http title (invis)<BODY> . . .</BODY> Main text delimiters<BASEFONT FACE = "Helvetica" SIZE = 12> Body text font selection<FONT SIZE = +2>. .</FONT> Font type, size & colour<Hx> . . . </Hx> Subheading at level x<B> . . . </B> Embolden font<I> . . . </I> Italicize font<UL> . . . </UL> Unordered list<OL> . . . </OL> Ordered list<MENU> . . .</MENU> Menu<LI> List star t<BR> Break text, \n<P> New paragraph<HR> Horizontal line<PRE> . . .</PRE> Nofill, prefor matted<IMG SRC = ". . . "> Inser t image file here<A HREF = "http://www.." > [Press] </A> set up a Hyperlink
Star ter set of HTML tagsCSA Rob Williams CSA ch 15 - p 210Pearson Education (c) 2006
http proxy [URL] - The proxy command allows a proxy HTTP server to be definedwhich will be used in subsequent client commands. Providing a URL argument setsthe proxy server. Setting the proxy to an empty string turns the proxy featureoff.
http head url - The head command retrieves the HTTP header for the documentlocated at URL.
http get url file - The get command retrieves the document located at URL. Thebody of the document is written to file. The command returns the HTTP header asdescr ibed for the http head command above .
http post url filename_1 filename_2 - The post command posts the document infilename_1 to the location URL. The body of the returned document is written tofilename_2. The command returns the HTTP header as described forthe http head command above .
http put URL file - The put command copies the file into the URL. Thecommand returns the HTTP header as described for the http head command above .
http delete URL - The delete command deletes the document at the URL.The command returns HTTP status infor mation.
The %X variables are substituted before a script is evaluated:
%A - The networ k address of the client.
%P - The URL path requested by the requestor.
%S - The search path contained in the URL path.
Examples from Hypertext Transmission Protocol (http)
CSA Rob Williams CSA ch 15 - p 211Pearson Education (c) 2006
rob@olveston [50] telnet www.altavista.com 80Trying 204.152.190.69...
Connected to altavista.com.
Escape character is ’ˆ]’.
GET /- - -
<img src="/av2/gifs/dart.gif" width=8 height=9 hspace=5 vspace=5 align=top><a
<img src="/av2/gifs/dart.gif" width=8 height=9 hspace=5 vspace=5 align=top><a
</font></td></tr></table>
<br>
<table width="100%" cellpadding=0 cellspacing=0 border=0><tr>
<td align=center><font size=-2 face="arial,helvetica" color="#003399">
<a href="/av/content/about.htm">About AltaVista</a> |
<a href="/av/content/help.htm">Help</a> |
<a href="/av/content/questions.htm">Feedback</a> |
<a href="http://www.doubleclick.net/advertisers/altavista/">Advertising Info</a> |
<a href="/cgi-bin/query?pg=addurl">Add a Page</a><br>
<a href="/av/content/disclaimer.htm">Disclaimer</a> |
<a href="/av/content/privacy.htm">Privacy</a> |
<a href="http://image.altavista.com/AV_CopyrightPolicy.htm">Copyright</a> |
<a href="/av/content/av_network.html">International</a> |
<a href="/cgi-bin/query?pg=tmpl&v=pref.html">Set your Preferences</a>
</font></td></tr></table>
</body></html>
Connection closed by foreign host.
Attaching to a web server by telnet for an on-line session
rob@localhost> telnet www.cems.uwe.ac.uk 80Trying 164.11.8.19...Connected to www.cems.uwe.ac.uk (164.11.8.19).Escape character is ’ˆ]’.GET /˜rwilliam/http_spook
Hello, and welcome to the targetfile in this telnet/http file GET exercise.
Connection closed by foreign host.rob@localhost>
Using http/GET in place of ftp/get
CSA Rob Williams CSA ch 15 - p 212Pearson Education (c) 2006
Client broswer
DNSser ver
MultipleGoogleser vers
Index ser verseach with
80 dual Pentium cardswith 2 GB DRAM & 80 GB IDE disks
in cooled racking
Schematic of Google search engine
CSA Rob Williams CSA ch 15 - p 213Pearson Education (c) 2006
Crawlers
Inter net
Fetched pages
Repositor y of web pages(compressed by zlib)
Indexer
Word index storeinverted file
Searchers
hits
Filter andsor ter
results list
Parser
Quer ies
Inter net
wordIDconverter
Indexsor ter
Lexicon
Quer yallocate
Anchors
URL resolver
Documentindex store
URLser ver
Links
PageRank
Google data-flow activity diagram
CSA Rob Williams CSA ch 15 - p 214Pearson Education (c) 2006
Application layer 7 Application program
Presentation layer 6 transfor mationdata for matting
Session layer 5 computer dialoguecontrol
Tr anspor t layer 4 message <=> packets
Networ k layer 3Vir tual circuit
routing controlpacket sequencing
Link layer 2 Flow controlerror/lost block detection
Physical layer 1 Voltage levelsplug pinouts
Communication sub-net layers
ISO Seven Lay er OSI Model
Application
TCP or UDP
IP
Networ k
Application 7
Presention 6
Session 5
Tr anspor t 4
Networ k 3
Link 2
Physical 1
Compar ison of TCP/IP with ISO seven lay ersCSA Rob Williams CSA ch 15 - p 215Pearson Education (c) 2006
CSA Ch 16CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 16 - p 216Pearson Education (c) 2006
16. CSA - Other Networks
IXCTr unk lines IXC
Tr unkExch
LXCLocalExch
LXC
Brr BrrBrr Brr!
IXC
POTS, the traditional telephone networ k
1 2 3
654
7 8 9
#0∗
1209 1336 1477 Hz
697
770
825
941
DTMF, touch-tone signalling key pad
LineInterface
Card
01100101 00111100 11100101 00111101
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Analoguesignal
Digitalsignal
8 bitsev ery 125 µs
Digitization of telephone speech signals
CSA Rob Williams CSA ch 16 - p 217Pearson Education (c) 2006
16
32
48
64
80
96
112
128
V/1V/2V/4V/8V/16 V
Input Speech Signal
Out
put v
alue
Vout =A V in
1 + log Awhere A = 87.6
Non-linear voice compression for transmission
2. 048M64k
=2 x 106
64 x 103 =103
32= 32 channels
Multiplexor Demultplx30 channel TDM trunk line
0 01 12 23 3
28 2829 2930 3031 31
C1 1 2 3 4 5 6 7 24 25 26 27 28 29 30 C1 2 3 4 5 6
1 frame 125 µs
30 conversations
1 slot
8 bit speech sample, 3.9 µs10110110
C2
discrete voicechannels
Time Divison Multiplexing (TDM) for trunk line sharing
CSA Rob Williams CSA ch 16 - p 218Pearson Education (c) 2006
0123456789
9876543210
ControlComputer
ÎnputVoice
Channels
OuputVoice
Channels
SignalChannel
Space division circuit switching with control processor
frame 1 frame 2 frame 3 frame 4 frame 5125 µs time
0123456789
InputVoice
channels
TDM Bus
OutputVoice
channels
0123456789
TDMController
58
58
58
58
58
20
20
20
20
20
84
84
84
84
84
Time Division Circuit Switching
CSA Rob Williams CSA ch 16 - p 219Pearson Education (c) 2006
VLF
300 Hz
LF
30 KHz
MF HF
3 MHz
VHF UHF
300 MHz
SHF EHF
30 GHz
IR
3 THz
Vis
300 THz
UV
coaxcable
opticfibre
gsm
twistedpair
Bands within the electromagnetic spectrum
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1 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0
Carr ierfrequency
AmplitudeModulated
FrequencyModulated
PhaseModulated
Radio wave modulation usingamplitude, frequency and phase techniques
CSA Rob Williams CSA ch 16 - p 220Pearson Education (c) 2006
Basestation
Switch
Radio mast
Switch Switch
Radio cell equipment and interconnection
0.1 - 0.3 GHz VHF Terrestr ial television & radio0.3 - 1.0 GHz UHF Television, GSM mobile (0.9 GHz), packet radio, pagers1.0 - 2.0 GHz Navigation aids, GSM mobile (1.8 GHz)2.4 - 2.5 GHz Shor t range radio control (Bluetooth)3.4 - 3.5 GHz Neighbourhood antennae
Utilization of radio frequency bands
CSA Rob Williams CSA ch 16 - p 221Pearson Education (c) 2006
1
2
5
6
3
7
4
1
2
5
6
3
7
41
2
5
6
3
7
4
1
2
5
6
3
7
4
1
2
5
6
3
7
4
1
2
5
6
3
7
4
Cells with a repeat 7 pattern of radio frequencies
1
3
3
2
2
4
4
A cell arrangement with only repeat 4 pattern
CSA Rob Williams CSA ch 16 - p 222Pearson Education (c) 2006
ADC
DA C
VoiceCodec
Soundswitch
SpeechEncoder
ListenerNoise
SpeechEncoder
Extrapolation
SpeechProcessing
Class 1 CRCConvl CodingRe-order ingInter leavingCipher ing
Burst assemGMSK_mod
EqualizerBurst Disass
De-cipherDe-inter leave
DecodingClass 1 CRC
Sig Proc
DA C
ADC
RadioModem
PAMXRFilter
LNAMXRFilter
RadioUnit
gsm handset signal processing schematic
VoiceCodecADCDA C
RadioModem
DA CADC
Analog Baseband
PLL
TDMA timer
DSPSpeechEncoder
ControlProcessorProtocol
StackUser
InterfacePeripherals
Control
EqualizerBurst Disass
De-cipherDe-inter leave
DecodingClass 1 CRC
Memor y :
RAMFLASHROM
LCDdisplay
Ke ypad
SIM card
Radio Transceiver Unit
gsm handset functional modules
CSA Rob Williams CSA ch 16 - p 223Pearson Education (c) 2006
0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425
0 1 2 3 4 5 6 7
T3
Voice57
C1
TS26
C1
Voice57
T3
Gd8.25bits
577 µs time slot
4.616 ms TDM frame
120 ms TCh Multiframe
Packet str ucture for gsm voice transmissions
1 2 3 4 1 2 3 4 1 2 3 4
Circuit Switching Vir tualCircuit Switching
DatagramPacket Switching
Switch:
CircuitSet up
Voicedata
CircuitClosed
PathArranged
PacketsTr ansfer
PathClosed
PacketsSent
MessageComplete
Circuit switched vs. packet switched message timing
CSA Rob Williams CSA ch 16 - p 224Pearson Education (c) 2006
Header5 bytes
Pa yload48 bytes
VPIVPI VCI ECC
The ATM frame structure
ATMSwitch
ATMSwitch
155 Mbps ATM trunk line
0 01 12 23 3
28 2829 2930 3031 31
Schematic ATM router switch
01
0
1
155 Mbps
01
01
0
4
111 111 111
155 Mbps
01
2
301
01
1
5
01
4
501
01
2
6
01
6
701
01
3
7
10101000111000 111
ATM data cell
data payload addr
Interconnection inside an ATM Banynan Switch
CSA Rob Williams CSA ch 16 - p 225Pearson Education (c) 2006
LANATM
switch
ATMswitch
ATM 155 MbpsTr unk Line
ATMswitch
Ser ver
ATMswitch
ATM WAN linking together diverse LANs to for mpar t of the Internet
1 0 1 0 1 0 1 0 1 0 8 frames
Synchronization1.125 sec
Batch1.0625 sec Next Batch
A/C address func CRC P
Digital Paging word for mat
CSA Rob Williams CSA ch 16 - p 226Pearson Education (c) 2006
12 : 01
Enter car number first
Coins
Tariff1hr 40pSun freeSat free
Press forticket
P
Application of packet radio data messaging
NT1ISDNLocal
Exchange
Digital phone
ISDN i/f card
DomesticControl
U T
Networ kter minator
maximum8 devices
customerpremises
Narrow Band ISDN defined interfaces
Tr ansmission Frame48 bits in 250 µsecs
B chan-1 B chan-2 B chan-1 B chan-2
D D D D
2B-1D Narrowband ISDN protocol timing
CSA Rob Williams CSA ch 16 - p 227Pearson Education (c) 2006
0 0 01 1
01 1
01
01 1
01
Data
4B3T, Europe
2B1Q, USA
0001 1011 0101 1010
00 01 10 11 01 01 10
Multi-level baseband encoding
Binar y 3-level codesdata
0 0 0 0 + 0 -0 0 0 1 - + 00 0 1 0 0 - +0 0 1 1 + - 00 1 0 0 + + 0 - - 00 1 0 1 0 + + 0 - -0 1 1 0 + 0 + - 0 -0 1 1 1 + + + - - -1 0 0 0 + + - - - +1 0 0 1 - + + + - -1 0 1 0 + - + - + -1 0 1 1 + 0 0 - 0 01 1 0 0 0 + 0 0 - 01 1 0 1 0 0 + 0 0 -1 1 1 0 0 + -1 1 1 1 - 0 +
Three-level 4B3T encoding table
CSA Rob Williams CSA ch 16 - p 228Pearson Education (c) 2006
PTTLocal
Exchage
DSLModem
ATMSwitch
SplitterSubscr iber line
2.5 Km
SplitterDSL
Modem
Subscr iber premisesLocal Exchange
Office
Voice
Data
Voice
Data
Digital Subscriber Line configuration
............................................................................... .............................................................................................................................................................. ...
...
...
...
...
...
...
...
...
...
................................................. ...............................................................................
........................................
Data down-linkband
Dataup-linkband
Voiceband
Guard bands
Am
plitu
de
Frequency (kHz)0 4 25 160 240 780
Subscr iber line bandwidth allocation for ADSL
CSA Rob Williams CSA ch 16 - p 229Pearson Education (c) 2006
HeadendLocal
TelephoneExchange
PSTNTr unklines
Satellitereceiver
KerbsideNode
KerbsideNode
KerbsideNode
Optic FibreVideo
Voice & data
Coax /Twisted Pair
Twin cable
15 Km 500 m
Set-topbox
Cable TV and telephone distribution scheme
5 750
Digital Outward
60040
59 Analogue TV Channels
54 575
DigitalInward
Telephones
MHz
Bandwidth allocation for a cable TV networ k
CSA Rob Williams CSA ch 16 - p 230Pearson Education (c) 2006
CSA Ch 17CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 17 - p 231Pearson Education (c) 2006
17. CSA - Introduction to Operating Systems, Unix
IBMSer ver
Batch Processing
On-line
Real-timeaw
kgrep
sed
Types of computer operating systems
CSA Rob Williams CSA ch 17 - p 232Pearson Education (c) 2006
BIOS booth/w check
Pr imary Bootstrapfrom disk
Secondar yBootstrap
Unix ker nelloaded
init runssingle user
Multi-user modestar ts
getty processesstar ted
login runson demand
Interactiveuser shell
Unix boot sequence
CSA Rob Williams CSA ch 17 - p 233Pearson Education (c) 2006
Tool Function Example
awk text processing language cat file | awk ’$0 !˜ /ˆ$/ print’cat opens and concatenates files cat header ch_01 | groff -petfH > /tmp/tmp.psdiff file compar ison diff ch_01.a ch_01.becho repeats argument to stdout echo $PATHfind file search utility find ˜ -name "*rob*" -printgrep string (reg expr) search grep "rob" /etc/passwdlpr print demon lpr -Pnts -#25 ˜/Sheets/unix_introls directory listing ls -almore text viewer more book.txtps process listing ps -afsed stream editor sed ’s/r-williams/rob.williams/g’ <file1 >file2sor t str ing sor ter cat file | sort +1 -2spell spell checker spell letter.txttr transpose strings tr -cs ’A-Za-z’ ’\012’troff text for matter groff -petfHuniq repeated line detector sor t | uniq -c | sort -nusers networ k users list users > checkfilewc file sizer wc -w assignment.txtwho local user list who
Some Unix tools
Computer hardware
Devicedr ivers
Memor yallocation
Taskdispatcher
Filemanager
Graphicpr imitives
API GUI or Shell
Scheduler
Tools Applications
Typical operating system layered structure
CSA Rob Williams CSA ch 17 - p 234Pearson Education (c) 2006
PID - process id
UID - owner
Process State
Semaphore ID
Signal ID
Memor y needs
CODE SEG pointer
STACK SEG pointer
DATA SEG pointer
Pr ior ity
Accountinginfor mation
File descriptors
Currentdirector y
Task Queuepointers
Summar y contents of a TCB
CSA Rob Williams CSA ch 17 - p 235Pearson Education (c) 2006
Task 1Control Block
Taskstackarea
Taskcode
Task 2Control Block
Taskstackarea
Taskcode
Task 3Control Block
Taskstackarea
Task 4Control Block
Taskstackarea
Taskcode
Tasks specified by their control blocks
CSA Rob Williams CSA ch 17 - p 236Pearson Education (c) 2006
TCB 1
Taskstackarea
Taskcode
TCB 2
Taskstackarea
Taskcode
TCB 3
Taskstackarea
Taskcode
TCB 4
Taskstackarea
Taskcode
Task Control Block queue
CSA Rob Williams CSA ch 17 - p 237Pearson Education (c) 2006
Ready Executing I/O Blocked
Waiting Zombie
Process
Forked
Exit
i/o wait
Terminated
ConditionwaitFreed
dataready
Timed out
Dispatched
State Diagram showing the task lifecycle
rob@olveston [100] rlogin millyLast login: Wed Mar 29 19:22:33 fromrob@milly [41]rob@milly [41] ps -A | wc -l
450rob@milly [42]rob@milly [42] logoutConnection closed.rob@olveston [101]rob@olveston [101] ps -A | wc -l
55rob@olveston [102]
Using ps & wc to count running tasks
CSA Rob Williams CSA ch 17 - p 238Pearson Education (c) 2006
UID (f,l) The effective user ID number of the process(the login name is printed under the -f option).
PID (all) The process ID of the process(this number is used when killing a process).
PPID (f,l) The process ID of the parent process.
STIME (f) The star ting time of the process, givenin hours, minutes, and seconds.(A process begun more than 24 hours before the psinquir y is displayed in days and months)
TTY (all) The controlling terminal for the process("?" is shown when there is no controlling terminalas for background or daemon processes)
TIME (all) The cumulative execution time for the process.CMD (all) The command name.
(the full command name and its arguments, up to alimit of 80 chars, are printed with the -f option).
S (l) The state of the process, (use the -f option):O Process is running on a processor.S Sleeping: process is waiting for an
ev ent to complete.R Runnable: process is on run queue.Z Zombie state: process terminated and
parent is not waiting.T Process is stopped, either by a job control
signal or because it is being traced.C (f,l) Processor utilization for scheduling.
Not printed when the -c option is used.
Infor mation in the ps display, from the man page
Time-slicingDemand preemptionCooperativeInterr upt dr iven
Process scheduling techniques
CSA Rob Williams CSA ch 17 - p 239Pearson Education (c) 2006
rob@olveston [141] ps -AfUID PID PPID C STIME TTY TIME CMDroot 0 0 0 Mar 16 ? 0:01 schedroot 1 0 0 Mar 16 ? 0:02 /etc/init -root 2 0 0 Mar 16 ? 0:00 pageoutroot 3 0 0 Mar 16 ? 3:39 fsflushroot 322 297 0 Mar 16 ? 145:37 /usr/openwin/bin/Xsun :0 -nobanroot 122 1 0 Mar 16 ? 0:00 /usr/sbin/inetd -sroot 318 1 0 Mar 16 ? 0:00 /usr/lib/saf/sac -t 300root 102 1 0 Mar 16 ? 0:00 /usr/sbin/rpcbindroot 112 1 0 Mar 16 ? 0:00 /usr/sbin/kerbdroot 110 1 0 Mar 16 ? 0:00 /usr/lib/netsvc/yp/ypbindroot 284 1 0 Mar 16 ? 0:02 /usr/sbin/voldroot 226 1 0 Mar 16 ? 0:00 /usr/lib/autofs/automountdroot 240 1 0 Mar 16 ? 0:01 /usr/sbin/cronroot 230 1 0 Mar 16 ? 0:00 /usr/sbin/syslogdroot 249 1 0 Mar 16 ? 0:01 /usr/sbin/nscdroot 259 1 0 Mar 16 ? 0:01 /usr/lib/lpschedroot 319 1 0 Mar 16 console 0:00 /usr/lib/saf/ttymon -g -h -p olvesroot 274 1 0 Mar 16 ? 0:00 /usr/lib/utmpdroot 292 1 0 Mar 16 ? 0:00 /usr/lib/sendmail -q15mroot 321 318 0 Mar 16 ? 0:00 /usr/lib/saf/ttymon
rwilliam 340 323 0 Mar 16 ? 0:00 /bin/ksh /usr/dt/config/Xsessionroot 325 1 0 Mar 16 ? 0:00 /usr/openwin/bin/fbconsole -d :0
rwilliam 408 407 0 Mar 16 ? 0:00 olwmslaverwilliam 342 340 0 Mar 16 ? 0:00 /bin/ksh /usr/dt/bin/Xsessionrwilliam 388 378 0 Mar 16 ? 0:00 /bin/ksh /usr/dt/config/Xsessionrwilliam 412 1 0 Mar 16 ?? 0:00 /usr/openwin/bin/cmdtool -Wp 0 0rwilliam 378 342 0 Mar 16 ? 0:00 /bin/tcsh -c unsetenv _ PWD;rwilliam 389 388 0 Mar 16 ? 0:00 /bin/ksh /home/staff/csm/csstaff/rwilliam 407 389 0 Mar 16 ? 0:18 olwm -syncpid 406rwilliam 19576 407 0 10:07:01 ?? 0:02 /usr/openwin/bin/xtermrwilliam 415 412 0 Mar 16 pts/3 0:00 /bin/tcshrwilliam 19949 19577 0 14:04:16 pts/5 0:05 ghostview /tmp/tmp.psrwilliam 469 407 0 Mar 16 ? 10:35 /usr/local/bin/emacsrwilliam 1061 1050 0 Mar 16 ? 0:00 (dns helper)rwilliam 553 407 0 Mar 16 ? 0:21 /usr/openwin/bin/filemgrrwilliam 11510 1 0 Mar 22 ? 4:08 /opt/simeon/bin/simeon.orig -u
root 20818 19577 1 18:01:46 pts/5 0:00 ps -Afrwilliam 20304 19949 0 15:31:45 pts/5 0:06 gs -sDEVICE=x11 -dNOPAUSE -dQUIETrwilliam 1050 407 0 Mar 16 ? 14:39 /usr/local/netscape/netscaperwilliam 12251 1 0 Mar 22 ? 0:17 /usr/local/Acrobat4/Reader/sparcsrwilliam 19577 19576 0 10:07:02 pts/5 0:01 tcsh
Displaying Unix task list using ps
CSA Rob Williams CSA ch 17 - p 240Pearson Education (c) 2006
sched: the O/S scheduler, notice the PID value, an impor tant process, following bootinit: startup process from boot time, gets all the other Unix processes startedpageout: virtual memory page handlerfsflush: updates the super block and flushes data to diskXsun: X-window ser verinetd: Internet server daemon, provides remote services such as ftp, telnet, rlogin, talksac: port ser vices access controllerrpcbind: address mapper for remote procedure callskerbd: source of kerberos unique keys, used for networ k user authenticationypbind: NIS distr ibuted password systemvold: file system (volume) management for CDROMs and floppy disk drivesautomountd: daemon to handle remote file system mount/unmout requestscron: schedules tasks to run at particular timessyslogd: system message handler and routernscd: name ser vice cache daemonlpsched: printer service schedulerttymon: monitors ter minal por ts for activityutmpd: user accounting daemonsendmail: Internet mail serverttymon: monitors ter minal por ts for activityksh: Kor n shell user interfacefbconsole: console windowolmslave: Open Look X-window managerksh: second korn shell user interfaceksh: third Korn shell user interfacecmdtool: command-tool window handlertcsh: a tenex shell user interfaceksh: four th Korn shellolwm: Open Look Window Managerxter m: X ter minal windowtcsh: a tenex shell user interfaceghostview; PostScr ipt screen vieweremacs: the best editor!dns: domain naming service for Internet name to IP number conversionsfilemgr: drag ’n drop file manager, useful for floppy diskssimeon: mail clientps: this produced the process listing!gs: ghostscript translatornetscape: Netscape Navigator Web browseracroread: Adobe Acrobat reader for viewing pdf documentstcsh: another user interface shell
Common Unix processes
CSA Rob Williams CSA ch 17 - p 241Pearson Education (c) 2006
Task 1 Task 2 Task 3 Task 4
Piping data between tasks in Unix
rob> world > hello.txt
rob> echo "Hello world!" > world.txt
rob> tr "\r" < ch_10.asc > ch_10
rob> cat header ch_* > book
rob> cat > letter << +++? Dear Craig,? Here is the book that I promised to send? Rob? +++
rob>
Redirecting data from tasks and files in Unix
Unixprocess
Stdin
0
Stdout
1
Stderr2
Standard I/O for Unix processes
WAIT(sem_buff). . . .//critical region code. . . .
SIGNAL(sem_buff);
Semaphore operators, WAIT and SIGNAL
CSA Rob Williams CSA ch 17 - p 242Pearson Education (c) 2006
WRITER Taskproduce a new item for Consumer TaskWAIT(sem_space)WAIT(sem_free)place item on buffer queue
SIGNAL(sem_free)SIGNAL(sem_data)
END_WRITER
READER TaskWAIT(sem_data)WAIT(sem_free)take item from buffer queueSIGNAL(sem_free)SIGNAL(sem_space)
process the itemEND_READER
Semaphores protecting a cyclic data buffer
#include <stdio.h>#include <signal.h>#define MYSIG 44
/* Signal handler function, evoked by sig 44reinstalls after each sig hit, prints number of hits
*/void getsig(int s)static int count = 0;printf("signal %d again, %dth time \n", s, ++count);signal(MYSIG, getsig);
/* Process to demonstrate signals, sets up a sig handler tocount the number of sig hits received. Loops forever.Start using "kbdcnt &" and make note of pid value returnedRecommend to use "kill -44 pid" to send signalsRemove using "kill -9 pid"
*/int main(void)signal(MYSIG, getsig);printf("start counting kbd kills\n");while(1) ;return 0;
Unix signal handler to count and display signal hitsCSA Rob Williams CSA ch 17 - p 243Pearson Education (c) 2006
rob [262]rob [263] gcc kbdcnt.crob [264] a.out &[1] 9539rob [265] start counting kbd killskill -44 9539rob [266] signal 44 again, 1th timekill -44 9539rob [267] signal 44 again, 2th timekill -44 9539rob [268] signal 44 again, 3th timekill -44 9539rob [269] signal 44 again, 4th time
compile the code
run kbdcnt process
send signal 44
Kill kbdcnt
signal44
Using a signal to notify a Unix process
CSA Rob Williams CSA ch 17 - p 244Pearson Education (c) 2006
#include <stdio.h>#include <signal.h>#include <errno.h>
#define PSIG 43 /* check the value of NSIG in *//* /usr/include/sys/signal.h */
#define CSIG 42 /* before choosing the signal values */
int ccount = 0;int pcount = 0;char str[] = "error message ";
void psigfunc(int s)
pcount++;signal(CSIG, psigfunc);
void csigfunc(int s)
ccount++;signal(PSIG, csigfunc);
main()int ke, tpid, ppid, cpid;
ppid = getpid();cpid = fork(); /* spawn child process */if ( cpid == -1)
printf("failed to fork\n");exit(1);
Continues
CSA Rob Williams CSA ch 17 - p 245Pearson Education (c) 2006
Parent Child
PSIG 43
CSIG 42
if (cpid == 0 )/* Child process executes here */
signal(PSIG, csigfunc);printf("Child started\n");while (1)
pause();printf("Child hit! count = %d\n",ccount);sleep(rand()%10);if( (kill(ppid, CSIG)) ) perror(str);
else/* Parent process continues execution from here */
signal(CSIG, psigfunc);printf("Parent started\n");while (1)
sleep(rand()%10);if( (kill(cpid, PSIG)) ) perror(str);pause();printf("Parent hit! count = %d\n",pcount);
Demonstrating the use of Signals by Unix Processes
rob@olveston [52] a.outChild startedParent startedChild hit! count = 1Parent hit! count = 1Child hit! count = 2Parent hit! count = 2Child hit! count = 3Parent hit! count = 3Child hit! count = 4Parent hit! count = 4Child hit! count = 5ˆCrob@olveston [53]
Signal demonstrator program running on UnixCSA Rob Williams CSA ch 17 - p 246Pearson Education (c) 2006
pid 469Parent
pid 469Parent
pid 472Child
fork
main() cpid = for k();
main() . . . . . .. . . . . .
else Parent continues
. . . . . . .
main() . . . . . .
if (cpid == 0 ) Child processstar t executing
. . . . . .
rob@olveston [40] trial &rob@olveston [41] ps
PID TTY TIME CMD451 pts/4 0:00 tcsh469 pts/4 0:02 trial
rob@olveston [42]
rob@olveston [43] psPID TTY TIME CMD451 pts/4 0:00 tcsh469 pts/4 0:02 trial472 pts/4 0:02 trial
rob@olveston [44]
Unix process creation using fork( )
Segmentnumber
Pagenumber Displacement
Vir tual Address
Seg TableReg
Segment table Page table
Vir tual to physical address translation
sh Original shell from Steve Bour necsh C shell from Bill Joybash borne again shelltcsh Tenex shell, my favour iteksh Kor n shell, ver y popular
Interactive Unix Shells
CSA Rob Williams CSA ch 17 - p 247Pearson Education (c) 2006
rob [52] grep "ofthe" ‘ls | egrep "ch_.." ‘ch_01: symbiosis established ofthe hardware and soft
ch_11:as little as it is, the start ofthe applicatio
rob [53]
rob [53] mail ‘cat mail_list‘ < messagerob [54]
rob[54] echo "There are ‘who | wc -l‘ users logged in at ‘date‘"There are 12 users logged in at Tue June 20 20:23:55 BST 2000
rob [55]
Examples of shell command substitution
echo "hello other window" > /dev/pts/0
value specifieswhich x-window
to send to0, 1, 2...
CSA Rob Williams CSA ch 17 - p 248Pearson Education (c) 2006
rob@olveston [154] ls /dev
arp icmp ptmajor ptyq5 ptyrd syscon ttypc ttyr4audio ie ptmx ptyq6 ptyre systty ttypd ttyr5audioctl ip pts ptyq7 ptyrf tcp ttype ttyr6bdoff ipd ptyp0 ptyq8 qe term ttypf ttyr7be ipdcm ptyp1 ptyq9 rawip ticlts ttyq0 ttyr8conslog ipdptp ptyp2 ptyqa rdiskette ticots ttyq1 ttyr9console isdn ptyp3 ptyqb rdiskette0 ticotsord ttyq2 ttyracua kbd ptyp4 ptyqc rdsk tnfctl ttyq3 ttyrbdiskette kmem ptyp5 ptyqd rfd0 tnfmap ttyq4 ttyrcdiskette0 kstat ptyp6 ptyqe rfd0a tty ttyq5 ttyrddsk ksyms ptyp7 ptyqf rfd0b ttya ttyq6 ttyredtremote le ptyp8 ptyr0 rfd0c ttyb ttyq7 ttyrfdump llc1 ptyp9 ptyr1 rmt ttyp0 ttyq8 udpecpp0 log ptypa ptyr2 sad ttyp1 ttyq9 volctles logindmux ptypb ptyr3 sehdlc ttyp2 ttyqa winlockfb m640 ptypc ptyr4 sehdlc0 ttyp3 ttyqb wsconsfb0 md ptypd ptyr5 sehdlc1 ttyp4 ttyqc zerofbs mem ptype ptyr6 sound ttyp5 ttyqdfd mouse ptypf ptyr7 sp ttyp6 ttyqefd0 null ptyq0 ptyr8 spcic ttyp7 ttyqffd0a openprom ptyq1 ptyr9 stderr ttyp8 ttyr0fd0b partn ptyq2 ptyra stdin ttyp9 ttyr1fd0c printers ptyq3 ptyrb stdout ttypa ttyr2hme profile ptyq4 ptyrc swap ttypb ttyr3rob@olveston [155]
Unix device drivers in directory /dev
CSA Rob Williams CSA ch 17 - p 249Pearson Education (c) 2006
rob@olveston [101] more /etc/termcap. . . . .
xterm|vs100|xterm terminal emulator (X Window System):\:AL=\E[%dL:DC=\E[%dP:DL=\E[%dM:DO=\E[%dB:IC=\E[%d@:U:al=\E[L:am:\:bs:cd=\E[J:ce=\E[K:cl=\E[H\E[2J:cm=\E[%i%d;%dH:co#8:cs=\E[%i%d;%dr:ct=\E[3k:\:dc=\E[P:dl=\E[M:\:im=\E[4h:ei=\E[4l:mi:\:ho=\E[H:\:is=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l:\:rs=\E[r\E[m\E[2J\E[H\E[?7h\E[?1;3;4;6l\E[4l\E<:\:k1=\EOP:k2=\EOQ:k3=\EOR:k4=\EOS:kb=ˆH:kd=\EOB:ke=\E:kl=\EOD:km:kn#4:kr=\EOC:ks=\E[?1h\E=:ku=\EOA:\:li#65:md=\E[1m:me=\E[m:mr=\E[7m:ms:nd=\E[C:pt:\:sc=\E7:rc=\E8:sf=\n:so=\E[7m:se=\E[m:sr=\EM:\:te=\E[2J\E[?47l\E8:ti=\E7\E[?47h:\:up=\E[A:us=\E[4m:ue=\E[m:xn:
Unix termcap entry for an Xterm
CSA Rob Williams CSA ch 17 - p 250Pearson Education (c) 2006
Code Arg Padding Functional str (P*) add new blank lineam bool ter minal has automatic marginsbs bool (o) terminal can backspace with ˆHcd str (P*) clear to end of displayce str (P) clear to end of linecl str (P*) clear screen and home cursorcm str (NP) cursor move to row m, column ncs str (NP) change scroll region to lines m thro nct str (P) clear all tab stopsdc str (P*) delete characterdl str (P*) delete lineim str enter insert modeho str (P) home cursor
%d decimal number starting at 0%2 same as %2d%3 same as %3d%. ASCII equiv%+v adds x then taken as %%>xy if value is >x; then add y. no transmission%r reverse order of rows/columns%i origin is at 1,1 not 0,0%% gives a single %%n XOR row and column (??)%B BCD format%D reverse coding
Some Unix termcap metacodes
CSA Rob Williams CSA ch 17 - p 251Pearson Education (c) 2006
CSA Ch 18CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 18 - p 252Pearson Education (c) 2006
18. CSA - Windows XP
User Applications
Win NT Subsystems
Native API
NTExecutive
NTKernel
HALHardware Abstraction Layer
Hardware
User Mode
Kernel Mode
Windows-NT/XP structure
Applications
Winr32Subsys
OS/2Subsys
PosixSubsys
DOSSubsys
Native API
NTKernel
Win32 and the Ker nel
CSA Rob Williams CSA ch 18 - p 253Pearson Education (c) 2006
Displaying the PC task list using the Task Manager
CSA Rob Williams CSA ch 18 - p 254Pearson Education (c) 2006
Registr y Editor windows displayed
HKEY_LOCAL_MACHINE holds the hardware configuration, installed device drivers,networ k protocols, software classes.
Configconfiguration parameters for local computerEnum device configurationHardwareser ial por t configurationNetwor kuser login infor mationSecur ityremote administration permissionsSoftwareinstalled softwareSystembooting infor mation
HKEY_CURRENT_CONFIG holds the current hardware configuration, where options exist
HKEY_CLASSES_ROOT holds document types, file associations, shell interface
HKEY_USERS holds login users’ software preferences and desktop configuration
HKEY_CURRENT_USER holds copies of the preferences of the curent user.
Registr y top level keys
CSA Rob Williams CSA ch 18 - p 255Pearson Education (c) 2006
Setting networ k Shares and Per missions to a directory
User name 20 charPasswords 14 charMachine name 15 charWorkgroup names 15 charShare names 12 char
Discrepency in effective str ing lengths
CSA Rob Williams CSA ch 18 - p 256Pearson Education (c) 2006
Installing a shared directory as a local virtual drive
CSA Rob Williams CSA ch 18 - p 257Pearson Education (c) 2006
CSA Ch 19CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 19 - p 258Pearson Education (c) 2006
19. CSA - Filing Systems
Data Application Advantages Disadvantagesorganization type
Sequential batch Simple, efficient Maintenanceprocessing difficult data needs sorting
Indexed- batch Sequential and Index takes upsequential processing direct access space
no data sorting less efficient
Direct on-line No data sorting Space inefficientfast access inconvenient to use
Database on-line flexible Perfor mance pooraccess maintenance
costs
Data filing and databases
Windows file browser showing the file hierarchyCSA Rob Williams CSA ch 19 - p 259Pearson Education (c) 2006
Sun File Manager display with floppy disk browser
Master Par titionBoot Record
Pr imary Par tition
Secondar yPartitions
Hard Disk with Four Par titions
CSA Rob Williams CSA ch 19 - p 260Pearson Education (c) 2006
Cylinder 0 Cylinder 1 Cylinder 22 Cylinder 53 Cylinder 120
Platter 0
Platter 1
Platter 2
Platter 3
0 6 5 7 3 1 4 2
5 7
3 2
1 4
Dr ive spindle
Alter native lay outs for blocks 1, 2, 3, 4, 5 & 7to reduce access times (Head Movement Delays)
CSA Rob Williams CSA ch 19 - p 261Pearson Education (c) 2006
Program to checkPartition Tableand transfer toBoot Par tition
Code
PartitionTable
AA55HSignature
Partition 1
Partition 2
Partition 3
Partition 4
Sector Size Contentstar t bytes
00H01H04H05H08HOCH
131344
Boot flagStar t of partition
System FlagEnd of Par titionStar t of Sector
# sectors
H7 H6 H5 H4 H3 H2 H1 H0
C9 C8 S6 S5 S4 S3 S2 S1 S0
C7 C6 C5 C4 C3 C2 C1 C0
Head, Cylinder, Sector
Boot Flag - 00H Inactive (nonbootable),80H Active (bootable)
System Flag -01H FAT-1204H FAT-1605H Extended DOS partition08H AIX0AH OS/20BH FAT-32DBH CP/M (!)83H Linux
Disk Master Par tition Boot Record
OS bootloader program
# Hidden Sectors
# Heads
# Sectors / Track
# sectors / FAT
media byte (F8H)
# logical Sectors
# Root DIR entries
# FATS
# Boot Sectors
# Sectors / Cluster
# Bytes / sector
OEM Name/ID
jmp to loader 3 byte
8 byte
2 byte
1 byte
2 byte
1 byte
2 byte
2 byte
1 byte
2 byte
2 byte
2 byte
2 byte
A Par tition Boot Record (non Master)
CSA Rob Williams CSA ch 19 - p 262Pearson Education (c) 2006
file name
file type
owner id
per missions
file size
create date
disk address
diskblock
Essential infor mation for director y entr ies
rob@milly [20]/usr/sbin/mount/ on /dev/dsk/c0t0d0s0 read/write/setuid on Mon Jul 19 08:12:44 2000/usr on /dev/dsk/c0t0d0s3 read/write/setuid on Mon Jul 19 08:12:44 2000/proc on /proc read/write/setuid on Mon Jul 19 08:12:44 2000/dev/fd on fd read/write/setuid on Mon Jul 19 08:12:44 2000/var on /dev/dsk/c0t0d0s4 read/write/setuid on Mon Jul 19 08:12:44 2000/cache/cache1 on /dev/dsk/c0t0d0s7 setuid/read/write on Mon Jul 19 08:13:4/cache/cache2 on /dev/dsk/c0t1d0s7 setuid/read/write on Mon Jul 19 08:13:4/cache/cache3 on /dev/dsk/c0t2d0s7 setuid/read/write on Mon Jul 19 08:13:4/cache/cache4 on /dev/dsk/c0t3d0s7 setuid/read/write on Mon Jul 19 08:13:4/cache/cache5 on /dev/dsk/c0t10d0s7 setuid/read/write on Mon Jul 19 08:13:/opt on /dev/dsk/c0t0d0s6 setuid/read/write on Mon Jul 19 08:13:45 2000/tmp on /dev/dsk/c0t0d0s5 setuid/read/write on Mon Jul 19 08:13:45 2000/tftpboot on /dev/dsk/c0t1d0s0 setuid/read/write on Mon Jul 19 08:13:45 19/home/student/csm/BSc/CRTS/2 on /dev/dsk/c0t1d0s3 nosuid/read/write/quota/home/student/csm/BSc/other on /dev/dsk/c0t1d0s4 nosuid/read/write/quota on/home/student/csm/BA/other on /dev/dsk/c0t1d0s5 nosuid/read/write/quota on/home/student/csm/PhD on /dev/dsk/c0t1d0s6 nosuid/read/write/quota on Mon/home/student/csm/BSc/CRTS/2p on /dev/dsk/c0t2d0s3 nosuid/read/write/quota
. . .
Unix mount table
CSA Rob Williams CSA ch 19 - p 263Pearson Education (c) 2006
Disk Directory: 32 byte entries
filename
fileext
fileattr reser v create
timecreatedate
LBN1st
clusterfile
length
TEST DAT 4 BIOS
LBN
CHS
Disk
8 3 1 10 2 2 2 4 bytes
FFFFH
6
10
7
0
1
2
3
4
5
6
7
8
9
10
FAT
FAT-16 Directory and File Allocation Table
Sector Sectors Cluster Cluster NaxSize per Size Index Volume
Cluster Size Capacity512B 4 2kB 16bits 128MB512B 16 8kB 16bits 512MB512B 32 16kB 16bits 1GB512B 64 32kB 16bits 2GB512B 16 8kB 32bits 32TB
FAT cluster size and volume capacity
CSA Rob Williams CSA ch 19 - p 264Pearson Education (c) 2006
struct stat
dev_t st_dev; /* device holding the relevant directory */
long st_pad1[3]; /* reserve for dev expansion, */
ino_t st_ino; /* inode number */
mode_t st_mode;
nlink_t st_nlink; /* number of active links to the file */
uid_t st_uid; /* file owner’s ID */
gid_t st_gid; /* designated group id */
dev_t st_rdev;
long st_pad2[2];
off_t st_size; /* file size in bytes */
long st_pad3; /* reserve for future off_t expansion */
timestruc_t st_atime; /* last access time */
timestruc_t st_mtime; /* last write time (modification) */
timestruc_t st_ctime; /* last status change time */
long st_blksize;
long st_blocks;
char st_fstype[_ST_FSTYPSZ];
long st_pad4[8]; /* expansion area */
;
Unix file system inode structure
Boot Block
Super Block
inode Blocks
Data Blocks
owner uidgid of owner
file typerwx access modestime of last access
time modifiedtime of inode change
file size
direct 1direct 2direct 3direct 4direct 5direct 6direct 7direct 8direct 9direct 10indirect
double indirecttr iple indirect
Unix inode file access records
CSA Rob Williams CSA ch 19 - p 265Pearson Education (c) 2006
director yname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodp
dirinode
0 inodp1 inodp2 inodp3 inodp4 inodp5 inodp6 inodp7 inodp8 inodp9 inodp
10 inodp11 inodp12 Iinode13 DIinode14 TIinode
Data Block
Data Block
Data Block
indexblock0 dp1 dp2 dp3 dp4 dp5 dp
994 dp995 dp996 dp997 dp998 dp999 dp
Data Block
Data Block
Data Block
pr incipalfile inodetest.c
Unix inode pointers indicating a file’s data blocks
CSA Rob Williams CSA ch 19 - p 266Pearson Education (c) 2006
director yname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodp
binetcusrdevlib
tmpsbinlocalhomepub
/root
dirinode
0 inodp1 inodp2 inodp3 inodp4 inodp5 inodp6 inodp7 inodp8 inodp9 inodp
10 inodp11 inodp12 Iinode13 DIinode14 TIinode
/etc
director yname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodp
uucp
dirinode
0 inodp1 inodp2 inodp3 inodp4 inodp5 inodp6 inodp7 inodp8 inodp9 inodp
10 inodp11 inodp12 Iinode13 DIinode14 TIinode
Config
Data Block
Data Block
Data Block
dirinode
0 inodp1 inodp2 inodp3 inodp4 inodp5 inodp6 inodp7 inodp8 inodp9 inodp10 inodp11 inodp12 Iinode13 DIinode14 TIinode
/stuff
director yname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodpname inodp
rusers
Relating Unix directories to the inode blocks
CSA Rob Williams CSA ch 19 - p 267Pearson Education (c) 2006
MTFHeader
1 fp2 fp3 fp4 fp5 fp6 fp7 fp8 fp9 fp10 fp
Info Name DOSName Secur ity Cluster Pointers
Director yBlock
Data Block
Data Block
Windows-NTFS Master File Table
Read Write/ Execute/delete attach
ownergroupeesany user
File and directory access control options
CSA Rob Williams CSA ch 19 - p 268Pearson Education (c) 2006
str ip 1str ip 6
str ip 2str ip 7
str ip 3str ip 8
str ip 4str ip 9
str ip 5str ip 10
Data Block
RAID 0
1 2 3 4 5
Data Block
RAID 1
1 2 3 4 5
byte 1 byte 2 byte 3 byte 4 CRC
Data Block
RAID 2/3
str ip 1str ip 5
str ip 2str ip 6
str ip 3str ip 7
str ip 4str ip 8
chksumchksum
Data Block
RAID 4
1 2 3 4 5
str ip 1str ip 5str ip 9str ip 13chksum
str ip 2str ip 6
str ip 10chksumstr ip 17
str ip 3str ip 7
chksumstr ip 14str ip 18
str ip 4chksumstr ip 11str ip 15str ip 19
chksumstr ip 8str ip 12str ip 16str ip 20
RAID 5
RAID disk configuations
CSA Rob Williams CSA ch 19 - p 269Pearson Education (c) 2006
rob@olveston [63] ls -al-rwx------ 1 rob csstaff 280 Sep 5 1998 timezone-rwx------ 1 rob csstaff 48 Sep 11 1999 tit-rwx------ 1 rob csstaff 229 Jan 22 1999 to_arthur-rwx------ 1 rob csstaff 25007 Apr 1 1999 unzipit-rwx------ 1 rob csstaff 251 Sep 5 1998 vorc-rwx------ 1 rob csstaff 243 Sep 5 1998 vorcornrob@olveston [64] chmod 666 unziprob@olveston [65] ls -al unzip-rw-rw-rw- 1 rob csstaff 25007 Apr 1 1999 unzipitrob@olveston [66] chmod 000 unzipitrob@olveston [67] ./unzipit./unziput: permission denied.rob@olveston [68] ls -al unzip---------- 1 rob csstaff 25007 Apr 1 1999 unzipitrob@olveston [69] chmod 100 unzipitrob@olveston [70] ./unzipitrob@olveston [71]rob@olveston [71] chmod 711 unzipitrob@olveston [72] ls -al unzipit-rwx--x--x 1 rob csstaff 25007 Apr 1 1999 unzipitrob@olveston [73]
Setting File Access Per missions in Unix
CSA Rob Williams CSA ch 19 - p 270Pearson Education (c) 2006
CSA Ch 20CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 20 - p 271Pearson Education (c) 2006
20. CSA - Visual Output
Display Pixel data Display size Image sizepixels Bytes
Full colour 24 bits 1024 x 768 2.25MBReduced-range colour 8 bits 0.75MBGrey-scale monochrome 8 bits 0.75MBBlack-white monochrome 1 bit 96kB
Data requirements for different display types
Vertical Fly Back
Hor izontal Fly Back
Magnified view ofpixels on the
screen
Bitmapped raster display
Glass frontscreen with
phosphor coatingShadow mask GRB
RGBelectron guns
Shadow mask inside a colour CRT
CSA Rob Williams CSA ch 20 - p 272Pearson Education (c) 2006
Resolution Ver tical Hor izontalscan rate scan rate
Hz kHz640 x 480 60 31.5640 x 480 72 37.8800 x 600 75 46.9800 x 600 85 53.7
1024 x 768 75 60.01024 x 768 85 68.81152 x 864 85 77.61280 x 1024 75 80.01280 x 1024 85 91.2
Nor mal CRT hor izontal and ver tical scan rates
The time period for writing a single pixel onto the screen can be estimated:
160 x 1024 x 768
= 21 ns/pixel
1
0
Control signals
liquid crystal
polar izing filterback plane electrode
polar izing filter
100Hz driver clock
in phaseOFF
out of phaseON
light
Liquid crystal panels
CSA Rob Williams CSA ch 20 - p 273Pearson Education (c) 2006
Twisted nematic LCD panels,showing the polarized, ribbed panels
CSA Rob Williams CSA ch 20 - p 274Pearson Education (c) 2006
.PSdefine Driver [line right 0.3 down 0.1
line left 0.3 down 0.1; line up 0.2]
Base: box wid 6 ht 2 invisline up 2 from Base.swline up 2 from Base.sw+0.4,0line right 0.4 from Base.w+0,0.4line right 0.4 from Base.w-0,0.4 """""image""data" belowcircle rad 0.02 at Base.w+0.2,0line up 0.5 from last circle; arrow right 2 "color#""" above
Palet: box wid 1.2 ht 1ibox wid 1.2 ht 0.2 with .n at Palet.n "RGB Palette"ibox wid 1.2 ht 0.2 with .n at last box.s "table"ibox wid 1.2 ht 0.2 with .n at last box.s "R G B"move up 0.1; line left 1.2move down 0.1line left 0.4; line up 0.2; line left 0.4line up 0.2; line left 0.4line down 0.7 from Palet.s-0.3,0arrow right 1.2 "8 bits" below; [Driver]line right 0.2 from last [].e then up 0.25 then right 0.2box wid 0.6 ht 0.3 invis with .n at last [].s "DACs"line down 0.1 from Palet.s+0.3,0arrow right 0.6 "8 bits" below; [Driver]line right 0.2 from last [].e; line down 0.25; line right 0.2line down 0.4 from Palet.sarrow right 0.9 "8 bits" below; [Driver]line right 0.4 from last [].e then up 0.07 then right 0.4 then right 0.5 up 0.2line down 0.6 "CRT " rjustline left 0.5 up 0.2; line left 0.4; line up 0.07box wid 0.8 ht 0.2 at Base.w+1.1,0.2 "image base"box wid 0.8 ht 0.2 with .n at last box.s-0,0.1 "Y X"arrow <- right 0.2 from last box.e
move down 0.1for i=1 to 2 do
line right 0.1 then up 0.2 then right 0.1 then down 0.2
line right 0.1line from last box.n to last box.sarrow -> left 0.2 from last box.wbox wid 0.6 ht 0.4 invis with .n at last box.s "image pointer""23" at Palet.nw+0,0.2;"0" at Palet.ne+0,0.2box wid 0.5 ht 0.3 invis "Memory" with .nw at Base.sw
.PE
Example pic script
CSA Rob Williams CSA ch 20 - p 275Pearson Education (c) 2006
<?xml version="1.0" standalone="no"?><!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN""http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
<svg width="100%" height="100%" version="1.1" xmlns="http://www.w3.org/2000/svg">
<rect x="250" y="50" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="250" y="200" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="50" y="200" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="450" y="200" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="250" y="350" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="250" y="500" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="50" y="500" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<rect x="450" y="500" rx="20" ry="20" width="150" height="100"style="fill:white;stroke:black;stroke-width:5;opacity:0.5"/>
<line x1="330" y1="150" x2="330" y2="200" stroke="#000000" stroke-width="2" /><line x1="330" y1="150" x2="125" y2="200" stroke="#000000" stroke-width="2" /><line x1="330" y1="150" x2="525" y2="200" stroke="#000000" stroke-width="2" /><line x1="330" y1="300" x2="330" y2="350" stroke="#000000" stroke-width="2" /><line x1="330" y1="450" x2="330" y2="500" stroke="#000000" stroke-width="2" /><line x1="330" y1="450" x2="525" y2="500" stroke="#000000" stroke-width="2" /><line x1="330" y1="450" x2="125" y2="500" stroke="#000000" stroke-width="2" />
<text id="S1" x="280" y="100" font-size="25"> System </text><text id="S2" x="290" y="250" font-size="25"> Body </text><text id="S3" x="100" y="250" font-size="25"> Init </text><text id="S4" x="460" y="250" font-size="25"> Closedown </text><text id="S5" x="410" y="375" font-size="50"> * </text></svg>
An SVG scr ipt, rendered by Firefox
CSA Rob Williams CSA ch 20 - p 276Pearson Education (c) 2006
Intel 740HM64265/25
HM64265/25DB-15 VGAsocket
to monitor
Tw o tieredAGP connector
An SVGA graphics adapter card with AGP interface
Mono 1981 Te xt only mode offered by original 8088 PC
Hercules 1983 First mono graphics card 720 x 348graphics
CGA 1983 first colour (4) graphics card from IBM 320 x 200double horizontal resolution if limited to mono
EGA 1984 16 colour graphics 640 x 350
VGA 1987 EGA compatible16 colour high resolution256 colours 640 x 480256k colours (18 bit/pixel) 320 x 200 (CGA)
SVGA 1990 256 colours (8 bits/pixel) 1024 x 7681995 24 bit true colour (3 bytes/pixel)
XGA 1997 32768 colours (15 bits) 1280 x 1024
Evolving range of standards for screen display
CSA Rob Williams CSA ch 20 - p 277Pearson Education (c) 2006
DVI-I dual standard monitorsocket
1
11
DB-15 SVGA MonitorSocket
Pin # Signal Name Pin # Signal Name Pin # Signal Name1 TMDS Data2- 9 TMDS Data1- 17 TMDS Data0-2 TMDS Data2+ 10 TMDS Data1+ 18 TMDS Data0+3 TMDS Data2/4 Shield 11 TMDS Data1/3 Shield 19 TMDS Data0/5 Shield4 TMDS Data4- 12 TMDS Data3- 20 TMDS Data5-5 TMDS Data4+ 13 TMDS Data3+ 21 TMDS Data5+6 DDC Clock [SCL] 14 +5 V Pow er 22 TMDS Clock Shield7 DDC Data [SDA] 15 Ground 23 TMDS Clock +8 Analog Ver t Sync 16 Hot Plug Detect 24 TMDS Clock -C1 Analog RedC2 Analog GreenC3 Analog BlueC4 Analog Hor iz SyncC5 Analog GND Return
29 pin DVI connector pinout and signal names
Pin SVGA
1 RED
2 GREEN
3 BLUE
4
5 ground
6 RED rtn
7 GREEN rtn
8 BLUE rtn
9 key-pin
10 SYNC rtn
11
12 Mon id
13 H Sync
14 V Sync
15
15 pin SVG connector pinout and signal names
CSA Rob Williams CSA ch 20 - p 278Pearson Education (c) 2006
image
data
24bit colour valueR G B
8 bitsDA Cs
8 bits
8 bitsCRTY X
image pointer
image base reg
23 0
DisplayMemor y
Dr iving a colour screen
image
data
8 bit colour #
00
RGB Palette 04table 03
R G B 0201
8 bitsDA Cs
8 bits
8 bitsCRT
Y X
image pointer
row column
image base reg
23 0
DisplayMemor y
Dr iving a PC screen using a palette table
CSA Rob Williams CSA ch 20 - p 279Pearson Education (c) 2006
Cr ystalOscillator
14.31818 MHz
Pixel
Clock÷ 1024
Screencolumnposition
09
H Sync
Line
Clock÷ 60
Screenrow
position
09
Field
ClockV Sync
Display memor yaddress
019
Address to display memor y
row 1
row 2
row 3
Displaymemor y
65µs
60msRaster control
Synchronization of screen raster with display memor y
CSA Rob Williams CSA ch 20 - p 280Pearson Education (c) 2006
CleanerErase lamp
electron spray
Scanning headMotor
lasersourcePaper Tray
Motor
paper feedHopper Toner
CPUIRQ
PostScr iptInter preterMemor y
I/O
ser ial link from host computer
Laser Printer
For a page represented as a 600 dpi image:
single A4 page image =11x 7x 600x 600
8= 3. 5Mbytes
The same page may be represented by far less data if it is ASCII coded:
Maximum number of characters on an A4 page = 60x 100 = 6000char
The number of characters on a WP page is about 2500, 2.5 Kbytes of ASCII data.
Thus, the compressing ratio would be:
compression ratio =2500
3500000= 0. 0007
Such a size reduction is certainly wor th achieving but OCR software has onlyrecently been improved enough to give acceptably fast and accurate perfor mance.
CSA Rob Williams CSA ch 20 - p 281Pearson Education (c) 2006
** emacs test1.ps
Ghostview, version 1.1newpath270 360 moveto0 72 rlineto72 0 rlineto0 -72 rlinetoclosepath4 setlinewidth
strokenewpath
272 362 moveto0 68 rlineto68 0 rlineto0 -68 rlinetoclosepath.8 setgrayfill
/Times-Roman findfont24 scalefontsetfont280 400 moveto0 setgray(hello!) show
showpage
hello!
PostScr ipt development, script edited by emacs,rendered by ghostview
CSA Rob Williams CSA ch 20 - p 282Pearson Education (c) 2006
** emacs uwe_pacman.ps
Ghostview, version 1.1newpath1 0 0 setrgbcolor200 200 moveto0 160 rlineto160 0 rlineto0 -160 rlineto
closepathfillnewpath
360 280 moveto-80 0 rlineto80 -40 rlinetoclosepath1 setgray
fillnewpath
380 280 105 180 135 arcn48 0 rlineto0 -40 rlinetoclosepath1 setgray
fill/Helvetica findfont68 scalefontsetfont1 setgray255 200 translate90 rotate0 0 moveto(UWE) show
newpath80 -130 120 0 180 arc1 setgray7 setlinewidth
stroke0 0 moveto-90 rotate/Helvetica findfont42 scalefontsetfont1 0 0 setrgbcolor-60 -40 rmoveto(BRISTOL) show
showpage
UW
EBRISTOL
More PostScr ipt, but now in colour!
gs -dNOPAUSE -dBATCH -r1200 -sDEVICE=pdfwrite -sOutputFile=ch_16.pdf ch_16.ps
CSA Rob Williams CSA ch 20 - p 283Pearson Education (c) 2006
rob [57] cat header ch_16 | groff -t -e -p -fH > ch_16.psrob [58] gs -dNOPAUSE -dBATCH -r1200 -sDEVICE=pdfwrite -sOutputFile=ch_16.pdf ch_16.ps. . . .
rob [57] ls -al ch_16*-rw------- 1 rwilliam csstaff 52114 Jul 1 08:42 ch_16
-rwx------ 1 rwilliam csstaff 42253 Jun 28 13:26 ch_16.asc
-rw------- 1 rwilliam csstaff 840398 Jul 1 08:44 ch_16.pdf
-rw------- 1 rwilliam csstaff 1212385 Jul 1 08:43 ch_16.ps
-rw------- 1 rwilliam csstaff 22093 Feb 24 11:07 ch_16d
-rw------- 1 rwilliam csstaff 16437 Nov 5 1998 ch_16d˜
-rw------- 1 rwilliam csstaff 23975 Jun 16 16:42 ch_16˜
. . . .
rob [58] acroread ch_l6.pdf &. . . .
rob [59] ghostview ch_16.ps &. . . .
rob [60]
Compar ing file sizes: ASCII, ps and pdf
CSA Rob Williams CSA ch 20 - p 284Pearson Education (c) 2006
%PDF-1.0
1 0 obj<</Type /Catalog/Pages 3 0 R/Outlines 2 0 R>>endobj
2 0 obj<</Type /OutlinesCount 0>>endobj
3 0 obj<</Type /Pages/Count 1/Kids [4 0 R]>>endobj
4 0 obj<</Type /Page/Parent 3 0 R/Resources <</Font<</F1 7 0 R>>/ProcSet 6 0 R>>/MediaBox [0 0 612 792]/Contents 5 0 R>>endobj
5 0 obj<< /Lengtb 44 >>streamBT/F1 72 Tf100 50 Td (Hello World!) TjETendstreamendobj
6 0 obj[/PDF /Text]endobj
7 0 obj<</Type /Font/Subtype /Type1/Name /F1/BaseFont /Helvetica/Encoding /MacRomanEncoding>>endobjxref0 80000000000 65535 f0000000009 00000 n0000000074 00000 n0000000120 00000 n0000000179 00000 n0000000322 00000 n0000000415 00000 n0000000445 00000 ntrailer<</Size 8/Root 1 0 R>>startxref553%%EOF
The "Hello Wor ld!" example in pdf code
CSA Rob Williams CSA ch 20 - p 285Pearson Education (c) 2006
Viewing the pdf File using Adobe Acrobat
CSA Rob Williams CSA ch 20 - p 286Pearson Education (c) 2006
HyperBase _File Edit View
NewLoadSave
Save AsQuit
Layout of a typical window scheme
CSA Rob Williams CSA ch 20 - p 287Pearson Education (c) 2006
Vir tual Device Inferface (GDI)Bitmaps, Icons & MetafilesCreating WindowsOperating WindowsOn-screen Menu handlingDealing with Mouse and Keyboard EventsHandling Dialog BoxesTimer Events
Threads and Process SchedulingException Messages
Free Memory ManagementDevice handlingPr inting and Text outputFile Management
Data interchange through ClipboardOLE / DDE data interchange
System Parameter Registry ManagementSystem Infor mation
DLL Management functions
Networ k Access Routines
Passing and processing Messages
Audio data management
Win32 API facilities
CSA Rob Williams CSA ch 20 - p 288Pearson Education (c) 2006
#include <windows.h>
int WINAPI WinMain(HINSTANCE a, HINSTANCE b, LPSTR c, int d)
MessageBox(NULL, "Hello Worle!", "WSM", MB_OK);return NULL;
Your first Windows application
CSA Rob Williams CSA ch 20 - p 289Pearson Education (c) 2006
Application Code
Intr insics
Widgets
X-Lib
X-Windows Programming
mm0
mm1
mm2
mm3
mm4
mm5
mm6
mm7080 63
f/pmmx
xmm0
xmm1
xmm2
xmm3
xmm4
xmm5
xmm6
xmm70127
MMX and SSE data registers
CSA Rob Williams CSA ch 20 - p 290Pearson Education (c) 2006
CSA Ch 21CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 21 - p 291Pearson Education (c) 2006
21. CSA - RISC Processors
Applicationcode
OperatingSystem
CUMicrocode
H/w LogicUnits
Functional hierarchy
Sun Microsystems’ UltraSparc II
CSA Rob Williams CSA ch 21 - p 292Pearson Education (c) 2006
1. Single length instruction codes2. Single clock cycle execution period3. Limited arithmetical complexity supported4. Extensive supply of CPU registers5. Limited repetoire of machine instructions6. Only straightforward addressing modes supported7. Hardware support for procedure handling8. No structured data types recognised9. Compiler supplied to support the architecture10. Hardware CU, pipelined decoding11. Simplified interrupt facilities
Pr incipal features of RISC CPUs
1970 1980 1985 1990 1995 2000
1
10
100
1000
i8080
AMD Athlon
i8086
AMD K7
Pentium
i486
Pentium ProPentium II
i386
MHz
Increasing clock speed of microprocessors
CSA Rob Williams CSA ch 21 - p 293Pearson Education (c) 2006
systemstack
MainMemor y
CPUregisters
CPUstack
registers
Stack passing Parameters are pushed up onto thestack before transferr ing control (jumping) to thesubroutine. The subroutine code shares the samestack and can access the parameters through thestack or frame pointer. Copies of VALUE parametersare simply pushed onto the stack, while reference,VAR, parameters are 32 bit addresses pointing backat data. Stack frame setup overheads, and accesstimes to non-local var iables within scope are an issue.
Register passing Using CPU registers to hold theparameters is the fastest method, but limited by thenumber and size of registers available. Compilersselect this technique only if a couple of simple(integer, char) var iables are to be passed IN, and forthe single OUT return value from functions.
Register windows This is a specialised stacktechnique used by SPARC processors to reduce theamount of stack PUSHing and POPping. Byphysically overlapping the stack frames for adjacentprocedures, some of the local var iables can be visibleas parameters with no data copying. To fur ther speedup the process, SPARC CPUs have fast stack caches.
Parameter blocks For machines without stacks, theproblem of where to save the return address is solvedby the CALL instruction inserting the return address atthe top of the procedure code before transferr ingcontrol. The parameters are cunningly inserted in ablock immediately after the CALL instruction, thusgiving the procedure access by using the returnaddress as a pointer.
Global access Fortran and BASIC would rely onglobal data blocks visible to all code. This system ofmemor y parameter blocks has been reinstituted forgraphics and Windows programming, where thenumber of parameters is so great that little else couldbe suggested.
Variety of parameter passing methods
CSA Rob Williams CSA ch 21 - p 294Pearson Education (c) 2006
JMP ADD - - -
NOP JMP ADD - -
NOP NOP JMP ADD -
NOP NOP NOP JMP ADD
NOP NOP NOP NOP JMP
AND NOP NOP NOP NOP
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
System Clock
Fetch Decode Readin Execute Wr iteback
Multi-stage pipeline decoding - parallel processing
IF ID INT
FP
LD/ST
RO WB
1 2 4 5
A 5 stage superscalar achitecture with 3 execution units
CSA Rob Williams CSA ch 21 - p 295Pearson Education (c) 2006
Dependency Description Example Blocked until...TypeData RAW, read after write MOV EAX,10
ADD EBX,EAX EAX is loaded
WAR, write after read MOV EBX,EAXMOV EAX,10 EAX is read
WAW, write after write MUL 100 sequenceADD EAX,10 correct
Control the outcome of a previous CMP AL,’q’instr uction is essential for JZ exit Z flag setan instruction to complete
Resource limited availability of floating-pointhardware resources ar ithmetic unit free
Instr uction pipeline dependencies
CSA Rob Williams CSA ch 21 - p 296Pearson Education (c) 2006
Prefetcher
unit
Instr uctionsfrom
memor y
Pipeline B
Pipeline A
Pipeline C
PC
prefetchbuffer
decoderstage 1
operandread execute store
result
ALU A
ALU B
ALU C
RegisterFile
Use of Register File Store with superscalar processors
CSA Rob Williams CSA ch 21 - p 297Pearson Education (c) 2006
Mapping TableValid Flag Index0123456789
81
31
Register File
r5r6r7r8r9r10r11r12r13r14
Register renaming
ConditionalInstr uctionaddress
Branch Targetaddress
PredictionConfidence
Value
Control Unit Branch Prediction Table
CSA Rob Williams CSA ch 21 - p 298Pearson Education (c) 2006
Version Example Descr iption Pipelinecore
v1 ARM1 Or iginal processor, 26 bit address, 3coprocessor for Beeb
v2 ARM2 32 bit multiplier, coprocessor included 3Acor n Archemedies/A3000
v2a ARM3 on-chip cache, semaphore support with 3sw ap instr uction
v3 ARM6 & ARM7DI 32 bit address, CPSR/SPSR, MMU 3first macro-cell product.
v3M ARM3M enhanced multiply with 64 bit result 3
v4 StrongArm LD/ST for 8/16 bit values, system mode 5iPAQ PDA,
v4T ARM7TDMI Compressed Thumb instruction set, MULA 3used for many mobile handsets
ARM9TDMI 5
v5 XScale 7
v5TE ARM9E & ARM10E better MUL, extra DSP instcns 5
v5TEJ ARM7EJ & ARM926EJ Java option 5
v6 ARM11 8
Histor ic revisions of ARM architectures
CSA Rob Williams CSA ch 21 - p 299Pearson Education (c) 2006
User &system
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15/pc
/lr
/sp
cpsr
-
Fastinterr uptrequest
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
Interr uptrequest
r13_irq
r14_irq
Super visortrap
r13_svc
r14_svc
Undefinedexception
r13_undef
r14_undef
Abor terror
r13_abt
r14_abt
spsr_fiq spsr_irq spsr_svc spsr_undef spsr_abt
ARM CPU registers, showing the alternate sets
CSA Rob Williams CSA ch 21 - p 300Pearson Education (c) 2006
ldr/str
condition2831
012627
#25
P24
U23
B22
W21
L20
Rn1619
Rd1215
offset field011
source/destination registerbase register
load or store operationRindex write back for auto indexing
word or unsigned byte databackwards/forwards, sign bit for displacement
pre/post index, bump pointer before or after data movementoffset type, immediate or register
predicate execution condition (Z, C, N, V)
12 bit displacement (unsigned)011
OR
shift-size711
sh/rot56
04
Rindex03
0
1
Instr uction formats for the ARM ldr & str instr uctions
N31
Z C V Q27
J24 23 8
i F t SVC4 0
Condition codes
Negative value, msb==1Zero value
Carr y outOverflow
SaturatedJazelle
Interr upt enabledFast interrupt enabled
Thumb mode enabled
ARM program status register
CSA Rob Williams CSA ch 21 - p 301Pearson Education (c) 2006
Opcode Mnm Meaning Flag[31-28]0000 EQ equal values Z=10001 NE not equal Z=00010 CS carr y set C=10011 CC carr y clear C=00100 MI negative value N=10101 PL positive value N=00110 VS overflow V=10111 VC no overflow V=01000 HI unsign higher C=1 && Z=01001 LS unsign lower C=0 || Z=11010 GE greater or equal N=V1011 LT less than N!=V1100 GT greater than Z=0 && N=V1101 LE less or equal Z=1 || N!=V1110 AL always1111 NV never use
ARM condition codes
mov Rn, Rm copy data between registers
ldr Rn, [Rm] get a var iable from memorystr Rn, [Rm] put a var iable back in memor y
add R0, R1, R2 add two registers, result in thirdcmp R0, R1 compare two registers
b addr jump to relative location (+_32 MB)bl addr call subroutine (+_ 32MB)mov R15, R14 retur n from subroutine
ldmfd R13!, Rm-Rn pop registers from stackstmfd R13!, Rm-Rn push registers onto stack
ldr Rn, =constantadr Rn, label
Basic "starter" instructions for the ARM processor
CSA Rob Williams CSA ch 21 - p 302Pearson Education (c) 2006
movand/add/sub/cmptst/and/orrrrr/eor/bic
condition2831
002627
#25
opcode2124
S20
Rn1619
Rd1215
operand 2011
destination registeroperand register
set condition status flagsar ithmetic/logic function selector
operand 2 typepredicate execution condition (Z, C, N, V)
Rshift811
04
sh/rot56
14
Rindex03
OR
shift-size711
OR
sh/rot56
04
Rindex03
shift-size811
8 bit immediate data07
0
0
1
opcode Mnm Meaning Effect0000 and logical bit-wise AND Rd = Rn && Op20001 eor logical bit-wise XOR Rd = Rn ˆˆ Op20010 sub subtract Rd = Rn - Op20011 rsb reverse sub Rd = Op2- Rn0100 add ar ithmetic add Rd = Rn + Op20101 adc add with carry in Rd = Rn+Op2+C0110 sbc subtract with carry Rd = Rn-Op2+C-10111 rsc reverse sbc Rd = Op2-Rn+C-11000 tst test Rn && Op21001 teq test equal RN ˆˆ Op21010 cmp compare Rn - Op21011 cmn negated comp Rn + Op21100 orr logical bit-wise OR Rd = Rn || Op21101 mov copy register data Rd = Op21110 bic bit clear Rd = Rn $$ ˜Op21111 mvn negated mov Rd = ˜Op2
sh/rot Effect00 Rn, LSL #shift-size01 Rn, LSR #shift-size10 Rn, ASR #shift-size11 Rn, ASL #shift-size
Instr uction formats for move , ar ithmetic & logical instructions
opcode sh/rot
CSA Rob Williams CSA ch 21 - p 303Pearson Education (c) 2006
The HP iPAQ hx4700 Pocket PC,with XScale PXA 270 processor
HP iPAQ hx2400 PCB. The 420 MHz XScale CPU isshrouded by emission reduction foil
CSA Rob Williams CSA ch 21 - p 304Pearson Education (c) 2006
Intel® PXA270 624MHz processor64 MB Mobile SDRAM128 MB Flash: 2 x 64 Mbyte (Intel RD48F4400L0zb0)Up to 135 Mbyte of memory is available for user applications100 mm transflective TFT VGA 64K color display (480x640)Graphics controller (ATI Mobileon W3220)Touch screen (Texas Instruments TSC2046 /SPI)Touchpad (Synaptics NavPoint module /SPI),Removable & rechargeable Lithium-Ion battery (1800 mAh)Secure Digital (SDIO) slotCompact Flash I & II (CF) slotIrDA por t (Exar XR16L580IL 16550-compatible)WiFi LAN 802.11b capability (Texas Instruments TNETW1100B)Bluetooth (Texas Instruments BRF6150USB)RS232 port, 16550 compatible (PXA270)Integrated microphone, speaker and stereo headset jackAudio codec (AK4641)USB (PXA270)Weight: 186.7 g
HP iPAQ hx4700 series Pocket PC
CSA Rob Williams CSA ch 21 - p 305Pearson Education (c) 2006
Bank Sel line MBytes384 Reserved
3 128 zeros3 RAS/CAS3 128 DRAM bank 33 RAS/CAS2 128 DRAM bank 23 RAS/CAS1 128 DRAM bank 13 RAS/CAS0 128 DRAM bank 02 256 LCD & DMA registers2 256 Expansion & memor y2 256 SCM registers2 256 PM registers
768 Reserved1 CS5 128 Flash/SRAM bank 51 CS4 128 Flash/SRAM bank 40 PSTSEL 256 PCMIA socket 10 !PSTSEL 256 PCMIA socket 00 CS3 128 Flash/SRAM bank 30 CS2 128 Flash/SRAM bank 20 CS1 128 Flash/SRAM bank 10 CS0 128 Flash bank 0
SA1110 StrongARM 4 GByte memory map
Physical Address
FFFF_FFFFH
inter nal to SA1110StrongARM
0000_0000H
CSA Rob Williams CSA ch 21 - p 306Pearson Education (c) 2006
Block diagram for the StrongARM core
IR-0
IR-1
IR-2
IR-3
deco
der
deco
der
Pipeline
Stage 0
Fetch instr
from I-cache
Stage 1
Decode,
reg read,
get branch addr.
Stage 2
Execute
ALU/shift,
LD/ST mem addr.
Stage 3
D-cache LD/ST
Stage 4
Result
wr ite-back
16 KByte
I-cache
Register File
shifter
ALU & multiply
+4
+disp
mux
+4
B-repl
8 KByte
D-cache
0.5 KByte
Minicache
rotate
Wr ite Register
next PC →
op code →
←
branch
offset
immediate
fields
↓
R15/PC↓
reg write
→
LD/ST address
branch
←addr
incr PC
CSA Rob Williams CSA ch 21 - p 307Pearson Education (c) 2006
oscil
oscil
PLL
PLL
RTCOS timer
GP I/O
Intr CntrlPwr MngtRst Contrl
Ser ialchannel 0
USB
Ser ialchannel 1
UART
Ser ialchannel 2
IrDA
Ser ialchannel 3
UART
Ser ialchannel 4CODEC
Br idge
JTAGi/f
LCDcontrol
Memor y& PCMCIA
controlA0-A25D0-D31
DMAcontrol
ARMSA-1core
read buffwr ite buff
Icache
Dcache
Minicache
IMMU
DMMU
3.686 MHz
32.768 KHz
Intel SA1110 StrongARM microcontroller
CSA Rob Williams CSA ch 21 - p 308Pearson Education (c) 2006
LOCAL
IN
OUT
LOCAL
IN
OUT
LOCAL
IN
OUT
CPU registers
LOCAL
IN
OUT
GLOBAL
7
0
31 023
0cwp
system
stackMain Memory
RestoreSave
Operation of the Register File during procedure calls
CSA Rob Williams CSA ch 21 - p 309Pearson Education (c) 2006
CSA Ch 22CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 22 - p 310Pearson Education (c) 2006
22. CSA - The EPIC Itanium processor
L1 Icache 16 kbyte, 64 byte lineL1 Dcache 16 kbyte, 64 byte line, write-throughL2 256 kbyte, 128 byte line, write-backL3 3-9 Mbyte, 128 byte line, write-backmain memory <1 Pbyte (264)Clock 1.66 GHzSystem bus 400 MHz, 128 bits wideCPU power 100 watts
Itanium 2 processor parameters
CSA Rob Williams CSA ch 22 - p 311
Pearson Education (c) 2006
Instr 2
97127
Instr 1
4686
Instr 0
545
Templ
04
Opcode
3740
Field4
2736
Field3
2026
Field2
1319
Field1
612
pred
05
Instr uction Bundle for the IA-64 Architecture
CSA Rob Williams CSA ch 22 - p 312Pearson Education (c) 2006
General Regs
063 0
gr0
gr1
gr2
gr127
gr126
gr125
NAT Floating-Point Regs
+ 0.081 0
+ 1.0
Application Regs
KR063 0
ar0
KR7
RSCBSP
BSPstoreRNAT
FCREFLAG
CSDSSD
CFLGFSRFIRFDR
CCV
UNAT
FPSRITC
PFSLCEC
ar127
IP63 0
Predicate Flags63 0
CFM37 0
Branch Regs
br063 0
br1
br2
br3
br4
br5
br6
br7
Intel IA-64 / Itanium Register Set
CSA Rob Williams CSA ch 22 - p 313Pearson Education (c) 2006
Register name title class usageGr0 r0 constant reads as zeroGr1 r1 gp special global data pointerGr2-Gr3 r2-r3 scratch used with addlGr4-Gr7 r4-r7 preservedGr8-Gr11 r8-r11 ret0-ret3 scratch return valuesGr12 r12 sp special stack pointerGr13 r13 tp special thread pointerGr14-Gr31 r14-r31 scratchGr32-Gr39 r32-r39 in0-in7 automatic function paramsGr32-Gr127 r32-r127 automatic input registers
loc0-loc95 automatic local registersout0-out95 automatic output registers
automatic rotating registers(groups of 8)
Asm programmers’ usage of Itanium registers
CSA Rob Williams CSA ch 22 - p 314Pearson Education (c) 2006
TypeA ALU operations, arithmetic on integers and logicI multimedia, integer shifts, special register opsM memor y load/store operationsB branching, jumping and returningF floating-point operationsX special instructions
Itanium instruction classes
CSA Rob Williams CSA ch 22 - p 315
Pearson Education (c) 2006
Template Slot0 Slot1 Slot200 M-unit I-unit I-unit01 M-unit I-unit I-unit ||02 M-unit I-unit || I-unit03 M-unit I-unit || I-unit ||04 M-unit L-unit X-unit05 M-unit L-unit X-unit ||060708 M-unit M-unit I-unit09 M-unit M-unit I-unit ||0A M-unit || M-unit I-unit0B M-unit || M-unit I-unit0C M-unit F-unit I-unit0D M-unit F-unit I-unit ||0E M-unit M-unit F-unit0F M-unit M-unit F-unit ||10 M-unit I-unit B-unit11 M-unit I-unit B-unit ||12 M-unit B-unit B-unit13 M-unit B-unit B-unit ||141516 B-unit B-unit B-unit17 B-unit B-unit B-unit ||18 M-unit M-unit B-unit19 M-unit M-unit B-unit ||1A1B1C M-unit F-unit B-unit1D M-unit F-unit B-unit ||1F M-unit I-unit I-unit
Template field encoding for Itanium 2,showing the positions of inter-instruction stops
CSA Rob Williams CSA ch 22 - p 316Pearson Education (c) 2006
#include <stdio.h>
/* selection_sort.c A good basic sort routine.Works by scanning up through the array finding the "smallest" item, whichit then swaps with the item at the start of the scan. It then scans again,starting at the second position, looking for the next smallest item...and so on.*/
int selectionsort(char *pc[ ], int n ) int min, i, j, k;char *pctemp;
for (i = 0; i < n; i++) min = i;for(j = i+1; j < n; j++)
if (strcmp(pc[j], pc[min]) > 0) min = j;pctemp = pc[min];pc[min] = pc[i];pc[i] = pctemp;for(k=0; k<n; k++)
printf("%s ", pc[k]);printf("\n");
return 0;
void main() int i;char *names[7], *testset[7] =
"Monday", "Tuesday", "Wednesday", "Thursday", "Friday", "Saturday", "Sunday";
for(i=0; i < 7; i++)names[i] = testset[i];
printf("\n\nSelection Sort\n");i = selectionsort(names, 7);
CSA Rob Williams CSA ch 22 - p 317Pearson Education (c) 2006
.file "selection_sort.c"
.pred.safe_across_calls p1-p5,p16-p63
.section .rodata
.align 8.LC0: stringz "%s "
.align 8.LC1: stringz "\n"
.text
.align 16
.global selectionsort#
.proc selectionsort#selectionsort:
.prologue 14, 34
.save ar.pfs, r35alloc r35 = ar.pfs, 2, 4, 2, 0.vframe r36mov r36 = r12adds r12 = -48, r12mov r37 = r1.save rp, r34mov r34 = b0.body;;adds r14 = -32, r36;;st8 [r14] = r32adds r14 = -24, r36;;st4 [r14] = r33adds r14 = -16, r36;;st4 [r14] = r0
.L2: ; FOR i loopadds r14 = -16, r36adds r15 = -24, r36;;ld4 r16 = [r14]ld4 r14 = [r15];;cmp4.gt p6, p7 = r14, r16(p6) br.cond.dptk .L5br .L3;;
.L5: adds r15 = -20, r36adds r14 = -16, r36;;ld4 r14 = [r14];;st4 [r15] = r14adds r15 = -12, r36adds r14 = -16, r36 ; get ipntr;;ld4 r14 = [r14] ; ;;adds r14 = 1, r14 ; incr i;;st4 [r15] = r14 ;
; Exit FOR i loop
.L6: ; FOR j loopadds r14 = -12, r36adds r15 = -24, r36;;ld4 r16 = [r14] ; get npntrld4 r14 = [r15] ; get jpntr;;cmp4.gt p6, p7 = r14, r16(p6) br.cond.dptk .L9br .L7;;
.L9: adds r14 = -12, r36;;ld4 r14 = [r14];;sxt4 r14 = r14;;shladd r15 = r14, 3, r0adds r16 = -32, r36;;ld8 r14 = [r16];;add r16 = r15, r14adds r14 = -20, r36;;ld4 r14 = [r14];;sxt4 r14 = r14;;shladd r15 = r14, 3, r0adds r17 = -32, r36;;ld8 r14 = [r17];;add r14 = r15, r14ld8 r38 = [r16];;ld8 r39 = [r14]br.call.sptk.many b0 = strcmp#mov r1 = r37mov r14 = r8;;cmp4.ge p6, p7 = 0, r14(p6) br.cond.dptk .L8adds r14 = -20, r36adds r15 = -12, r36;;ld4 r15 = [r15];;st4 [r14] = r15
.L8: adds r15 = -12, r36adds r14 = -12, r36;;ld4 r14 = [r14];;adds r14 = 1, r14;;st4 [r15] = r14br .L6;;
; Exit j FOR loop
CSA Rob Williams CSA ch 22 - p 318Pearson Education (c) 2006
.L7: mov r16 = r36 ; get temppntradds r14 = -20, r36;;ld4 r14 = [r14];;sxt4 r14 = r14;;shladd r15 = r14, 3, r0adds r17 = -32, r36;;ld8 r14 = [r17];;add r14 = r15, r14;;ld8 r14 = [r14] ; ;; ; pctemp=pc[min]st8 [r16] = r14 ;
adds r14 = -20, r36;;ld4 r14 = [r14];;sxt4 r14 = r14;;shladd r15 = r14, 3, r0adds r16 = -32, r36;;ld8 r14 = [r16];;add r16 = r15, r14adds r14 = -16, r36 ; get ipntr;;ld4 r14 = [r14];;sxt4 r14 = r14 ; sign extend i;;shladd r15 = r14, 3, r0; i x 8adds r17 = -32, r36;;ld8 r14 = [r17];;add r14 = r15, r14 ; build pntr;;ld8 r14 = [r14] ; ;; ; pc[min]=pc[i]st8 [r16] = r14 ;
adds r14 = -16, r36 ; get ipntr;;ld4 r14 = [r14] ; get i;;sxt4 r14 = r14;;shladd r15 = r14, 3, r0; i x 8adds r16 = -32, r36 ; get pc[] base;;ld8 r14 = [r16];;add r15 = r15, r14 ; build pc[i] pntrmov r14 = r36 ; get pctemppntr;;ld8 r14 = [r14] ; ;; ; pc[i]=pctempst8 [r15] = r14 ;
adds r14 = -8, r36 ; get kpntr;;st4 [r14] = r0 ; zero k
.L11: ; FOR k loopadds r14 = -8, r36 ; get kpntradds r15 = -24, r36;;ld4 r16 = [r14]ld4 r14 = [r15];;cmp4.gt p6, p7 = r14, r16(p6) br.cond.dptk .L14br .L12;;
.L14: adds r14 = -8, r36;;ld4 r14 = [r14];;sxt4 r14 = r14;;shladd r15 = r14, 3, r0adds r17 = -32, r36;;ld8 r14 = [r17];;add r15 = r15, r14addl r14 = @ltoffx(.LC0), r1;;ld8.mov r38 = [r14], .LC0ld8 r39 = [r15]br.call.sptk.many b0 = printf#mov r1 = r37adds r15 = -8, r36 ; get dest kpntradds r14 = -8, r36 ; get src kpntr;;ld4 r14 = [r14] ; ;;adds r14 = 1, r14 ; incr k;;st4 [r15] = r14 ;
br .L11;;
.L12: addl r14 = @ltoffx(.LC1), r1;;ld8.mov r38 = [r14], .LC1br.call.sptk.many b0 = printf#mov r1 = r37adds r15 = -16, r36 ; get Dest ipntradds r14 = -16, r36 ; get Src ipntr;;ld4 r14 = [r14] ; ;;adds r14 = 1, r14 ; incr i;;st4 [r15] = r14 ;
br .L2 ; Bottom of i loop;;
.L3: mov r14 = r0;;mov r8 = r14mov ar.pfs = r35 ; save FPmov b0 = r34.restore spmov r12 = r36br.ret.sptk.many b0;;.endp selectionsort#
; Exit k FOR loop
CSA Rob Williams CSA ch 22 - p 319Pearson Education (c) 2006
.text ; Code Section
.align 16
.global main#
.proc main#main: .prologue 14, 32
.save ar.pfs, r33alloc r33 = ar.pfs, 0, 4, 2, 0.vframe r34mov r34 = r12 ; set FP from SPadds r12 = -144, r12 ; open stack framemov r35 = r1.save rp, r32mov r32 = b0 ; save branch reg.body;;adds r15 = -48, r34 ; build tablepntraddl r14 = @ltoffx(.LC2), r1; build RAM pntr;; ; using offset+base pntrld8.mov r14 = [r14], .LC2;;st8 [r15] = r14 ; save str npntr in tableadds r16 = 8, r15 :bump pntraddl r14 = @ltoffx(.LC3), r1;; ; "Tuesday"ld8.mov r14 = [r14], .LC3;;st8 [r16] = r14 ; save str npntr in tableadds r16 = 16, r15addl r14 = @ltoffx(.LC4), r1;; ; "Wednesday"ld8.mov r14 = [r14], .LC4;;st8 [r16] = r14 ; save str npntr in tableadds r16 = 24, r15addl r14 = @ltoffx(.LC5), r1;; ; "Thursday"ld8.mov r14 = [r14], .LC5;;st8 [r16] = r14 ; save str npntr in tableadds r16 = 32, r15addl r14 = @ltoffx(.LC6), r1;; ; "Fr iday"ld8.mov r14 = [r14], .LC6;;st8 [r16] = r14 ; save str npntr in tableadds r16 = 40, r15addl r14 = @ltoffx(.LC7), r1;; ; "Saturday"ld8.mov r14 = [r14], .LC7;;st8 [r16] = r14 ; save str npntr in tableadds r15 = 48, r15addl r14 = @ltoffx(.LC8), r1;;ld8.mov r14 = [r14], .LC8;; ; "Sunday"st8 [r15] = r14 ; save str npntr in tableadds r14 = -128, r34 ; build ipntr;;st4 [r14] = r0 ; clear i
.L16: ; star t of FOR i loopadds r15 = -128, r34;; ; names[]=testset[]ld4 r14 = [r15] ; get i;;cmp4.ge p6, p7 = 6, r14(p6) br.cond.dptk .L19 ; test end of FOR loopbr .L17;;
.L19: adds r15 = -112, r34; get Destpntradds r16 = -128, r34 ; get ipntr;; ; local var iablesld4 r14 = [r16] ; get i;;sxt4 r14 = r14 ; sign extend;;shladd r14 = r14, 3, r0; i x 8;;add r16 = r14, r15 ; index Destpntradds r15 = -48, r34 ; get Srcpntradds r17 = -128, r34 ; get ipntr;;ld4 r14 = [r17] ; get i;;sxt4 r14 = r14 ; sign extend;;shladd r14 = r14, 3, r0:ix8;;add r14 = r14, r15 ; index Srcpntr;;ld8 r14 = [r14] ; | get next_word;; : |st8 [r16] = r14 ; | put next_wordadds r15 = -128, r34 ; get ipntr;;ld4 r14 = [r15] ; get i;;adds r14 = 1, r14 ; incr iadds r16 = -128, r34 ; get ipntr;;st4 [r16] = r14 ; save ibr .L16 ; bottom of FOR;;
.L17: addl r14 = @ltoffx(.LC9), r1;;ld8.mov r36 = [r14],.LC9; print bannerbr.call.sptk.many b0 = printf#mov r1 = r35 ; retur n valueadds r14 = -112, r34 ; get Destpntr;;mov r36 = r14 ; param1=Destpntraddl r37 = 7, r0 ; param2=7br.call.sptk.many b0 = selectionsort# ; call sort routinemov r1 = r35 ; get return valuemov r14 = r8adds r17 = -128, r34 ; get ipntr;;st4 [r17] = r14 ; store in imov ar.pfs = r33mov b0 = r32 ; restore branch addr.restore spmov r12 = r34 ; restore SPbr.ret.sptk.many b0 RETURN to shell;;.endp main#.ident "GCC: (GNU) 3.3.5 (Debian 1:3.3.5-13)"
CSA Rob Williams CSA ch 22 - p 320Pearson Education (c) 2006
.section .rodata ; Constants Section
.align 8.LC2: stringz "Monday"; constant strings store
.align 8.LC3: stringz "Tuesday"
.align 8.LC4: stringz "Wednesday"
.align 8.LC5: stringz "Thursday"
.align 8.LC6: stringz "Friday"
.align 8.LC7: stringz "Saturday"
.align 8.LC8: stringz "Sunday"
.align 8.LC9: stringz "\n\nSelection Sort\n"
Itanium assembler code produced by gcc
CSA Rob Williams CSA ch 22 - p 321Pearson Education (c) 2006
Linux-64 with gvd/gdb debugger to watch Itanium code
Registerswindow
Source codewindow
Disassemblerwindow
gdbwindow
Browserwindow
Call stackwindow
CSA Rob Williams CSA ch 22 - p 322Pearson Education (c) 2006
CSA Ch 23CSA
ComputersFetch-execute cycleHardware
CPUAr ithmetic Logic UnitControl UnitRISC featuresARM processorPentiumItanium
Input-outputParallel communicationSer ial communication
Networ kingLocal Area Networ ks
Ether netUSB
Wide Area Networ ksOther Networ ks
Point to pointVisual output
Memor yMemor y hierarchyCache and main memoryDisk filing
Parallel processingSoftware
Operating systemsUnixMS Windows
ToolsCompilers and assemblers
Subroutines and stacksWIMPs
Users’ viewpointsHardware engineerHLL programmerSystems administratorSystems programmer
CSA Rob Williams CSA ch 23 - p 323Pearson Education (c) 2006
23. CSA - Parallel Processing
Program has N instructionsInstr uctions take τ secs each to completeUni-processor run time will be N x τIDEALLY, P processors could reduce run time to (Nτ )/P
But only a fraction of real application code can be parallelized:
total_time = serial_part + parallel_part = Nτ f +Nτ (1 − f )
PWhile f is the fraction of the problem that must be carried out sequentially due todata or control dependencies, (1 − f ) is the fraction which can run in parallel. Notethat f + (1 − f ) evaluates to 1. P is the number of processors available.
The speed-up-ratio is then defined as the uni-processor-time divided by the(smaller!) multi-processor-time, which is:
speed _up_ratio: S =Nτ
Nτ f +Nτ (1 − f )
P
=1
f + (1 − f )/P
Parallelizable code, Amdahl’s Law
CSA Rob Williams CSA ch 23 - p 324Pearson Education (c) 2006
0.9
0.7
0.5
0.30.1
0.8
fraction parallelcode, (1-f )
x1
x2
x3
x4
x5
x6
2 4 6 8 10 12 14
S,s
peed
-up
ratio
P , number of CPUs
Amdahl’s Law plotted for 1-15 processors and0.1 - 0.9 compliant code
CSA Rob Williams CSA ch 23 - p 325Pearson Education (c) 2006
Instr uction Datastream stream
SISD Single Single Personal PC word processingSIMD Single Multiple Vector processors geological simulationMISD Multiple Single Possibly none.MIMD Multiple Multiple Central server WWW search engine
Flynn’s processor taxonomy
System bus
sharedmemor y
CPU2CPU1 CPU3
memor y
data
CPU2
cache
CPU1
cache
CPU3
cache
sharedmemor y
CPU2
cache
localmemor y
CPU1
cache
localmemor y
CPU3
cache
localmemor y
copies
Single bus, shared memory multi-processing (SMP)
Cache event Action
Read Hit cache readMiss main memor y read
cache update
Wr ite Hit main memor y wr itecache marked stale
Miss main memor y wr ite
Cache coherency protocol with write-through
CSA Rob Williams CSA ch 23 - p 326Pearson Education (c) 2006
CPU2
cache
localmemor y
CPU1
cache
localmemor y
CPU3
cache
localmemor y
CPU4
cache
localmemor y
CPU5
cache
localmemor y
CPU6
cache
localmemor y
Hardware configuration for an MPI system
int MPI_Send( void* sendBuf,int count,MPI_Datatype datatype,int destinationRank,int tag,MPI_Comm comm)
int MPI_Recv( void* recvBuf,int count,MPI_Datatype datatype,int sourceRank,int tag,MPI_Comm comm,MPI_Status *status)
int MPI_Bcast ( void* buffer,int count,MPI_Datatype datatype,int root,MPI_Comm comm )
CSA Rob Williams CSA ch 23 - p 327Pearson Education (c) 2006
256 kbyte
Localstorage
Frontend
StorageLogic
ControlLogic
ExecutionLogic
I-fetch
Decode
Dispatch
Vper mL/SUSCUBU
Vector arithmetic units
SPU1 SPU2 Byte FX1 FX2
Controlunit
R-commit
The IBM/Sony Cell SPE unit
CSA Rob Williams CSA ch 23 - p 328Pearson Education (c) 2006
64 bitPo werPC
32 kB L1
512 kB L2
SPE 0
SPE 1
SPE 2
SPE 3
SPE 4
SPE 5
SPE 6
SPE 7
BICFlexIO
MIC2x XDR
Cell schematic architecture
SwitchingHub
workstations
A single switched hub Cluster with Star topology
CSA Rob Williams CSA ch 23 - p 329Pearson Education (c) 2006
Inter net Applicationor iginator
workstations
Gr id computing
CSA Rob Williams CSA ch 23 - p 330Pearson Education (c) 2006
5 /1/07
Fr i Jan 5 00:09:48 GMT 2007
localhost
CSA Rob Williams CSA ch 23 - p 331
Pearson Education (c) 2006