CS61C L20 Single-Cycle CPU Control (1) Beamer, Summer 2007 © UCB Scott Beamer Instructor...

CS61C L20 Single-Cycle CPU Control (1) Beamer, Summer 2007 © UCB

Scott Beamer

Instructor

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures

Lecture #20 – Controlling a Single-Cycle CPU

2007-7-30

Black Hat Conference Kicks Off in Vegas


Putting it All Together:A Single Cycle Datapath

imm16

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrEqual

Instruction<31:0><21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRtRs

clk

PC

00

4

nPC_sel

PC

Ext

Adr

InstMemory

Ad

derA

dder

Mu

x

01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


Review: A Single Cycle Datapath

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der

3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In32

MemWrzero

01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel instrfetchunitclk

• We have everything except control signals


An Abstract View of the Implementation

DataOut

clk

5

Rw Ra Rb

RegisterFile

Rd

Data In

DataAddr Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

PC

5Rs

5Rt

32

323232

A

B

Nex

t A

dd

ress

Control

Datapath

Control Signals Conditions

clk clk

AL

U


Recap: Meaning of the Control Signals• nPC_sel: “+4” 0 PC <– PC + 4

“br” 1 PC <– PC + 4 + {SignExt(Im16) , 00

}• Later in lecture: higher-level connection between

mux and branch condition

“n”=next

imm16

clk

PC

00

4nPC_sel

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

0

1


Recap: Meaning of the Control Signals• ExtOp: “zero”, “sign”

• ALUsrc: 0 regB; 1 immed

• ALUctr: “ADD”, “SUB”, “OR”

° MemWr: 1 write memory° MemtoReg: 0 ALU; 1 Mem° RegDst: 0 “rt”; 1 “rd”° RegWr: 1 write register

32

ALUctr

clk

busW

RegWr

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst

Exten

der 3216imm16

ALUSrcExtOp

MemtoReg

clk

Data In

32

MemWr01

0

1

AL

U 0

1

WrEn Adr

DataMemory

5


RTL: The Add Instruction

add rd, rs, rt•MEM[PC] Fetch the instruction

from memory

•R[rd] = R[rs] + R[rt] The actual operation

•PC = PC + 4 Calculate the next instruction’s address

op rs rt rd shamt funct

061116212631

6 bits 6 bits5 bits5 bits5 bits5 bits


Instruction Fetch Unit at the Beginning of Add• Fetch the instruction from Instruction memory: Instruction = MEM[PC]

• same for all instructions

imm16

clk

PC

00

4nPC_sel

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

InstMemory Instruction<31:0>


Instruction Fetch Unit at the End of Add• PC = PC + 4

• This is the same for all instructions except: Branch and Jump

imm16

clk

PC

00

4nPC_sel=+4

PC

Ext

Ad

derA

dder

Mu

x

Inst Address

InstMemory


The Single Cycle Datapath during Add

R[rd] = R[rs] + R[rt]op rs rt rd shamt funct

061116212631

32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=1

Exten

der

3216imm16

ALUSrc=0ExtOp=x

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=+4 instrfetchunitclk


Single Cycle Datapath during Or Immediate?

op rs rt immediate

016212631

• R[rt] = R[rs] OR ZeroExt[Imm16]

32

ALUctr=

clk

busW

RegWr=

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=

Exten

der3216

imm16

ALUSrc=ExtOp=

MemtoReg=

clk

Data In32

MemWr=

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel= instrfetchunitclk


• R[rt] = R[rs] OR ZeroExt[Imm16]op rs rt immediate

016212631

Single Cycle Datapath during Or Immediate?

32

ALUctr=OR

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=0

Exten

der3216

imm16

ALUSrc=1ExtOp=zero

MemtoReg=0

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs



The Single Cycle Datapath during Load?

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

32

ALUctr=

clk

busW

RegWr=

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=

Exten

der3216

imm16

ALUSrc=ExtOp=

MemtoReg=

clk

Data In32

MemWr=

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs



The Single Cycle Datapath during Load

• R[rt] = Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate

016212631

32

ALUctr=ADD

clk

busW

RegWr=1

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=0

Exten

der3216

imm16

ALUSrc=1ExtOp=sign

MemtoReg=1

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs



The Single Cycle Datapath during Store?

op rs rt immediate

016212631

• Data Memory {R[rs] + SignExt[imm16]} = R[rt]

32

ALUctr=

clk

busW

RegWr=

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=

Exten

der3216

imm16

ALUSrc=ExtOp=

MemtoReg=

clk

Data In32

MemWr=

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs



The Single Cycle Datapath during Store

• Data Memory {R[rs] + SignExt[imm16]} = R[rt]op rs rt immediate

016212631

32

ALUctr=ADD

clk

busW

RegWr=0

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=x

Exten

der3216

imm16

ALUSrc=1ExtOp=sign

MemtoReg=x

clk

Data In32

MemWr=1

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs



Administrivia

• Assignments• HW7 due 8/2

• Proj3 due 8/5

• Assignment Grading• Grades should be coming in now (HW1, HW2 done, expect HW3, HW4, Proj1 soon)

• Reader info posted on webpage

• Midterm Regrades due Wed 8/1


32

ALUctr =

Clk

busW

RegWr =

3232

busA

32busB

55 5

Rw Ra Rb32 32-bitRegisters

Rs

Rt

Rt

RdRegDst =

Exten

der

Mu

x

Mux

3216imm16

ALUSrc =

ExtOp =

Mu

x

MemtoReg =

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr =A

LU

InstructionFetch Unit

Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

• New PC = { PC[31..28], target address, 00 }

nPC_sel=

The Single Cycle Datapath during Jump

op target address02631

J-type jump25

Jump=

<0:25>

TA26


The Single Cycle Datapath during Jump

32

ALUctr =x

Clk

busW

RegWr = 0

3232

busA

32busB

55 5


Rs

Rt

Rt

RdRegDst = x

Exten

der

Mu

x

Mux

3216imm16

ALUSrc = x

ExtOp = x

Mu

x

MemtoReg = x

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr = 0A

LU


Clk

Zero

Instruction<31:0>

0

1

0

1

01<

21:25>

<16:20>

<11:15>

<0:15>

RdRsRt

• New PC = { PC[31..28], target address, 00 }

nPC_sel=?

Jump=1

Imm16

<0:25>

TA26

op target address02631

J-type jump25


Instruction Fetch Unit at the End of Jump

Adr

InstMemory

Ad

derA

dder

PC

Clk

00Mu

x

4

nPC_sel

imm

16

Instruction<31:0>

0

1

Zero

nPC_MUX_sel

• New PC = { PC[31..28], target address, 00 }op target address

02631J-type jump

25

How do we modify thisto account for jumps?

Jump


Instruction Fetch Unit at the End of Jump

Adr

InstMemory

Ad

derA

dder

PC

Clk00

Mu

x

4

nPC_sel

imm

16

Instruction<31:0>

0

1

Zero

nPC_MUX_sel

• New PC = { PC[31..28], target address, 00 }op target address

02631J-type jump

25

Mu

x1

0

Jump

TA

4 (MSBs)

00

Query• Can Zero still get asserted?

• Does nPC_sel need to be 0?

• If not, what?

26


The Single Cycle Datapath during Branch?

• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0op rs rt immediate

016212631

32

ALUctr=

clk

busW

RegWr=

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=

Exten

der3216

imm16

ALUSrc=ExtOp=

MemtoReg=

clk

Data In32

MemWr=

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs



The Single Cycle Datapath during Branch

• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0op rs rt immediate

016212631

32

ALUctr=SUB

clk

busW

RegWr=0

32

32busA

32

busB

5 5

Rw Ra Rb

RegFile

Rs

Rt

Rt

RdRegDst=x

Exten

der3216

imm16

ALUSrc=0ExtOp=x

MemtoReg=x

clk

Data In32

MemWr=0

zero01

0

1

=

AL

U 0

1

WrEn Adr

DataMemory

5


<16:20>

<11:15>

<0:15>

Imm16RdRtRs

nPC_sel=br instrfetchunitclk


Instruction Fetch Unit at the End of Branch• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ;

else PC = PC + 4

op rs rt immediate

016212631

• What is encoding of nPC_sel?

• Direct MUX select?

• Branch inst. / not branch

• Let’s pick 2nd option

nPC_sel zero? MUX0 x 01 0 01 1 1

Adr

InstMemory

nPC_selInstruction<31:0>

Zero

nPC_sel

Q: What logic gate?

imm16 clk

PC

00

4

PC

Ext

Ad

derA

dder

Mu

x

0

1

MUX ctrl


Step 4: Given Datapath: RTL Control

ALUctrRegDst ALUSrcExtOp MemtoRegMemWr

Instruction<31:0>

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel

Adr

InstMemory

DATA PATH

Control

Op

<0:5>

Fun

RegWr

<26:31>


A Summary of the Control Signals (1/2)inst Register Transfer

add R[rd] R[rs] + R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = “ADD”, RegDst = rd, RegWr, nPC_sel = “+4”

sub R[rd] R[rs] – R[rt]; PC PC + 4

ALUsrc = RegB, ALUctr = “SUB”, RegDst = rd, RegWr, nPC_sel = “+4”

ori R[rt] R[rs] + zero_ext(Imm16); PC PC + 4

ALUsrc = Im, Extop = “Z”,ALUctr = “OR”, RegDst = rt,RegWr, nPC_sel =“+4”

lw R[rt] MEM[ R[rs] + sign_ext(Imm16)]; PC PC + 4

ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”

sw MEM[ R[rs] + sign_ext(Imm16)] R[rs]; PC PC + 4

ALUsrc = Im, Extop = “sn”, ALUctr = “ADD”, MemWr, nPC_sel = “+4”

beq if ( R[rs] == R[rt] ) then PC PC + sign_ext(Imm16)] || 00 else PC PC + 4

nPC_sel = “br”, ALUctr = “SUB”


A Summary of the Control Signals (2/2)

add sub ori lw sw beq jump

RegDst

ALUSrc

MemtoReg

RegWrite

MemWrite

nPCsel

Jump

ExtOp

ALUctr<2:0>

1

0

0

1

0

0

0

x

Add

1

0

0

1

0

0

0

x

Subtract

0

1

0

1

0

0

0

0

Or

0

1

1

1

0

0

0

1

Add

x

1

x

0

1

0

0

1

Add

x

0

x

0

0

1

0

x

Subtract

x

x

x

0

0

?

1

x

x

op target address

op rs rt rd shamt funct

061116212631

op rs rt immediate

R-type

I-type

J-type

add, sub

ori, lw, sw, beq

jump

func

op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010Appendix A10 0000See 10 0010 We Don’t Care :-)


Boolean Expressions for Controller

RegDst = add + subALUSrc = ori + lw + swMemtoReg = lwRegWrite = add + sub + ori + lw MemWrite = swnPCsel = beqJump = jump ExtOp = lw + swALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR)ALUctr[1] = or

where,

rtype = ~op5 ~op4 ~op3 ~op2 ~op1 ~op0, ori = ~op5 ~op4 op3 op2 ~op1 op0 lw = op5 ~op4 ~op3 ~op2 op1 op0 sw = op5 ~op4 op3 ~op2 op1 op0

beq = ~op5 ~op4 ~op3 op2 ~op1 ~op0 jump = ~op5 ~op4 ~op3 ~op2 op1 ~op0

add = rtype func5 ~func4 ~func3 ~func2 ~func1 ~func0

sub = rtype func5 ~func4 ~func3 ~func2 func1 ~func0

How do we implement this in

gates?


Controller Implementation

add

sub

ori

lw

sw

beq

jump

RegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr[0]ALUctr[1]

“AND” logic “OR” logic

opcode func


Other Programmable Logic Arrays

• There are other types of PLAs which can be reprogrammed on the fly

• The most common is called a Field Programmable Gate Array (FPGA)

• made up of configurable logic blocks (CLBs) and flip-flops which can be programmed by software

• Berkeley has on-going research into reconfigurable computing with FPGAs

Check out RAMP and BEE3 projects


An Abstract View of the Critical Path Critical Path (Load Instruction) =

Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write

clk

5

Rw Ra Rb

RegisterFile

Rd

Data In

DataAddr Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

PC

5Rs

5Rt

32

323232

A

B

Nex

t A

dd

ress

clk clk

AL

U(Assumes a fast controller)


Peer Instruction

A. MemToReg=‘x’ & ALUctr=‘sub’. SUB or BEQ?

B. ALUctr=‘add’. Which 1 signal is different for all 3 of: ADD, LW, & SW? RegDst or ExtOp?

C. “Don’t Care” signals are useful because we can simplify our PLA personality matrix. F / T?

ABC0: SRF1: SRT2: SEF3: SET4: BRF5: BRT6: BEF7: BET

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

55 5


Rs

Rt

Rt

Rd

RegDst

Exten

der

Mu

x

Mux

3216imm16

ALUSrc

ExtOp

Mu

x

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr

AL

U


Clk

Zero

Instruction<31:0>

0

1

0

1

01

<21:25>

<16:20>

<11:15>

<0:15>

Imm16RdRsRt

nPC_sel


°5 steps to design a processor• 1. Analyze instruction set datapath requirements• 2. Select set of datapath components & establish clock

methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to

determine setting of control points that effects the register transfer.

• 5. Assemble the control logic• Formulate Logic Equations• Design Circuits

Summary: Single-cycle Processor

Control

Datapath

Memory

ProcessorInput

Output

CS61C L20 Single-Cycle CPU Control (1) Beamer, Summer 2007 © UCB Scott Beamer Instructor...

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Transcript of CS61C L20 Single-Cycle CPU Control (1) Beamer, Summer 2007 © UCB Scott Beamer Instructor...