CS429 9 -BQ CS4299-BQ - statics.cirrus.com · T he CS429 9 -BQ is an A C’97 2.1 compatible stereo...

Preliminary Product Information This document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.

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Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.com

MAR‘06DS319-BQPP2

CS4299-BQ

FeatureslAC ’97 2.1 Compatible

l Industry Leading Mixed Signal Technology

l20-bit Stereo Digital-to-Analog Converters

l18-bit Stereo Analog-to-Digital Converters

lSample Rate Converters

lFour Analog Line-level Stereo Inputs for LINE_IN, CD, VIDEO, and AUX

lTwo Analog Line-level Mono Inputs for Modem and Internal PC Beep

lDual Stereo Line-level Outputs for LINE_OUT and ALT_LINE_OUT

lDual Microphone Inputs

lHigh Quality Pseudo-Differential CD Input

lExtensive Power Management Support

lMeets or Exceeds the Microsoft® PC 99 Audio Performance Requirements lS/PDIF Digital Audio OutputlCrystalClear® 3D Stereo Enhancementl Industrial Temperature Range

DescriptionThe CS4299-BQ is an AC ’97 2.1 compatible stereo au-dio codec designed for PC multimedia systems. Usingthe industry leading CrystalClear® delta-sigma andmixed signal technology, the CS4299-BQ enables thedesign of PC 99-compliant desktop, portable, and enter-tainment PCs.

Coupling the CS4299-BQ with a PCI audio acceleratoror core logic supporting the AC ’97 interface, implementsa cost effective, superior quality, audio solution. TheCS4299-BQ surpasses PC 99 and AC ’97 2.1 audioquality standards.

ORDERING INFOCS4299-BQZ lead-free 48-pin LQFP 9x9x1.4 mm

AC '97REGISTERS

LINE

CD

AUX

VIDEO

MIC1

MIC2

PHONE

PC_BEEP

LINE_OUT

ALT_LINE_OUT

MONO_OUT

ANALOG INPUT MUXAND OUTPUT MIXER

AC-LINK AND AC '97REGISTERS

PCM_DATA

GAIN / MUTE CONTROLS

INPUTMUX

ΣOUTPUTMIXER

MIXER / MUX SELECTS

AC-LINK

PWRMGTTEST

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

PCM_DATASRC

SRC

ID0#

ID1#

EAPD, S/PDIFEAPD

SPDIF_OUT

18 bitADC

20 bitDAC

3D StereoEnhancement

ΣINPUTMIXER

CrystalClear® SoundFusion™ Audio Codec ’97

Copyright © Cirrus Logic, Inc. 2006(All Rights Reserved)

Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

http://www.cirrus.com

CrystalClear® SoundFusion™ Audio Codec ‘97

CS4299-BQ

March '06DS319-BQPP2

CS4299-BQ

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TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

ANALOG CHARACTERISTICS................................................................................................ 5ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6RECOMMENDED OPERATING CONDITIONS ....................................................................... 6DIGITAL CHARACTERISTICS................................................................................................. 6AC ’97 SERIAL PORT TIMING................................................................................................. 7

2. GENERAL DESCRIPTION ..................................................................................................... 102.1 AC-Link ............................................................................................................................ 102.2 Control registers .............................................................................................................. 102.3 Sample Rate Converters .................................................................................................. 112.4 Output Mixer .................................................................................................................... 112.5 Input Mux ......................................................................................................................... 112.6 Volume Control ................................................................................................................ 11

3. AC LINK FRAME DEFINITION ............................................................................................... 133.1 AC-Link Serial Data Output Frame .................................................................................. 143.1.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 143.1.2 Command Address Port (Slot 1) .................................................................................... 153.1.3 Command Data Port (Slot 2).......................................................................................... 153.1.4 PCM Playback Data (Slots 3-10) ................................................................................... 153.2 AC-Link Audio Input Frame .............................................................................................. 163.2.1 Serial Data Input Slot Tag Bits (Slot 0) ......................................................................... 163.2.2 Status Address Port (Slot 1) .......................................................................................... 163.2.3 Status Data Port (Slot 2) ................................................................................................ 173.2.4 PCM Capture Data (Slot 3-10)....................................................................................... 173.3 AC-Link Protocol Violation - Loss of SYNC ..................................................................... 18

4. REGISTER INTERFACE ........................................................................................................ 194.1 Reset Register (Index 00h) .............................................................................................. 204.2 Master Volume Register (Index 02h) ............................................................................... 204.3 Alternate Volume Register (Index 04h) ............................................................................ 214.4 Mono Volume Register (Index 06h) ................................................................................. 214.5 PC_BEEP Volume Register (Index 0Ah) ......................................................................... 224.6 Phone Volume Register (Index 0Ch) ................................................................................ 224.7 Microphone Volume Register (Index 0Eh) ........................................................................ 23

Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:http://www.cirrus.com/corporate/contacts/sales.cfm

Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.Intel is a registered trademark of Intel Corporation.Crystal Clear and Sound Fusion are trademarks of Cirrus Logic.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the infor-mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” withoutwarranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents orother rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets.No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, pho-tographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user.However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (elec-tronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as abasis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendorsand suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A listof Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

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4.8 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h) ........................................... 24

4.9 Input Mux Select Register (Index 1Ah)............................................................................. 25

4.10 Record Gain Register (Index 1Ch) ................................................................................. 25

4.11 General Purpose Register (Index 20h) ........................................................................... 26

4.12 3D Control Register (Index 22h)..................................................................................... 26

4.13 Powerdown Control/Status Register (Index 26h) ........................................................... 27

4.14 Extended Audio ID Register (Index 28h) ........................................................................ 28

4.15 Extended Audio Status/Control Register (Index 2Ah) .................................................... 28

4.16 PCM Front DAC Rate Register (Index 2Ch) ................................................................ 29

4.17 PCM L/R ADC Rate Register (Index 32h) ...................................................................... 29

4.18 AC Mode Control Register (Index 5Eh) .......................................................................... 30

4.19 Misc. Crystal Control Register (Index 60h) ..................................................................... 30

4.20 S/PDIF Control Register (Index 68h)............................................................................. 31

4.21 Vendor ID1 Register (Index 7Ch) ................................................................................... 32

4.22 Vendor ID2 Register (Index 7Eh) ................................................................................... 32

5. POWER MANAGEMENT ....................................................................................................... 33

5.1 AC ’97 Reset Modes ........................................................................................................ 33

5.1.1 Cold AC ‘97 Reset .............................................................................................. 33

5.1.2 Warm AC ’97 Reset ............................................................................................ 33

5.1.3 Register AC ’97 Reset ........................................................................................ 33

5.2 Powerdown Controls ....................................................................................................... 34

6. ANALOG HARDWARE DESCRIPTION ................................................................................. 36

6.1 Analog Inputs ................................................................................................................... 36

6.1.1 Line-Level Inputs ................................................................................................. 36

6.1.2 CD Input .............................................................................................................. 36

6.1.3 Microphone Inputs .............................................................................................. 37

6.1.4 PC Beep Input ..................................................................................................... 37

6.1.5 Phone Input ......................................................................................................... 38

6.2 Analog Outputs ................................................................................................................ 38

6.2.1 Stereo Outputs .................................................................................................... 38

6.2.2 Mono Output ....................................................................................................... 38

6.3 Miscellaneous Analog Signals ......................................................................................... 39

6.4 Power Supplies ................................................................................................................ 39

6.5 Reference Design ............................................................................................................ 39

7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 40

8. GROUNDING AND LAYOUT ................................................................................................. 40

9. PIN DESCRIPTIONS ........................................................................................................... 42

10. PARAMETER AND TERM DEFINITIONS ............................................................................ 47

11. REFERENCE DESIGN ....................................................................................................... 49

12. REFERENCES ...................................................................................................................... 50

13. PACKAGE DIMENSIONS .................................................................................................... 51

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LIST OF FIGURESFigure 1. Power Up Timing.............................................................................................................. 8

Figure 2. Codec Ready from Startup or Fault Condition ................................................................. 8

Figure 3. Clocks .............................................................................................................................. 8

Figure 4. Data Setup and Hold........................................................................................................ 9

Figure 5. PR4 Powerdown and Warm Reset .................................................................................. 9

Figure 6. Test Mode ........................................................................................................................ 9

Figure 7. AC-link Connections....................................................................................................... 10

Figure 8. Mixer Diagram................................................................................................................ 12

Figure 9. AC-link Input and Output Framing.................................................................................. 13

Figure 10. Line Input (Replicate for Video and Aux) ..................................................................... 36

Figure 11. Differential 2 VRMS CD Input ...................................................................................... 36

Figure 12. Differential 1 VRMS CD Input ...................................................................................... 36

Figure 13. Microphone Input ......................................................................................................... 37

Figure 14. Microphone Pre-amplifier ............................................................................................. 37

Figure 15. PC_BEEP Input............................................................................................................ 37

Figure 16. Modem Connection ...................................................................................................... 38

Figure 17. Alternate Line Output as Headphone Output ............................................................... 38

Figure 18. Stereo Output............................................................................................................... 38

Figure 19. Voltage Regulator ........................................................................................................ 39

Figure 20. S/PDIF Output.............................................................................................................. 40

Figure 21. Conceptual Layout for the CS4299-BQ........................................................................ 41

Figure 22. Pin Locations for the CS4299-BQ ................................................................................ 42

Figure 23. CS4299 Reference Design .......................................................................................... 49

LIST OF TABLESTable 1. Mixer Registers ...................................................................................................................... 19

Table 2. Analog Mixer Output Attenuation........................................................................................... 21

Table 3. Microphone Input Gain Values .............................................................................................. 23

Table 4. Analog Mixer Input Gain Values ............................................................................................ 24

Table 5. Stereo Volume Register Index............................................................................................... 24

Table 6. Input Mux Selection ............................................................................................................... 25

Table 7. Standard Sample Rates......................................................................................................... 29

Table 8. Slot Mapping......................................................................................................................... 30

Table 9. Device ID with Corresponding Part Number.......................................................................... 32

Table 10. Revision Values ................................................................................................................... 32

Table 11. Powerdown PR Bit Functions .............................................................................................. 34

Table 12. Powerdown PR Function Matrix .......................................................................................... 35

Table 13. Power Consumption by Powerdown Mode.......................................................................... 35

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1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS Standard test conditions unless otherwise noted: Tambient = 25° C, AVdd = 5.0 V ±5%, DVdd = 3.3 V ±5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=100 kΩ/ 1000 pF load, CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC functions, 20-bit linear coding for DAC functions; Mixer registers set for unity gain.

Notes: 1. ZAL refers to the analog output pin loading and CDL refers to the digital output pin loading.

2. Parameter definitions are given in the Section 10, Parameter and Term Definitions.

3. Path refers to the signal path used to generate this data. These paths are defined in the Section 10, Parameter and Term Definitions.

4. This specification is guaranteed by silicon characterization, it is not production tested.

Parameter (Note 2)

Symbol Path(Note 3)

CS4299-BQZUnitMin Typ Max

Full Scale Input VoltageLine InputsMic InputsMic Inputs (20 dB internal gain)

A-DA-DA-D

---

1.001.000.10

---

VRMSVRMSVRMS

Full Scale Output VoltageLine,Alternate Line, and Mono Outputs D-A 0.85 1.0 1.15 VRMS

Frequency Response (Note 4)Analog Ac = ± 0.25 dBDAC Ac = ± 0.25 dBADC Ac = ± 0.25 dB

FRA-AD-AA-D

202020

---

20,00020,00020,000

HzHzHz

Dynamic RangeStereo Analog inputs to LINE_OUTMono Analog inputs to LINE_OUTDAC Dynamic RangeADC Dynamic Range

DRA-AA-AD-AA-D

----

90858580

----

dB FS AdB FS AdB FS AdB FS A

DAC SNR (-20 dB FS input w/ CCIR-RMS filter on output)

SNRD-A - 70 - dB

Total Harmonic Distortion + Noise(-3 dB FS input signal):Line/Alternate Line OutputDACADC (all inputs except phone/mic)ADC (phone/mic)

THD+N

A-AD-AA-DA-D

----

-72-72-72-72

----

dB FSdB FSdB FSdB FS

Power Supply Rejection Ratio (1 kHz, 0.5 VRMS w/ 5 V DC offset) (Note 4) - 40 - dB

Interchannel Isolation - 60 - dBSpurious Tone (Note 4) - -100 - dB FSInput Impedance (Note 4) 10 - - kΩExternal Load Impedance 10 - - kΩOutput Impedance (Note 4) - 730 - ΩInput Capacitance (Note 4) - 5 - pFVrefout 2.0 2.28 2.5 V

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ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)

DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)

Parameter Min Typ Max UnitPower Supplies Digital

Analog-0.3-0.3

--

5.55.5

VV

Total Power Dissipation (Supplies, Inputs, Outputs) - 0.95 1.25 WInput Current per Pin (Except Supply Pins) -10 - 10 mAOutput Current per Pin (Except Supply Pins) -15 - 15 mAAnalog Input voltage -0.3 - AVdd +

0.3V

Digital Input voltage -0.3 - DVdd +0.3

V

Ambient Temperature (Power Applied) -40 - 85 °CStorage Temperature -65 - 150 °C

Parameter Symbol Min Typ Max UnitPower Supplies +3.3 V Digital

+5 V DigitalAnalog

DVdd1, DVdd2DVdd1, DVdd2AVdd1, AVdd2

3.1354.754.75

3.355

3.4655.255.25

VVV

Operating Ambient Temperature -40 - 85 °C

Parameter Symbol Min Typ Max UnitLow level input voltage Vil - - 0.8 VHigh level input voltage Vih 0.65 x DVdd - - VHigh level output voltage Voh 0.90 x DVdd 0.99 x DVdd - VLow level output voltage Vol - 0.03 0.10 x DVdd VInput Leakage Current (AC-link inputs) -10 - 10 µAOutput Leakage Current (Tri-stated AC-link outputs) -10 - 10 µAOutput buffer drive currentBIT_CLK, S/PDIF_OUTSDATA_IN, EAPD (Note 4)

- -

244

--

mAmA

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AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: Tambient = 25° C,

AVdd = 5.0 V, DVdd = 3.3 V; CL = 55 pF load.

Parameter Symbol Min Typ Max UnitRESET TimingRESET# active low pulse width Trst_low 1.0 - - µsRESET# inactive to BIT_CLK start-up delay Trst2clk - 40.0 - µs1st SYNC active to CODEC READY set Tsync2crd - 62.5 - µsVdd stable to Reset inactive Tvdd2rst# 100 - - µsClocksBIT_CLK frequency Fclk - 12.288 - MHzBIT_CLK period Tclk_period - 81.4 - nsBIT_CLK output jitter (depends on XTAL_IN source) - - 750 psBIT_CLK high pulse width Tclk_high 36 40.7 45 nsBIT_CLK low pulse width Tclk_low 36 40.7 45 nsSYNC frequency Fsync - 48 - kHzSYNC period Tsync_period - 20.8 - µsSYNC high pulse width Tsync_high - 1.3 - µsSYNC low pulse width Tsync_low - 19.5 - µsData Setup and HoldOutput Propagation delay from rising edge of BIT_CLK Tco - 12 - nsInput setup time from falling edge of BIT_CLK Tisetup 10 - - nsInput hold time from falling edge of BIT_CLK Tihold 0 - - nsInput Signal rise time Tirise 2 - 6 nsInput Signal fall time Tifall 2 - 6 nsOutput Signal rise time (Note 4) Torise 2 4 6 nsOutput Signal fall time (Note 4) Tofall 2 4 6 nsMisc. Timing ParametersEnd of Slot 2 to BIT_CLK, SDATA_IN low (PR4) Ts2_pdown - .28 1.0 µsSYNC pulse width (PR4) Warm Reset Tsync_pr4 1.0 - - µsSYNC inactive (PR4) to BIT_CLK start-up delay Tsync2clk 162.8 285 - nsSetup to trailing edge of RESET# (ATE test mode) (Note 4) Tsetup2rst 15 - - nsRising edge of RESET# to Hi-Z delay (Note 4) Toff - - 25 ns

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BIT_CLK

Trst_low Trst2clk

Tvdd2rst#

Vdd

RESET#

Figure 1. Power Up Timing

Figure 2. Codec Ready from Startup or Fault Condition

BIT_CLK

Tsync2crd

CODEC_READY

SYNC

Figure 3. Clocks

BIT_CLK

SYNC

Tirise Tifall

Torise TifallTclk_high Tclk_low

Tsync_high Tsync_low

Tsync_period

Tclk_period

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BIT_CLK

Tisetup Tihold

Tco

SDATA_OUT,SYNC

SDATA_IN

Figure 4. Data Setup and Hold

BIT_CLK

Ts2_pdown

SDATA_IN

SDATA_OUT

SYNC

Write to 0x20 Data PR4 Don't Care

Slot 1 Slot 2

sync_pr4 sync2clkT T

Figure 5. PR4 Powerdown and Warm Reset

RESET#

SDATA_OUT,SYNC

Tsetup2rst

SDATA_IN,

Toff

BIT_CLKHi-Z

Figure 6. Test Mode

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2. GENERAL DESCRIPTION

The CS4299-BQ is a mixed-signal serial audio Co-dec compliant to the Intel® Audio Codec ‘97 Spec-ification, revision 2.1 [1]. It is designed to be pairedwith a digital controller, typically located on thePCI bus or integrated within the system core logicchip set. The controller is responsible for all com-munications between the CS4299-BQ and the re-mainder of the system. The CS4299-BQ containstwo distinct functional sections: digital and analog.The digital section includes the AC-link interface,S/PDIF interface, serial data port, Sample RateConverters, and power management support. Theanalog section includes the analog input multiplex-er (mux), stereo output mixer, mono output mixer,stereo Analog-to-Digital Converters (ADCs), ste-reo Digital-to-Analog Converters (DACs), andtheir associated volume controls.

2.1 AC-Link

All communication with the CS4299-BQ is estab-lished with a 5-wire digital interface to the control-ler, as shown in Figure 7. This interface is calledthe AC-link. All clocking for the serial communi-cation is synchronous to the BIT_CLK signal.BIT_CLK is generated by the primary audio codecand is used to clock the controller and any second-

ary audio codecs. Both input and output AC-linkaudio frames are organized as a sequence of 256 se-rial bits forming 13 groups referred to as ‘slots’.During each audio frame, data is passed bi-direc-tionally between the CS4299-BQ and the control-ler. The input frame is driven from the CS4299-BQon the SDATA_IN line. The output frame is drivenfrom the controller on the SDATA_OUT line. Thecontroller is also responsible for issuing reset com-mands via the RESET# signal. Following a ColdReset, the CS4299-BQ is responsible for notifyingthe controller that it is ready for operation after syn-chronizing its internal functions. The CS4299-BQAC-link signals must use the same digital supplyvoltage as the controller chip, either +5 V or+3.3 V. See Section 3, AC Link Frame Definition,for detailed AC-link information.

2.2 Control registers

The CS4299-BQ contains a set of AC ’97 compli-ant control registers and a set of Cirrus Logic de-fined control registers. These registers control thebasic functions and features of the CS4299-BQ.Read accesses of the control registers by theAC ’97 controller are accomplished with the re-quested register index in Slot 1 of a SDATA_OUTframe. The following SDATA_IN frame will con-

CODECSYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

Digital AC'97Controller

Figure 7. AC-link Connections

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tain the read data in its Slot 2. Write operations aresimilar, with the register index in Slot 1 and thewrite data in Slot 2 of a SDATA_OUT frame. Thefunction of each input and output frame is detailedin Section 3, AC Link Frame Definition. Individualregister descriptions are found in Section 4, Regis-ter Interface.

2.3 Sample Rate Converters

The Sample Rate Converters (SRCs) provide highaccuracy digital filters supporting sample frequen-cies other than 48 kHz to be captured from theCS4299 or played from the controller. AC ’97 re-quires support for two audio rates (44.1 and48kHz). In addition, the Intel® I/O Controller Hub(ICHx) specification requires support for five moreaudio rates (8, 11.025, 16, 22.05, and 32). TheCS4299 supports all these rate, as shown in Table 7on page 29.

2.4 Output Mixer

The CS4299-BQ has two output mixers, illustratedin Figure 8. The stereo output mixer sums togetherthe analog inputs to the CS4299-BQ, including thePC_BEEP and PHONE signals, according to thesettings in the volume control registers. The stereooutput mix is sent to the LINE_OUT and

ALT_LINE_OUT pins on the CS4299-BQ. Themono output mixer generates a monophonic sum ofthe left and right channels from the stereo inputmixer. The mono output mix is sent to theMONO_OUT output pin on the CS4299-BQ.

2.5 Input Mux

The input multiplexer controls which analog inputis sent to the ADCs. The output of the input mux isconverted to stereo 18-bit digital PCM data andsent to the controller by means of the AC-linkSDATA_IN signal.

2.6 Volume Control

The CS4299-BQ volume registers control analoginput levels to the input mixer and analog outputlevels, including the master volume level, and thealternate volume level. The PC_BEEP volume con-trol uses 3 dB steps with a range of 0 dB to -45 dBattenuation. All other analog volume controls use1.5 dB steps. The analog inputs have a mixingrange of +12 dB signal gain to -34.5 dB signal at-tenuation. The analog output volume controls havefrom 0 dB to -94.5 dB attenuation for LINE_OUTand from 0 dB to -46.5 dB attenuation forALT_LINE_OUT and MONO_OUT.

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VO

L MUTE

VO

L MUTE

VO

L MUTE

VO

LV

OL MUTE

VO

LV

OL

VO

L MUTE

BOOST

ΣΣ ΣΣ

ΣΣ1/2

OUTPUTBUFFER

OUTPUTBUFFER

OUTPUTBUFFER

VO

LV

OL

ADCINPUTMUX

VO

L ADCMUTE

PCM_OUT

PC_BEEP

PHONE

MIC1

MIC2

LINE

CD

VIDEO

AUX

AN

ALO

G S

TE

RE

OIN

PU

T M

IXE

R

ANALOG STEREOOUTPUT MIXER

MASTERVOLUME

ALT LINEVOLUME

MONOVOLUME

MONO OUTSELECT

STEREO TOMONO MIXER

MAIN ADCGAIN

MAIN A/DCONVERTERS

MICSELECT

MONO OUT

LINE OUT

PCM_IN

DAC

MAIN D/ACONVERTERS

ΣΣ1/2

STEREO TOMONO MIXER

MUTE

MUTE

MUTE

3D

ALT LINE OUT

ΣΣ3D OUTPUT

MIXER

VO

L

MUTE

MUTE

MUTE

DAC DIRECTMODE

PC BEEP BYPASS

BYPASSBUFFER

Figure 8. Mixer Diagram

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3. AC LINK FRAME DEFINITION

The AC-link is a bidirectional serial port with dataorganized into frames consisting of one 16-bit andtwelve 20-bit time-division multiplexed slots. Thefirst slot, called the tag slot, contains bits indicatingif the CS4299-BQ is ready to receive data (inputframe) and which, if any, other slots contain validdata. Slots 1 through 12 contain audio or con-trol/status data. Both the serial data output and in-put frames are defined from the controllerperspective, not from the CS4299-BQ perspective.

The controller synchronizes the beginning of aframe with the assertion of the SYNC signal.

Figure 9 shows the position of each bit locationwithin the frame. The first bit position in a new se-rial data frame is F0 and the last bit position in theserial data frame is F255. When SYNC goes active(high) and is sampled active by the CS4299-BQ (onthe falling edge of BIT_CLK), both devices aresynchronized to a new serial data frame. The dataon the SDATA_OUT pin at this clock edge is thefinal bit of the previous frame’s serial data. On thenext rising edge of BIT_CLK, the first bit of Slot 0is driven by the controller on the SDATA_OUTpin. On the next falling edge of BIT_CLK, theCS4299-BQ latches this data in, as the first bit ofthe frame.

20.8 µs(48 kHz)

Tag Phase Data Phase

12.288 MHz81.4 ns

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

F0 F1 F2 F16F15F14F13F12 F35 F56 F76

D19

F255

ValidFrame

Slot 1Valid 0 R/W 0 WD15

F36 F57

D19 D18 D19

D19 D18 D19RD150000

F0 F1 F2 F16F15F14F13F12 F35 F56 F76F255 F36 F57

F255

F255

0 0

GPIOINT

F96

F96

D19

Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slots 5-12

Slot 2Valid

Slot 1Valid

Slot 2Valid

CodecReady 0

Slot 12Valid

CodecID1

CodecID0

Slot 12Valid

GPIOINT

Bit Frame Position:

Bit Frame Position:

Figure 9. AC-link Input and Output Framing

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3.1 AC-Link Serial Data Output Frame

In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4299-BQ from the AC’97 controller. Figure 9 illustrates the serial port timing.

The PCM playback data being passed to the CS4299-BQ is shifted out MSB first in the most significantbits of each slot. Any PCM data from the AC ’97 controller that is not 20 bits wide should be left justifiedin its corresponding slot and dithered or zero-padded in the unused bit positions.

Bits that are reserved should always be ‘cleared’ by the AC ’97 controller.

3.1.1 Serial Data Output Slot Tags (Slot 0)

Valid Frame The Valid Frame bit determines if any of the following slots contain either valid playback data for the CS4299-BQ DACs or data for read/write operations. When ‘set’, at least one of the other AC-link slots contain valid data. If this bit is ‘clear’, the remainder of the frame is ignored.

Slot [1:2] Valid The Slot [1:2] Valid bits indicate the validity of data in their corresponding serial data output slots. If a bit is ‘set’, the corresponding output slot contains valid data. If a bit is ‘cleared’, the corresponding slot will be ignored.

Slot [3:10] Valid The Slot [3:10] Valid bits indicate Slot [3:10] contains valid playback data for the CS4299-BQ. If a Slot Valid bit is ‘set’, the named slot contains valid audio data. If the bit is ‘clear’, the slot will be ignored. The CS4299-BQ supports alternate slot mapping as defined in the AC ’97 2.1 spec-ification. For more information, see the AC Mode Control Register (Index 5Eh).

Codec ID[1:0] The Codec ID[1:0] bits display the Codec ID of the audio codec being accessed during the cur-rent AC-link frame. Codec ID[1:0] = 00 indicates the primary codec is being accessed. Codec ID[1:0] = 01, 10, or 11 indicates one of three possible secondary codecs is being accessed. A non-zero value of one or more of the Codec ID bits indicates a valid Read or Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Valid

FrameSlot 1 Valid

Slot 2 Valid

Slot 3 Valid

Slot 4 Valid

Slot 5 Valid

Slot 6 Valid

Slot 7 Valid

Slot 8 Valid

Slot 9 Valid

Slot 10 Valid

ReservedCodec

ID1Codec

ID0

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3.1.2 Command Address Port (Slot 1)

R/W Read/Write. When this bit is ‘set’, a read of the AC ’97 register specified by the register index bits will occur in the AC ’97 2.1 audio codec. When the bit is ‘cleared’, a write will occur. For any read or write access to occur, the Frame Valid bit (F0) must be ‘set’ and the Codec ID[1:0] bits (F[14:15]) must match the Codec ID of the AC ’97 2.1 audio codec being accessed. Additionally, for a primary codec, the Slot 1 Valid bit (F1) must be ‘set’ for a read access and both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘set’ for a write access. For a secondary co-dec, both the Slot 1 Valid bit (F1) and the Slot 2 Valid bit (F2) must be ‘cleared’ for read and write accesses. See Figure 9 for bit frame positions.

RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the CS4299-BQ. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’ to access CS4299-BQ registers.

3.1.3 Command Data Port (Slot 2)

WD[15:0] Write Data. The WD[15:0] bits contain the 16-bit value to be written to the register. If an access is a read, this slot is ignored.

NOTE: For any write to an AC ’97 register, the write is defined to be an ‘atomic’ access. This means that when the Slot 1 Valid bit in output Slot 0 is ‘set’, the Slot 2 Valid bit in output slot 0 should always be ‘set’ during the same audio frame. No write access may be split across 2 frames.

3.1.4 PCM Playback Data (Slots 3-10)

PD[19:0] Playback Data. The PD[19:0] bits contain the 20-bit PCM playback (2’s complement) data for the left and right DACs and/or the S/PDIF transmitter. Table 8 on page 30 lists a cross reference for each function and its respective slot. The mapping of a given slot to a DAC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and by the SM[1:0] and AMAP bits in the AC Mode Control Register (Index 5Eh).

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R/W RI6 RI5 RI4 RI3 RI2 RI1 RI0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Reserved

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

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3.2 AC-Link Audio Input Frame

In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299-BQ to the AC ’97controller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 il-lustrates the serial port timing.

The PCM capture data from the CS4299-BQ is shifted out MSB first in the most significant 18 bits of eachslot. The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from theAC ’97 Controller that is less than 18 bits wide, the controller should dither and round or just round (butnot truncate) to the desired bit depth.

Bits that are reserved or not implemented in the CS4299-BQ will always be returned ‘cleared’.

3.2.1 Serial Data Input Slot Tag Bits (Slot 0)

Codec Ready The Codec Ready bit indicates the readiness of the CS4299-BQ AC-link. Immediately after a Cold Reset this bit will be ‘clear’. Once the CS4299-BQ clocks and voltages are stable, this bit will be ‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted by the controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function. Those must be checked in the Powerdown Control/Status Reg-ister (Index 26h) by the controller before any access is made to the mixer registers. Any ac-cesses to the CS4299-BQ while Codec Ready is ‘clear’ are ignored.

Slot 1 Valid When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.

Slot 2 Valid When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.

Slot [3:10] Valid When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the CS4299-BQ ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot con-tain valid data.

3.2.2 Status Address Port (Slot 1)

RI[6:0] Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has been requested in the previous frame. The CS4299-BQ will only echo the register index for a read access. Write accesses will not return valid data in Slot 1.

SR[3:10] Slot Request. If SRx is ‘set’, this indicates the CS4299 SRC does not need a new sample on the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register (Index 2Ah) is ‘clear’, the SR[3:10] bits are always 0. When VRA is ‘set’, the SRC is enabled and the SR[3:10] bits are used to request data.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Codec Ready

Slot 1 Valid

Slot 2 Valid

Slot 3 Valid

Slot 4 Valid

Slot 5 Valid

Slot 6 Valid

Slot 7 Valid

Slot 8 Valid

Slot 9 Valid

Slot 10 Valid

0 0 0 0 0

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 RI6 RI5 RI4 RI3 RI2 RI1 RI0 SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10 0 Reserved

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3.2.3 Status Data Port (Slot 2)

RD[15:0] Read Data. The RD[15:0] bits contain the register data requested by the controller from the previous read request. All read requests will return the read address in the input Slot 1 and the register data in the input Slot 2 on the following serial data frame.

3.2.4 PCM Capture Data (Slot 3-10)

CD[17:0] Capture Data. The D[17:0] bits contain 18-bit PCM (2’s complement) capture data. The map-ping of a given slot to an ADC is determined by the state of the ID[1:0] bits in the Extended Audio ID Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Reg-ister (Index 5Eh). The definition of each slot can be found in Table 8 on page 30.

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Reserved

Bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 0 0

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3.3 AC-Link Protocol Violation - Loss of SYNC

The CS4299-BQ is designed to handle SYNC pro-tocol violations. The following are situations wherethe SYNC protocol has been violated:

• The SYNC signal is not sampled high for exact-ly 16 BIT_CLK clock cycles at the start of anaudio frame.

• The SYNC signal is not sampled high on the256th BIT_CLK clock period after the previousSYNC assertion.

• The SYNC signal goes active high before the256th BIT_CLK clock period after the previousSYNC assertion.

Upon loss of synchronization with the controller,the CS4299-BQ will ‘clear’ the Codec Ready bit inthe serial data input frame until two valid framesare detected. During this detection period, theCS4299-BQ will ignore all register reads andwrites and will discontinue the transmission ofPCM capture data. In addition, if the LOSM bit inthe Misc. Crystal Control Register (Index 60h) is‘set’ (default), the CS4299-BQ will mute all analogoutputs. If the LOSM bit is ‘clear’, the analog out-puts will not be muted.

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4. REGISTER INTERFACE

Reg Register Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default00h Reset 0 SE4 SE3 SE2 SE1 SE0 0 ID8 ID7 0 0 ID4 0 0 0 0 1990h

02h Master Volume Mute 0 ML5 ML4 ML3 ML2 ML1 ML0 0 0 MR5 MR4 MR3 MR2 MR1 MR0 8000h

04h Alternate Volume Mute 0 ML5 ML4 ML3 ML2 ML1 ML0 0 0 MR5 MR4 MR3 MR2 MR1 MR0 8000h

06h Mono Volume Mute 0 0 0 0 0 0 0 0 0 MM5 MM4 MM3 MM2 MM1 MM0 8000h

0Ah PC_BEEP Volume Mute 0 0 0 0 0 0 0 0 0 0 PV3 PV2 PV1 PV0 0 0000h

0Ch Phone Volume Mute 0 0 0 0 0 0 0 0 0 0 GN4 GN3 GN2 GN1 GN0 8008h

0Eh Mic Volume Mute 0 0 0 0 0 0 0 0 20dB 0 GN4 GN3 GN2 GN1 GN0 8008h

10h Line In Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0 8808h

12h CD Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0 8808h

14h Video Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0 8808h

16h Aux Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0 8808h

18h PCM Out Volume Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0 8808h

1Ah Record Select 0 0 0 0 0 SL2 SL1 SL0 0 0 0 0 0 SR2 SR1 SR0 0000h

1Ch Record Gain Mute 0 0 0 GL3 GL2 GL1 GL0 0 0 0 0 GR3 GR2 GR1 GR0 8000h

20h General Purpose 0 0 3D 0 0 0 MIX MS LPBK 0 0 0 0 0 0 0 0000h

22h 3D Control 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0 0000h

26h Powerdown Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC 000Fh

28h Extended Audio ID ID1 ID0 0 0 0 0 AMAP 0 0 0 0 0 0 0 0 VRA 0201h

2Ah Extended Audio Ctrl/Stat 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRA 0000h

2Ch PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

32h PCM L/R ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h

Cirrus Logic Defined Registers:5E AC Mode Control 0 0 0 0 0 0 0 DDM AMAP 0 SM1 SM0 0 0 0 0 0080h

60 Misc. Crystal Control 0 0 0 0 Reserved 0 0 Reserved 0 Reserved LOSM 0023h

68 S/PDIF Control SPEN Val 0 Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Emph Copy /Audio Pro 0000h

7Ch Vendor ID1(CR) F7 F6 F5 F4 F3 F4 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0 4352h

7Eh Vendor ID2(Y-) T7 T6 T5 T4 T3 T2 T1 T0 0 DID2 DID1 DID0 0 REV2 REV1 REV0 5931h

Table 1. Mixer Registers

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4.1 Reset Register (Index 00h)

SE[4:0] Crystal 3D Stereo Enhancement. SE[4:0] = 00110, indicating this feature is present.

ID8 18-bit ADC Resolution. The ID8 bit is ‘set’, indicating this feature is present.

ID7 20-bit DAC resolution. The ID7 bit is ‘set’, indicating this feature is present.

ID4 Headphone Output (Alt Line Out). The ID4 bit is ‘set’, indicating this feature is present.

Default 1990h. The data in this register is read-only data.

Any write to this register causes a Register Reset to the default state of the audio (Index 00h - 38h) and vendor spe-cific (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS429.

4.2 Master Volume Register (Index 02h)

Mute Master Mute. Setting this bit mutes the LINE_OUT_L/R output signals.

ML[5:0] Master Volume Left. These bits control the left master output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -94.5 dB attenuation.

MR[5:0] Master Volume Right. These bits control the right master output volume. Each step corresponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -94.5 dB attenuation.

Default 8000h. This value corresponds to 0 dB attenuation and Mute ‘set’.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 SE4 SE3 SE2 SE1 SE0 0 ID8 ID7 0 0 ID4 0 0 0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 ML5 ML4 ML3 ML2 ML1 ML0 0 0 MR5 MR4 MR3 MR2 MR1 MR0

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4.3 Alternate Volume Register (Index 04h)

Mute Alternate Mute. Setting this bit mutes the ALT_LINE_OUT_L/R output signals.

ML[4:0] Alternate Volume Left. These bits control the left alternate output volume. Each step corre-sponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB atten-uation. See Table 2 for further attenuation levels.

ML5 Alternate Volume Left Max Attenuation. Setting ML5 sets the left channel attenuation to -46.5 dB by forcing ML[4:0] to a ‘1’ state. ML[5:0] will read back 011111 when ML5 has been ‘set’. Table 2 summarizes this behavior.

MR[4:0] Alternate Volume Right. These bits control the right alternate output volume. Each step corre-sponds to 1.5 dB gain adjustment, with 00000 = 0 dB. The total range is 0 dB to -46.5 dB atten-uation. See Table 2 for further attenuation levels.

MR5 Alternate Volume Right Max Attenuation. Setting MR5 sets the right channel attenuation to -46.5 dB by forcing MR[4:0] to a ‘1’ state. MR[5:0] will read back 011111 when MR5 has been ‘set’. Table 2 summarizes this behavior.


4.4 Mono Volume Register (Index 06h)

Mute Mono Mute. Setting this bit mutes the MONO_OUT signal.

MM[5:0] Mono Volume. These bits control the mono output volume. Each step corresponds to 1.5 dB gain adjustment, with a total available range from 0 dB to -46.5 dB attenuation. See Table 2 for further attenuation levels.

MM5 Mono Volume Max Attenuation. Setting the MM5 bit sets the mono attenuation to -46.5 dB by forcing MM[4:0] to a ‘1’ state. MM[5:0] will read back 011111 when MM5 has been ‘set’. Table 2 summarizes this behavior.


D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 ML5 ML4 ML3 ML2 ML1 ML0 0 0 MR5 MR4 MR3 MR2 MR1 MR0

Mx[5:0] Write

Mx[5:0]Read

GainLevel

000000 000000 0 dB

000001 000001 -1.5 dB

… … ...

011111 011111 -46.5 dB

100000 011111 -46.5 dB

... ... ...

111111 011111 -46.5 dB

Table 2. Analog Mixer Output Attenuation

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 0 0 0 0 0 0 0 0 MM5 MM4 MM3 MM2 MM1 MM0

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4.5 PC_BEEP Volume Register (Index 0Ah)

Mute PC_BEEP Mute. Setting this bit mutes the PC_BEEP input signal.

PV[3:0] PC_BEEP Volume Control. The PV[3:0] bits are used to control the gain levels of the PC_BEEP input source to the Input Mixer. Each step corresponds to 3 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to -45 dB attenuation.

Default 0000h. This value corresponds to 0 dB attenuation and Mute ‘clear’.

This register has no effect on the PC_BEEP volume during RESET#.

4.6 Phone Volume Register (Index 0Ch)

Mute Phone Mute. Setting this bit mutes the Phone input signal.

GN[4:0] Phone Volume Control. The GN[4:0] bits are used to control the gain levels of the Phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 on page 24 for further details.

Default 8008h. This value corresponds to 0 dB gain and Mute ‘set’.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 0 0 0 0 0 0 0 0 0 PV3 PV2 PV1 PV0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 0 0 0 0 0 0 0 0 0 GN4 GN3 GN2 GN1 GN0

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4.7 Microphone Volume Register (Index 0Eh)

Mute Microphone Mute. Setting this bit mutes the MIC1 or MIC2 signal. The selection of the MIC1 or MIC2 input pin is controlled by the MS bit in the General Purpose Register (Index 20h).

GN[4:0] Microphone Volume Control. The GN[4:0] bits are used to control the gain level of the Micro-phone input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 3 for further details.

20dB Microphone 20 dB Boost. When ‘set’, the 20dB bit enables the +20 dB microphone boost block. This bit allows for variable boost of 0 dB or +20 dB. Table 3 summarizes this behavior.


D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 0 0 0 0 0 0 0 20dB 0 GN4 GN3 GN2 GN1 GN0

GN[4:0]Gain Level

20dB = 0 20dB = 1

00000 +12.0 dB +32.0 dB

00001 +10.5 dB +30.5 dB

… … ...

00111 +1.5 dB +21.5 dB

01000 0.0 dB +20.0 dB

01001 -1.5 dB +18.5 dB

… … ...

11111 -34.5 dB -14.5 dB

Table 3. Microphone Input Gain Values

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4.8 Stereo Analog Mixer Input Gain Registers (Index 10h - 18h)

Mute Stereo Input Mute. Setting this bit mutes the respective input signal, both right and left inputs.

GL[4:0] Left Volume Control. The GL[4:0] bits are used to control the gain level of the left analog input source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details.

GR[4:0] Right Volume Control. The GR[4:0] bits are used to control the gain level of the right analog in-put source to the Input Mixer. Each step corresponds to 1.5 dB gain adjustment, with 01000 = 0 dB. The total range is +12 dB to -34.5 dB gain. See Table 4 for further details.


The Stereo Analog Mixer Input Gain Registers are listed in Table 5.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 0 GL4 GL3 GL2 GL1 GL0 0 0 0 GR4 GR3 GR2 GR1 GR0

Gx[4:0] Gain Level

00000 +12.0 dB

00001 +10.5 dB

… …

00111 +1.5 dB

01000 0.0 dB

01001 -1.5 dB

… …

11111 -34.5 dB

Table 4. Analog Mixer Input Gain Values

Register Index Function

10h Line In Volume

12h CD Volume

14h Video Volume

16h Aux Volume

18h PCM Out Volume

Table 5. Stereo Volume Register Index

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4.9 Input Mux Select Register (Index 1Ah)

SL[2:0] Left Channel Source. The SL[2:0] bits select the left channel source to pass to the ADCs for recording. See Table 6 for possible values.

SR[2:0] Right Channel Source. The SR[2:0] bits select the right channel source to pass to the ADCs for recording. See Table 6 for possible values.

Default 0000h. This value selects the Mic input for both channels.

4.10 Record Gain Register (Index 1Ch)

Mute Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.

GL[3:0] Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain adjust-ment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain.

GR[3:0] Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain.


D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 0 SL2 SL1 SL0 0 0 0 0 0 SR2 SR1 SR0

Sx[2:0] Record Source

000 Mic

001 CD Input

010 Video Input

011 Aux Input

100 Line Input

101 Stereo Mix

110 Mono Mix

111 Phone Input

Table 6. Input Mux Selection

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0Mute 0 0 0 GL3 GL2 GL1 GL0 0 0 0 0 GR3 GR2 GR1 GR0

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4.11 General Purpose Register (Index 20h)

3D 3D Enable. When ‘set’, the 3D bit enables the CrystalClearTM 3D stereo enhancement. This function is not available in DAC Direct Mode (DDM).

MIX Mono Output Select. The MIX bit selects the source for the Mono Out output. When ‘set’, the microphone input is selected. When ‘clear’, the stereo-to-mono mixer is selected.

MS Microphone Select. The MS bit determines which of the two Mic inputs are passed to the mixer. When ‘set’, the MIC2 input is selected. When ‘clear’, the MIC1 input is selected.

LPBK Loopback Enable. When ‘set’, the LPBK bit enables the ADC/DAC Loopback Mode. This bit routes the output of the ADCs to the input of the DACs without involving the AC-link.

Default 0000h

4.12 3D Control Register (Index 22h)

S[3:0] Spacial Enhancement Depth. These bits control the amount of “space” added to the output ste-reo signal. When S[3:0] = 0000, the minimum amount of spatial enhancement is added. When S[3:0] = 1111, the maximum amount of spatial enhancement is added. The 3D function is en-abled and disabled by the 3D bit in the General Purpose Register (Index 20h).

Default 0000h. This value corresponds to minimum spatial enhancement added to the output signal.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 3D 0 0 0 MIX MS LPBK 0 0 0 0 0 0 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0

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4.13 Powerdown Control/Status Register (Index 26h)

EAPD External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power down external amplifiers.

PR6 Alternate Line Out Powerdown. When ‘set’, the alternate line out buffer is powered down.

PR5 Internal Clock Disable. When ‘set’, this bit completely powers down both the analog and digital sections of the CS4299-BQ. The only way to recover from setting this bit is through a Cold Re-set (driving the RESET# signal active).

PR4 AC-link Powerdown. When ‘set’, the AC link is powered down (BIT_CLK off). The AC-link can be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RESET# signal (primary audio codec only).

PR3 Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before writing any mixer registers.

PR2 Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the voltage reference is still active). When clearing this bit, the ANL bit should be checked before writing any mixer registers.

PR1 Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the DAC bit should be checked before sending any data to the DACs.

PR0 L/R ADCs and Input Mux Powerdown. When ‘set’, the ADCs and the ADC input muxes are pow-ered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit goes high.

REF Voltage Reference Ready Status. When ‘set’, indicates the voltage reference is at a nominal level.

ANL Analog Ready Status. When ‘set’, the analog output mixer, input multiplexer, and volume con-trols are ready. When clear, no volume control registers should be written.

DAC Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC link. When clear, the DACs will not accept any valid data.

ADC L/R ADC Ready Status. When ‘set’, the ADCs are ready to send data across the AC link. When clear, no data will be sent to the Controller.

Default 0000h. This value indicates all blocks are powered on. The lower four bits will change as the CS4299-BQ finishes an initialization and calibration sequence.

The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4299-BQ as well as external amplifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular section of the CS4299-BQ is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the powerdown functions.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 0 0 0 0 REF ANL DAC ADC

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4.14 Extended Audio ID Register (Index 28h)

ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4299-BQ is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4299-BQ is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins.

AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link slot to audio DAC mapping is supported. This bit is a shadow of the AMAP bit in the AC Mode Control Register (Index 5Eh). The PCM playback and capture slots are mapped according to Table 8 on page 30.

VRA Variable Rate PCM Audio. The VRA bit indicates whether variable rate PCM audio is supported. This bit always returns ‘1’, indicating that variable rate PCM audio is available.

Default x201h. Where x is determined by the state of ID[1:0]# input pins. The Extended Audio ID Reg-ister (Index 28h) is a read only register.

4.15 Extended Audio Status/Control Register (Index 2Ah)

VRA Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). The bit must be ‘set’ in order to use variable PCM playback or capture rates. The VRA bit also serves as a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default values. The SRC data path is flushed and the Slot Request bits for the currently active DAC slots will be fixed at ‘0’.

Default 0000h

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0ID1 ID0 0 0 0 0 AMAP 0 0 0 0 0 0 0 0 VRA

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRA

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4.16 PCM Front DAC Rate Register (Index 2Ch)

SR[15:0] Front DAC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the Extend-ed Audio Status/Control Register (Index 2Ah) is ‘set’. If the VRA bit is ‘clear’, all writes are ig-nored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the VRA bit is ‘set’, seven standard sample rates are available. If a sample rate written to the register is not directly supported, the attempted value to be written will be decoded according to the ranges indicated in Table 7. All register read transactions will reflect the actual value stored (column 2 in Table 7) and not the one attempted to be written.

Default BB80h. This value corresponds to 48 kHz sample rate..

4.17 PCM L/R ADC Rate Register (Index 32h)

SR[15:0] Left/Right ADC Sample Rate. The SR[15:0] bits can only be written when the VRA bit of the Extended Audio Status/Control Register (Index 2Ah) is ‘set’. If the VRA bit is ‘clear’, all writes are ignored and the register reads back BB80h; corresponding to a 48 kHz sample rate. If the VRA bit is ‘set’, seven standard sample rates are available. If a sample rate written to the reg-ister is not directly supported, the attempted value to be written will be decoded according to the ranges indicated in Table 7. All register read transactions will reflect the actual value stored (column 2 in Table 7) and not the one attempted to be written.

Default BB80h. This value corresponds to 48 kHz sample rate.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

Sample rate(Hz)

SR[15:0]SR[15:12]

Decode Range

8,000 1F40 0 or 1

11,025 2B11 2

16,000 3E80 3

22,050 5622 4 or 5

32,000 7D00 6 or 7

44,100 AC44 8, 9, or Ah

48,000 BB80 Bh, Ch, Dh, Eh, or Fh

Table 7. Standard Sample Rates

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0

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4.18 AC Mode Control Register (Index 5Eh)

DDM DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When ‘set’, the L/R DACs directly drive the line and alternate line outputs by bypassing the audio mix-er. When ‘clear’, the audio mixer is the source for the line and alternate line outputs.

AMAP Audio Slot Mapping. This read/write bit controls whether the CS4299-BQ responds to the Co-dec ID based slot mapping as outlined in the AC ’97 2.1 specification. The bit is shadowed in the Extended Audio ID Register (Index 28h). Refer to Table 8 for the slot mapping configura-tions.

SM[1:0] Slot Map. The SM[1:0] bits define the Slot Mapping for the CS4299-BQ when the AMAP bit is ‘cleared’. Refer to Table 8 for the slot mapping configurations.

Default 0080h

4.19 Misc. Crystal Control Register (Index 60h)

LOSM Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is ‘set’, the CS4299-BQ will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4299-BQ expects to sample SYNC ‘high’ for 16 consecutive BIT_CLK periods and then ‘low’ for 240 consecutive BIT_CLK periods, otherwise loss of SYNC becomes true.

Default 0023h

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 0 0 0 DDM AMAP 0 SM1 SM0 0 0 0 0

Slot Assignment

Mode

Codec ID Slot Map

AMAP

Slot Assignments

ID1 ID0 SM1 SM0DAC,SPDIF

ADC

L R L R

AMAP Mode 0 0 0 X X 1 3 4 3 4

AMAP Mode 1 0 1 X X 1 3 4 3 4

AMAP Mode 2 1 0 X X 1 7 8 7 8

AMAP Mode 3 1 1 X X 1 6 9 6 9

Slot Map Mode 0 X X 0 0 0 3 4 3 4

Slot Map Mode 1 X X 0 1 0 5 6 5 6

Slot Map Mode 2 X X 1 0 0 7 8 7 8

Slot Map Mode 3 X X 1 1 0 9 10 9 10

Table 8. Slot Mapping

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00 0 0 0 Reserved 0 0 Reserved 0 Reserved LOSM

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4.20 S/PDIF Control Register (Index 68h)

SPEN S/PDIF Enable. The SPEN bit enables S/PDIF data transmission on the S/PDIF_OUT pin. The SPEN bit routes the left and right channel data from the AC ’97 controller, the digital mix-er, or the digital effects engine to the S/PDIF transmitter block. The actual data routed to the S/PDIF block is controlled through the AMAP/SM[1:0] configuration in the AC Mode Control Register (Index 5Eh).

Val Validity. The V bit is mapped to the V bit (bit 28) of every sub-frame. If this bit is ‘0’, the signal is suitable for conversion or processing.

Fs Sample Rate. The Fs bit indicates the sampling rate for the S/PDIF data. The inverse of this bit is mapped to bit 25 of the channel status block. When the Fs bit is ‘clear’, the sampling frequency is 48 kHz. When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4299-BQ. The Fs bit is merely an indicator to the S/PDIF receiver.

L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘0’ indicates original material and a value of ‘1’ indicates a copy of original material. For all other category codes the definition of the L bit is reversed.

CC[6:0] Category Code. The CC[6:0] bits are mapped to bits 8-14 of the channel status block.

Emph Data Emphasis. The Emph bit is mapped to bit 3 of the channel status block. If the Emph bit is ‘1’, 50/15us filter pre-emphasis is indicated. If the bit is ‘0’, no pre-emphasis is indicated.

Copy Copyright. The Copy bit is mapped to bit 3 of the channel status block. If the Copy bit is ‘1’ copyright is not asserted and copying is permitted.

/Audio Audio / Non-Audio. The /Audio bit is mapped to bit 1 of the channel status block. If the /Audio bit is ‘0’, the data transmitted over S/PDIF is assumed to be digital audio. If the /Audio bit is ‘1’, non-audio data is assumed.

Pro Professional/Consumer. The Pro bit is mapped to bit 0 of the channel status block. If the Pro bit is ‘0’, consumer use of the audio control block is indicated. If the bit is ‘1’, professional use is indicated.

Default 0000h

For a further discussion of the proper use of the channel status bits see application note AN22: Overview of Digital Audio Interface Data Structures [3].

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0SPEN Val 0 Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Emph Copy /Audio Pro

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4.21 Vendor ID1 Register (Index 7Ch)

F[7:0] First Character of Vendor ID. With a value of F[7:0] = 43h, these bits define the ASCII ‘C’ character.

S[7:0] Second Character of Vendor ID. With a value of S[7:0] = 52h, these bits define the ASCII ‘R’ character.

Default 4352h. This register contains read-only data.

4.22 Vendor ID2 Register (Index 7Eh)

T[7:0] Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ character.

DID[2:0] Device ID. With a value of DID[2:0] = 011, these bits specify the audio codec is a CS4299.

REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’.

Default 593xh. This register contains read-only data.

The two Vendor ID registers provide a means to determine the manufacturer of the AC ’97 audio codec. The first three bytes of the Vendor ID registers contain the ASCII code for the first three letters of Crystal (CRY). The final byte of the Vendor ID registers is divided into a Device ID field and a Revision field. Table 9 lists the currently defined Device ID’s. Table 10 lists the current revisions of the CS4299-BQ.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0F7 F6 F5 F4 F3 F2 F1 F0 S7 S6 S5 S4 S3 S2 S1 S0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0T7 T6 T5 T4 T3 T2 T1 T0 0 DID2 DID1 DID0 0 REV2 REV1 REV0

DID[2:0] Part Name

000 CS4297

001 CS4297A

010 CS4294/CS4298

011 CS4299

100 CS4201

101 CS4205

110 CS4291

111 CS4202

Table 9. Device ID with Corresponding Part Number

REV[2:0] Revision

001 A

010 B

011 C

100 D, E, F, G, H

101 K

110 L

Table 10. Revision Values

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5. POWER MANAGEMENT

5.1 AC ’97 Reset Modes

The CS4299-BQ supports three reset methods, asdefined in the AC ’97 Specification: Cold AC ’97Reset, Warm AC ’97 Reset, Register AC ’97 Reset.A Cold Reset results in all AC ’97 logic (registersincluded) initialized to its default state. A WarmReset leaves the contents of the AC ’97 register setunaltered. A Register Reset initializes only theAC ’97 registers to their default states.

5.1.1 Cold AC ‘97 Reset

A Cold Reset is achieved by asserting RESET# fora minimum of 1 µs after the power supply railshave stabilized. This is done in accordance with theminimum timing specifications in the AC ’97 Seri-al Port Timing section on page 7. Once deasserted,all of the CS4299-BQ registers will be reset to theirdefault power-on states and the BIT_CLK andSDATA_IN signals will be reactivated.

5.1.2 Warm AC ’97 Reset

A Warm Reset allows the AC-link to be reactivatedwithout losing information in the CS4299-BQ reg-isters. A Warm Reset is required to resume from aD3hot state, where the AC-link had been halted yetfull power had been maintained. A primary codecWarm Reset is initiated when the SYNC signal isdriven high for at least 1 µs and then driven low inthe absence of the BIT_CLK clock signal. TheBIT_CLK clock will not restart until at least 2 nor-mal BIT_CLK clock periods (162.8 ns) after theSYNC signal is deasserted. A Warm Reset of thesecondary codec is recognized when the primarycodec on the AC-link resumes BIT_CLK genera-tion. The CS4299-BQ will wait for BIT_CLK to bestable to restore SDATA_IN activity and/orS/PDIF transmission on the following frame.

5.1.3 Register AC ’97 Reset

The third reset mode provides a Register Reset tothe CS4299-BQ. This is available only when theCS4299-BQ AC-link is active and the CodecReady bit is ‘set’. The audio (including extendedaudio) registers (Index 00h - 38h) and the vendorspecific registers (Index 5Ah - 7Ah) are reset totheir default states by a write of any value to the Re-set Register (Index 00h).

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5.2 Powerdown Controls

The Powerdown Control/Status Register(Index 26h) controls the power management func-tions. The PR[6:0] bits in this register control theinternal powerdown states of the CS4299-BQ.Powerdown control is available for individual sub-sections of the CS4299-BQ by asserting any PRxbit or any combination of PRx bits. Most power-down states can be resumed by clearing the corre-sponding PRx bit. Table 11 shows the mapping ofthe power control bits to the functions they man-age.

When PR0 is ‘set’, the L/R ADCs and the InputMux are shut down and the ADC bit in the Power-down Control/Status Register (Index 26h) is‘cleared’ indicating the ADCs are no longer in aready state. The same is true for the DACs, the an-alog mixers, and the reference voltage (Vrefout).When the PR2 or PR3 bit of the mixer is ‘cleared’,the mixer section will begin a power-on process,and the corresponding powerdown status bit will be‘set’ when the hardware is ready.

Shutting down the AC-link by ‘setting’ PR4 causesthe primary Codec to turn off the BIT_CLK anddrive SDATA_IN low. It also ignores SYNC and

SDATA_OUT in their normal capacities. Either aCold Reset or a Warm Reset is required to restoreoperation to the CS4299-BQ. A Cold Reset will re-store all mixer registers to their power-on defaultvalues. A Warm Reset will not alter the values ofany mixer register, except clearing the PR4 bit inPowerdown Control/Status Register (Index 26h).

The PR5 bit powers down all analog and digitalsubsections of the device. A Cold Reset is the onlyway to restore operation to the CS4299-BQ after aPR5 global powerdown.

The CS4299-BQ does not automatically mute anyinput or output when the powerdown bits are ‘set’.The software driver controlling the AC ’97 devicemust manage muting the input and output analogsignals before putting the part into any power man-agement state. The definition of each PRx bit mayaffect a single subsection or a combination of sub-sections within the CS4299-BQ. Table 12 onpage 35 contains the matrix of subsections affectedby the respective PRx function. Table 13 onpage 35 shows the different operating power con-sumptions levels for different powerdown func-tions.

PR Bit Function

PR0 L/R ADCs and Input Mux Powerdown

PR1 Front DACs Powerdown

PR2 Analog Mixer Powerdown (Vref on)

PR3 Analog Mixer Powerdown (Vref off)

PR4 AC-link Powerdown (BIT_CLK off)*

PR5 Internal Clock Disable

PR6 Alternate Line Out Powerdown

* Applies only to primary codec

Table 11. Powerdown PR Bit Functions

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PR Bit ADCs DACs MixerAlternate Line Out

Analog Reference

ACLink

Internal Clock Off

PR0 •PR1 •PR2 • • •PR3 • • • • •PR4 •PR5 • • • • • • •PR6 •

Table 12. Powerdown PR Function Matrix

Power StateIDVdd (mA)

[DVdd=3.3 V]IDVdd (mA)[DVdd=5 V]

IAVdd (mA)

Full Power + SRC’s 29.1 50.2 37.9

Full Power + S/PDIF1 30.1 49.4 37.9

Full Power 24.5 43.4 37.9

ADCs off (PR0) 21.0 38.1 29.0

DACs off (PR1) 22.1 39.6 31.3

Audio off (PR2) 22.1 39.9 10.7

Vref off (PR3) 18.9 34.8 45 µA

AC-Link off (PR4) 19.3 35.5 37.9

Internal Clocks off (PR5) 11 µA 27 µA 45 µA

Alt line out off (PR6) 24.5 43.4 36.2

RESET 11 µA 27 µA 450 µA

Table 13. Power Consumption by Powerdown Mode1 Assuming standard resistive load for transformer coupled coaxial S/PDIF output

(Rload = 292 Ohm, DVdd = 3.3 V) (Rload = 415 Ohm, DVdd = 5 V). General: IDVdd S/PDIF = IDVdd + DVdd/Rload/2

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6. ANALOG HARDWARE DESCRIPTION

The analog line-level input hardware consists offour stereo inputs (LINE_IN_L/R, CD_L/GND/R,VIDEO_L/R, and AUX_L/R), two selectablemono microphone inputs (MIC1 and MIC2), andtwo mono inputs (PC_BEEP and PHONE). The an-alog line-level output hardware consists of a monooutput (MONO_OUT), and dual stereo line outputs(LINE_OUT_L/R and ALT_LINE_OUT_L/R).This section describes the analog hardware neededto interface with these pins. The designs presentedin this section comply with specifications detailedin Chapter 17 of the Microsoft® PC Design Guide-lines [7] (referred to as PC 99). For EMI reductiontechniques refer to the application note AN165:CS4297A/CS4299 EMI Reduction Techniques [5].

6.1 Analog Inputs

All analog inputs to the CS4299-BQ, includingCD_GND, should be capacitively coupled to theinput pins. Unused analog inputs should be tied to-gether and connected through a capacitor to analogground or tied to the Vrefout pin directly. The max-imum allowed voltage for analog inputs, except themicrophone input, is 1 VRMS. For the microphoneinput the maximum allowed voltage depends on theselected boost setting.

6.1.1 Line-Level Inputs

Figure 10 shows circuitry for a line-level stereo in-put. Replicate this circuit for the Line, Video andAux inputs. This design attenuates the input by6 dB, bringing the signal from the PC 99 specified2 VRMS, to the CS4299-BQ maximum allowed1 VRMS.

6.1.2 CD Input

The CD line-level input has an extra pin,CD_GND, providing a pseudo-differential inputfor both CD_L and CD_R. This pin takes thecommon-mode noise out of the CD inputs when

connected to the CD analog source ground. Follow-ing the reference designs in Figure 11 andFigure 12 provides extra attenuation of commonmode noise coming from the CD-ROM drive,thereby producing a higher quality signal. One per-cent resistors are recommended since closelymatched resistor values provide better com-mon-mode attenuation of unwanted signals. Thecircuit shown in Figure 11 can be used to attenuatea 2 VRMS CD input signal by 6 dB. The circuitshown in Figure 12 can be used for a 1 VRMS CD in-put signal.

6.8 kΩ

6.8 kΩ

1.0 µF

1.0 µF

R

L

6.8 kΩ6.8 kΩ

Figure 10. Line Input (Replicate for Video and Aux)

(All resistors 1%)

6.8 kΩ

CD_L

CD_COM

CD_R1.0 µ F

CD_L

CD_R

CD_GND

6.8 kΩ 1.0 µ F

3.4 kΩ

6.8 kΩ

2.2 µF

3.4 kΩ6.8 kΩ

AGND

Figure 11. Differential 2 VRMS CD Input

100 Ω

CD_L

CD_COM

CD_R1.0 µF

CD_L

CD_R

CD_GND

100 Ω 1.0 µ F

100 Ω

47 kΩ

2.2 µF

47 kΩ47 kΩ

AGND

Figure 12. Differential 1 VRMS CD Input

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6.1.3 Microphone Inputs

Figure 13 illustrates an input circuit suitable for dy-namic and electret microphones. Electret, or phan-tom-powered, microphones use the right channel(ring) of the jack for power. The design also sup-ports the recommended advanced frequency re-sponse for voice recognition as specified in PC 99.Note the microphone input to the CS4299-BQ hasan integrated pre-amplifier. Using the 20dB bit inthe Microphone Volume Register (Index 0Eh) thepre-amplifier gain can be set to 0 dB or 20 dB.Figure 14 shows an external pre-amplifier circuitfor an additional 18 dB gain.

6.1.4 PC Beep Input

The PC_BEEP input is useful for mixing the outputof the “beeper” (timer chip), provided in most PCs,with the other audio signals. When the CS4299-BQis held in reset, PC_BEEP is passed directly to theline output. This allows the system sounds or“beeps” to be available before the AC ’97 interfacehas been activated. Figure 15 illustrates a typicalinput circuit for the PC_BEEP input. If PC_BEEPis driven from a CMOS gate, the 4.7 kΩ resistorshould be tied to analog ground instead of +5VA.Although this input is described for a low-quality“beeper”, it is of the same high-quality as all otheranalog inputs and may be used for other purposes.

0.33 µF

220 pFNPO

3.3 µF+

6.8 K Ω

47 kΩ

MC33078 orMC33178

Vrefout

MIC1 or MIC2

1 µF +

0.33 µFX7R

2 kΩ

47 kΩ 0.1 µF

47 Ω

100 pFNPO

Figure 13. Microphone Input

AGND

4

8

+5 VA

100

12534

2.7

CGND

220 pF 220 pF

68

AGND

0.068 µF

X7R

AGND

+

-

AGND

4

1

8

+5 VAU1AMC33078D3

2

10 µF

AGND

+

47

AGND

+5 VA

47

+

-6.8

10 µF

AGND

+

65

220 pF

47 kΩ

U1BMC33078D

1 µF

X7R

7MIC1/MIC2

kΩ

kΩ

kΩ

kΩ

kΩ

kΩ

47 kΩ

Figure 14. Microphone Pre-amplifier

4.7 kΩ

PC_BEEP

+5VA (Low Noise) orAGND if CMOS Source

PC-BEEP-BUS47 kΩ

2.7 nFX7R

0.1 µFX7R

AGND

Figure 15. PC_BEEP Input

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6.1.5 Phone Input

One application of the PHONE input is to interfaceto the output of a modem analog front end (AFE)device so that modem dialing signals and protocolnegotiations may be monitored through the audiosystem. Figure 16 shows a design for a modemconnection where the output is fed from theCS4299-BQ MONO_OUT pin through a divider.The divider ratio shown does not attenuate the sig-nal, providing an output voltage of 1 VRMS. If alower output voltage is desired, the resistors can bereplaced with appropriate values, as long as the to-tal load on the output is kept greater than 10 kΩ.The PHONE input is divided by 6 dB to accommo-date a line-level source of 2 VRMS.

6.2 Analog Outputs

The analog line-level output section provides twostereo outputs and a mono output. TheLINE_OUT_L/R, ALT_LINE_OUT_L/R, and

MONO_OUT pins require 680 pF to 1000 pF NPOcapacitors between the corresponding pin and ana-log ground. Each analog output is DC-biased up tothe Vrefout signal reference, nominally 2.3 V. Thisrequires the outputs be AC-coupled to external cir-cuitry (AC load must be greater than 10 kΩ) or DCcoupled to a buffer op-amp biased at Vrefout.

6.2.1 Stereo Outputs

See Figure 18 for a line-level stereo output refer-ence design. See Figure 17 for a recommendedheadphone stereo output reference design.

6.2.2 Mono Output

The mono output, MONO_OUT, can be either asum of the left and right output channels, attenuat-ed by 6 dB to prevent clipping at full scale, or theselected Mic signal. The mono out channel candrive the PC internal mono speaker using an appro-priate buffer circuit

PHONE

MONO_OUT

PHONE

MONO_OUT

6.8 kΩ 1.0 µF

0 Ω

6.8 kΩ

1.0 µF

47 kΩ

AGND AGND

1000 pF

Figure 16. Modem Connection

ALT_LINE_OUT_R

ALT_LINE_OUT_L

27 kΩ

1000 pFNPO

AGND

3

21

220 µ FELEC

220 µ FELEC

+

+

1000 pFNPO

27 kΩ47 k Ω

AGND

22 pFNPO

39 kΩ

5

67

22 pFNPO

39 kΩ

+

-

+

-

TDA1308Vrefout

10 Ω1/4 Watt

10 Ω1/4 Watt

47 kΩ

HeadphoneOut

Figure 17. Alternate Line Output as Headphone Output

AGND

ALT_LINE_OUT_R

27 kΩ

1000 pFNPO

1000 pFNPO

1

2 3

4

AGND

0.1 µFY5V

220 µF

+5

-

39 kΩ

1

2 3

4

+3

-

22 pFNPO

22 pFNPO

6

2

7

1

TDA1308

TDA1308

ALT_LINE_OUT_L

VREFOUT

+ELEC 1/4 WATT

10 ΩHP_OUT_R

220 µF

+ELEC 1/4 WATT

10 ΩHP_OUT_L

47 kΩ

1

34

AGND

2

1 µF

Figure 18. Stereo Output

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6.3 Miscellaneous Analog Signals

The AFLT1 and AFLT2 pins must have a 1000 pFNPO capacitor to analog ground. These capacitorsprovide a single-pole low-pass filter at the inputs tothe ADCs. This makes low-pass filters at each ana-log input pin unnecessary.

The REFFLT pin must have a 1 µF and a 0.1 µF ca-pacitor connected to analog ground with a short,wide trace to this pin (see Figure 21 in Section 8,Grounding and Layout, for an example). The 1 µFcapacitor must not be replaced with any value high-er than 1 µF. No other connection should be made,as any coupling onto this pin will degrade the ana-log performance of the CS4299-BQ. Likewise, dig-ital signals should be kept away from REFFLT forsimilar reasons.

The Vrefout pin is typically 2.3 V and provides acommon mode signal for single-supply externalcircuits. Vrefout only supports light DC loads andshould be buffered if AC loading is needed. Fortypical use the Vrefout pin should have a 1 µF anda 0.1 µF capacitor connected to analog ground.

6.4 Power Supplies

The power supplies providing analog power shouldbe as clean as possible to minimize coupling intothe analog section which could degrade analog per-formance. The analog power pins, AVdd1 andAVdd2, supply power to all the analog circuitry onthe CS4299-BQ. The +5 V analog supply should begenerated from a linear voltage regulator (7805type) connected to a +12 V supply. This helps iso-late the analog circuitry from noise typically foundon +5 V digital supplies. A typical voltage regula-tor circuit for analog power using aMC78M05CDT +5 V regulator is shown inFigure 19. The digital power pins, DVdd1 andDVdd2, should be connected to the same digitalsupply as the controller AC-link interface. The dig-ital interface on the CS4299-BQ may operate at ei-ther +3.3 V or +5 V and proper connection of thesepins will depend on the digital power supply of thecontroller.

6.5 Reference Design

See Section 11 for a CS4299-BQ reference design.

Figure 19. Voltage Regulator

+12VD

AGNDDGND

+5VA

0.1µFY5V

10µFELEC+

10µFELEC+

MC78M05CDT

OUT3

GND

2

IN1

0.1µFY5V

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7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF)

The S/PDIF digital output is used to interface theCS4299-BQ to consumer audio equipment externalto the PC. This output provides an interface forstoring digital audio data or playing digital audiodata to digital speakers. Figure 20 illustrates thecircuits necessary for implementing the IEC-958optical or consumer interface. For further informa-tion on S/PDIF operation see application noteAN22: Overview of Digital Audio Interface DataStructures [3]. For further information on S/PDIFrecommended transformers see application noteAN134: AES and S/PDIF Recommended Trans-formers [4].

8. GROUNDING AND LAYOUT

Figure 21 on page 41 shows the conceptual layoutfor the CS4299-BQ. The decoupling capacitorsshould be located physically as close to the pins aspossible. Also note the connection of the REFFLTdecoupling capacitors to the ground return traceconnected directly to the ground return pin, AVss1.

It is strongly recommended that separate analogand digital ground planes be used. Separate groundplanes keep digital noise and return currents frommodulating the CS4299-BQ ground potential anddegrading performance. The digital ground pinsshould be connected to the digital ground plane andkept separate from the analog ground connections

of the CS4299-BQ and any other external analogcircuitry. All analog components and traces shouldbe located over the analog ground plane and all dig-ital components and traces should be located overthe digital ground plane.

The common connection point between the twoground planes (required to maintain a commonground voltage potential) should be located underthe CS4299-BQ. The AC-link digital interface con-nection traces should be routed such that the digitalground plane lies underneath these signals (on theinternal ground layer). This applies along the entirelength of these traces from the AC ’97 controller tothe CS4299-BQ.

Refer to the Application Note AN18: Layout andDesign Rules for Data Converters and OtherMixed Signal Devices [2] for more information onlayout and design rules.

1

2

3

45

6

0.1 µFR2

R1

J1

DGNDDVddR1R2

SPDIF_OUTS/PDIF_OUT

TOTX-173

SPDIF_OUT+5V_PCI

DGND

8.2 kΩDGND

DGND

3.3V247.5 Ω107.6 Ω

5V375 Ω

93.75 Ω

T1

Figure 20. S/PDIF Output

40 DS319-BQPP2

CS4299-BQ

CS4299-BQ

41

AnalogGround

Pin 1

0.1 µF

1000 pFNPO

1 µF

0.1 µFY5V

0.1 µFY5V

Y5V

0.1 µFY5V

AVdd2

AVss2

AFLT2 REFFLTAVss1 AVdd1

DVdd2

AFLT1

DigitalGround

DVss2

DVss1DVdd1

Vrefoutto via Via to +5VA

Via to +5VA

Via to AnalogGround

Via to AnalogGround

Via to Digital Ground

Via to +5VD or +3.3VD

Via to +5VD or +3.3VD

Figure 21. Conceptual Layout for the CS4299-BQ

DS319-BQPP2 41

CS4299-BQ

CS4299-BQ

42

9. PIN DESCRIPTIONS

CD

_

AU

X_

VID

EO

_

CD

_

MIC

PH

ON

AU

X_

VID

EO

_

CD

_GN

MIC

LIN

E_ I

N_

LIN

E_ I

N_

LL L R 2E R R D 1 L R

BPCFG

LINE_OUT_L

FLTI

AFLT1

REFFLT

LINE_OUT_R

FLTO

FLT3D

AFLT2

Vrefout

AVss1AVdd1

NC

AV

dd2

MO

NO

_OU

T

6

2

4

8

10

1

3

5

7

9

11

1213 14 15 16 17 18 19 20 21 22 23 24

31

35

33

29

27

36

34

32

30

28

26

25

48 47 46 45 44 43 42 41 40 39 38 37

CS

4299-xQBIT_CLK

XTL_IN

DVss1

SDATA_IN

SYNC

DVdd1

XTL_OUT

SDATA_OUT

DVdd2

RESET#PC_BEEP

DVss2

AL

T_L

INE

_OU

T_R

AL

T_L

INE

_OU

T_L

NCEA

PD

ID0#

S/P

DIF

_OU

T

ID1#

NC

AV

ss2

(48-Pin LQ

FP

)

Figure 22. Pin Locations for the CS4299-BQ

42 DS319-BQPP2

CS4299-BQ

CS4299-BQ

43

Audio I/O

PC_BEEP - Analog Mono Source, Input, Pin 12

The PC_BEEP input is intended to allow the PC system POST (Power On Self-Test) tones to passthrough to the audio subsystem. The PC_BEEP input has two connections: the first connection is to theanalog output mixer, the second connection is directly to the LINE_OUT stereo outputs. While theRESET# pin is actively being asserted and the BCFG pin is left floating, the PC_BEEP bypass path tothe LINE_OUT outputs is enabled. While the CS4299-BQ is in normal operation mode, with RESET#deasserted or BCFG grounded, PC_BEEP is a monophonic source to the analog output mixer. Themaximum allowable input is 1 VRMS (sinusoidal). This input is internally biased at the Vrefout voltagereference and requires AC-coupling to external circuitry. If this input is not used, it should be connectedto the Vrefout pin or AC-coupled to analog ground.

PHONE - Analog Mono Source, Input, Pin 13

This analog input is a monophonic source to the analog output mixer. It is intended to be used as amodem subsystem input to the audio subsystem. The maximum allowable input is 1 VRMS (sinusoidal).This input is internally biased at the Vrefout voltage reference and requires AC-coupling to externalcircuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analogground.

MIC1 - Analog Mono Source, Input, Pin 21

This analog input is a monophonic source to the analog output mixer. It is intended to be used as adesktop microphone connection to the audio subsystem. The CS4299-BQ internal mixer's microphoneinput is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 VRMS(sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling toexternal circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled toanalog ground.

MIC2 - Analog Mono Source, Input, Pin 22

This analog input is a monophonic source to the analog output mixer. It is intended to be used as analternate microphone connection to the audio subsystem. The CS4299-BQ internal mixer's microphoneinput is MUX selectable with either MIC1 or MIC2 as the input. The maximum allowable input is 1 VRMS(sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC-coupling toexternal circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled toanalog ground.

LINE_IN_L, LINE_IN_R - Analog Line Source, Inputs, Pins 23 and 24

These inputs form a stereo input pair to the CS4299-BQ. The maximum allowable input is 1 VRMS(sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-couplingto external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin orboth AC-coupled, with separate AC-coupling caps, to analog ground.

CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20

These inputs form a stereo input pair to the CS4299-BQ. It is intended to be used for the Red Book CDaudio connection to the audio subsystem. The maximum allowable input is 1 VRMS (sinusoidal). Theseinputs are internally biased at the Vrefout voltage reference and require AC-coupling to externalcircuitry. If these inputs are not used, they should both be connected to the Vrefout pin or bothAC-coupled, with separate AC-coupling caps, to analog ground.

CD_GND - Analog CD Common Source, Input, Pin 19

This analog input is used to remove common mode noise from Red Book CD audio signals. Theimpedance on the input signal path should be one half the impedance on the CD_L and CD_R inputpaths. This pin requires AC-coupling to external circuitry. If this input is not used, it should be connectedto the Vrefout pin or AC-coupled to analog ground.

DS319-BQPP2 43

CS4299-BQ

CS4299-BQ

44

VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17

These inputs form a stereo input pair to the CS4299-BQ. It is intended to be used for the audio signaloutput of a video device. The maximum allowable input is 1 VRMS (sinusoidal). These inputs areinternally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If theseinputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, withseparate AC-coupling caps, to analog ground.

AUX_L, AUX_R - Analog Auxiliary Source, Inputs, Pins 14 and 15

These inputs form a stereo input pair to the CS4299-BQ. The maximum allowable input is 1 VRMS(sinusoidal). These inputs are internally biased at the Vrefout voltage reference and require AC-couplingto external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin orboth AC-coupled, with separate AC-coupling caps, to analog ground.

LINE_OUT_L, LINE_OUT_R - Analog Line-Level, Outputs, Pins 35 and 36

These signals are analog outputs from the stereo output mixer. The full-scale output voltage for eachoutput is nominally 1 VRMS (sinusoidal). These outputs are internally biased at the Vrefout voltagereference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biasedat the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground.

ALT_LINE_OUT_L, ALT _LINE_OUT_R - Analog Alternate Line-Level, Outputs, Pins 39 and 41

These signals are analog outputs from the stereo output mixer. The full-scale output voltage for eachoutput is nominally 1 VRMS (sinusoidal). These outputs are internally biased at the Vrefout voltagereference and require either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biasedat the Vrefout voltage. These pins need a 680-1000 pF NPO capacitor attached to analog ground.

MONO_OUT - Analog Mono Line-Level, Output, Pin 37

This signal is an analog output from the stereo-to-mono mixer or MIC1/2. The full-scale output voltagefor this output is nominally 1 VRMS (sinusoidal). This output is internally biased at the Vrefout voltagereference and requires either AC-coupling to external circuitry or DC-coupling to a buffer op-amp biasedat the Vrefout voltage. This pin needs a 680-1000 pF NPO capacitor attached to analog ground.

Clock and Configuration

XTL_IN - Crystal Input/Clock Input, Pin 2

In primary mode this pin requires either a 24.576 MHz crystal, with the other pin attached to XTL_OUT,or an external CMOS clock. The crystal frequency must be 24.576 MHz and designed for fundamentalmode, parallel resonance operation. If an external CMOS clock is used to drive this pin, it must run at24.576 MHz. In secondary mode all timing is derived from the BIT_CLK input signal and this pin shouldbe left floating.

XTL_OUT - Crystal Output, Pin 3

This pin is used when a crystal is placed between XTL_OUT and XLT_IN. If an external 24.576 MHzclock is used on XTL_IN, this pin must be left floating with no traces or components connected to it. Insecondary mode this pin should be left floating.

ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46

These pins select the Codec ID and mode of operation for the CS4299-BQ. They are only sampled afterthe rising edge of RESET#. These pins are internally pulled up to the digital supply voltage and shouldbe left floating for logic ‘0’ or tied to digital ground for logic ‘1’. When both pins are left floating theCS4299-BQ is the primary codec. If either or both pins are tied to ground the CS4299-BQ is asecondary codec.

44 DS319-BQPP2

CS4299-BQ

CS4299-BQ

45

Analog Reference, Filters, and Configuration

REFFLT - Internal Reference Voltage, Input, Pin 27

This signal is the voltage reference used internal to the CS4299-BQ. A 0.1 µF and a 1.0 µF (must notbe larger than 1 µF) capacitor with short, wide traces must be connected to this pin. No otherconnections should be made to this pin.

Vrefout - Voltage Reference, Output, Pin 28

All analog inputs and outputs are centered around Vrefout, nominally 2.3 Volts. This pin may be used tolevel shift external circuitry. This pin cannot drive any DC loads, thus any external loading must bebuffered.

AFLT1 - Left ADC Channel Antialiasing Filter, Input, Pin 29

This pin needs a 1000 pF NPO capacitor connected to analog ground.

AFLT2 - Right ADC Channel Antialiasing Filter, Input, Pin 30

This pin needs a 1000 pF NPO capacitor connected to analog ground.

FLTI, FLTO - 3D Filter, Input, Pin 33 and 34A 1000 pF capacitor must be connected between FLTI and FLTO if the 3D function is used.

FLT3D - 3D Filter, Input, Pin 32A 0.01 µF capacitor must be connected from this pin to AGND if the 3D function is used.

BCFG - Beep Configuration, Input, Pin 31This pin is the configuration control for the PC_BEEP bypass path. If this pin is grounded, the bypasspath is disabled. If this pin is left floating, the PC_BEEP bypass path is enabled.

Misc. Digital Interfaces

S/PDIF_OUT - Sony/Philips Digital Interface, Output, Pin 48

This pin generates the S/PDIF digital output from the CS4299-BQ when the SPEN bit in the S/PDIFControl Register (Index 68h) is ‘set’. This output may be used to directly drive a resistive divider andcoupling transformer to an RCA-type connector for use with consumer audio equipment.

EAPD - External Amplifier Powerdown, Output, Pin 47

This pin is used to control the powerdown state of an audio amplifier external to the CS4299-BQ. Theoutput is controlled by the EAPD bit in the Powerdown Ctrl/Stat Register (Index 26h). It is driven as anormal CMOS output and defaults low (‘0’) upon power-up.

DS319-BQPP2 45

CS4299-BQ

CS4299-BQ

46

AC-Link

RESET# - AC ’97 Chip Reset, Input, Pin 11

This active low signal is the asynchronous Cold Reset input to the CS4299-BQ. The CS4299-BQ mustbe reset before it can enter normal operating mode.

SYNC - AC-Link Serial Port Sync pulse, Input, Pin 10

This signal is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximumsample rate, 48 kHz. The signal is generated by the controller, synchronous to BIT_CLK. SYNC is anasynchronous input when the CS4299-BQ is configured as a primary audio codec and is in a PR4powerdown state. A series terminating resistor of 47 Ω should be connected on the signal near theSYNC source.

BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6

This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a12.288 MHz output clock derived from a 24.576 MHz crystal on the XTL_IN input clock. When theCS4299-BQ is in secondary mode, this signal is an input which controls the AC-link serial interface andgenerates all internal clocking including the AC-link serial interface timing and the analog samplingclocks. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4299-BQin primary mode or close to the BIT_CLK source in secondary mode.

SDATA_OUT - AC-Link Serial Data Input Stream to AC ’97, Input, Pin 5

This input signal receives the control information and digital audio output streams. The data is clockedinto the CS4299-BQ on the falling edge of BIT_CLK. A series terminating resistor of 47 Ω should beconnected on this signal near the controller.

SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8

This output signal transmits the status information and digital audio input streams from the ADCs. Thedata is clocked out of the CS4299-BQ on the rising edge of BIT_CLK. A series terminating resistor of47 Ω should be connected on this signal as close to the CS4299-BQ as possible.

Power Supplies

DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9

Digital supply voltage for the AC-link section of the CS4299-BQ. These pins can be tied to +5 V digitalor to +3.3 V digital. The CS4299-BQ and controller AC-link should share a common digital supply

DVss1, DVss2 - Digital Ground, Pins 4 and 7

Digital ground connection for the AC-link section of the CS4299-BQ. These pins should be isolated fromanalog ground currents.

AVdd1, AVdd2 - Analog Supply Voltage, Pins 25 and 38

Analog supply voltage for the analog and mixed signal sections of the CS4299-BQ. These pins must betied to the analog +5 V power supply. It is strongly recommended that +5 V be generated from avoltage regulator to ensure proper supply currents and noise immunity from the rest of the system.

AVss1, AVss2 - Analog Ground, Pins 26 and 42

Ground connection for the analog, mixed signal, and substrate sections of the CS4299-BQ. These pinsshould be isolated from digital ground currents.

46 DS319-BQPP2

CS4299-BQ

CS4299-BQ

47

10. PARAMETER AND TERM DEFINITIONSAC ’97 Specification

Refers to the Audio Codec ’97 Component Specification Ver 2.1 published by the Intel® Corporation [6].

AC ’97 Controller or Controller

Refers to the control chip which interfaces to the audio codec AC-link. This has been also called DC ’97for Digital Controller ’97 [6].

AC ’97 Registers or Codec Registers

Refers to the 64-field register map defined in the AC ’97 Specification.

ADC

Refers to a single Analog-to-Digital converter in the CS4299-BQ. “ADCs” refers to the stereo pair ofAnalog-to-Digital converters. The CS4299-BQ ADCs have 18-bit resolution.

Codec

Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is theCS4299-BQ.

DAC

Refers to a single Digital-to-Analog converter in the CS4299-BQ. “DACs” refers to the stereo pair ofDigital-to-Analog converters. The CS4299-BQ DACs have 20-bit resolution.

dB FS A

dB FS is defined as dB relative to full-scale. The “A” indicates an A weighting filter was used.

Differential Nonlinearity

The worst case deviation from the ideal code width. Units in LSB.

Dynamic Range (DR)

DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in thepresence of a signal, available at any instant in time (no change in gain settings betweenmeasurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A.

FFT

Fast Fourier Transform.

Frequency Response (FR)

FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitudecorner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. Thelisted minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequencyto maximum frequency inclusive.

Fs

Sampling Frequency.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, thedifference in output voltages for each channel when both channels are fed the same code. Units are indB.

DS319-BQPP2 47

CS4299-BQ

CS4299-BQ

48

Interchannel Isolation

The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1kHz, 0 dB, signal present on the other line input channel. Units are in dB.

Line-level

Refers to a consumer equipment compatible, voltage driven interface. The term implies a low driverimpedance and a minimum 10 kΩ load impedance.

Paths

A-D: Analog in, through the ADCs, onto the serial link.

D-A: Serial interface inputs through the DACs to the analog output.

A-A: Analog in to Analog out (analog mixer).

PC 99

Refers to the PC 99 System Design Guide published by the Microsoft® Corporation [7].

PLL

Phase Lock Loop. Circuitry for generating a desired clock from an external clock source.

Resolution

The number of bits in the output words to the DACs, and in the input words to the ADCs.

Signal to Noise Ratio (SNR)

SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor,in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB.

S/PDIF

Sony/Phillips Digital Interface. This interface was established as a means of digitally interconnectingconsumer audio equipment. The documentation for S/PDIF has been superseded by the IEC-958consumer digital interface document.

SRC

Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. TheCS4299-BQ operates at a fixed sample frequency of 48 kHz. The internal sample rate converters areused to convert digital audio streams playing back at other frequencies to 48 kHz.

Total Harmonic Distortion plus Noise (THD+N)

THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMSfull-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHzbandwidth with units in dB FS.

48 DS319-BQPP2

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49

11. REFERENCE DESIGN

R21

6.8K

R16

6.8K

C33

22pF

NP

O

C34

22pF

NP

O

C7

1uF

Y5V

C10

0.1u

F

X7R

J1 2X1H

DR

-SN

/PB

12

C20

1uF

Y5V

R14

6.8K

C11

0.1u

F

X7R

C4

0.1u

F

X7R

R1

47K R

66.

8K

C8

0.1u

F

X7R

J4

PH

ON

O-1

/8

4 3 5 2 1

C5

0.1u

F

X7R

C23

0.1u

F

X7R

C22

1uF

Y5V

R4

6.8K

J5

PH

ON

O-1

/8

4 3 5 2 1

C9

0.1u

F

X7R

C24

1uF

Y5V

C3

10uF

ELE

C

+

R8

47

R3

6.8K

C18

1000

pF

NP

O

Y1

24.5

76 M

Hz

J3 4X1H

DR

-AU

1234

R10

100K

C21

1uF

Y5V

C6

10uF

ELE

C

+

C12

1uF

Y5V

J2 4X1H

DR

-AU

1234

R9

100K

C31

0.1u

F

X7R

C19

1000

pF

NP

O

U3

CS

4299

LIN

E_O

UT

_R36

MO

NO

_OU

T37

AVdd238

ALT

_LIN

E_O

UT

_L39

nc7

44

ALT

_LIN

E_O

UT

_R41

AVss242

nc6

43nc

540

FLTO34

FLTI33

FLT

3D32

BC

FG

31

DVdd11

XTL_IN2

XTL_OUT3

DV

ss1

4

SD

AT

A_O

UT

5B

IT_C

LK6

DV

ss2

7

SD

AT

A_I

N8

SY

NC

10

DVdd29

RE

SE

T#

11P

C_B

EE

P12

PH

ON

E13

AU

X_L

14A

UX

_R15

VID

EO

_L16

VID

EO

_R17

CD

_L18

CD

_GN

D19

CD

_R20

MIC

121

MIC

222

LIN

E_I

N_L

23LI

NE

_IN

_R24

AVdd125

AVss126

RE

FF

LT27

Vre

fout

28

AF

LT1

29

AF

LT2

30

S/P

DIF

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T48

EA

PD

47

ID1#

46ID

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E_O

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_L35

R5

6.8K

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TO

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1234 5 6

R15

6.8K

C30

1uF

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C13

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R7

47

C2

2700

pF

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60 m

il tr

ace

GN

D_T

IE

C29

1000

pF

NP

O

R11

100K

C1

0.1u

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X7R

C28

0.01

uF

X7R

U1

MC

78M

05A

CD

T OU

T3

GND2

IN1

J7

PH

ON

O-1

/8

4 3 5 2 1

C27

1000

pF

NP

O

C14

1uF

Y5V

R17

6.8K

C26

1000

pF

NP

O

R20

100

R19

1.5K

C25

0.1u

F

X7R

R18

2.2K

C15

10uF

ELE

C

+

C17

10uF

ELE

C

+

C32

10uF

ELE

C

+

R2

6.8K

R12

220K

C16

1uF

Y5V

R13

220K

AG

ND

AG

ND

AG

ND

AG

ND

DG

ND

AG

ND

AG

ND

DG

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AG

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AG

ND

DG

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+5V

A+

12V

AG

ND

AG

ND

+3.

3VD

AG

ND

AG

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DG

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DS319-BQPP2 49

CS4299-BQ

CS4299-BQ

50

12. REFERENCES

1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997http://www.cirrus.com/products/papers/meas/meas.html

2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,Version 6.0, February 1998

3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.0, February 1998

4) Cirrus Logic, AN134: AES and S/PDIF Recommended Transformers, Version 2, April 1999

5) Cirrus Logic, AN165: CS4297A/CS4299 EMI Reduction Techniques, Version 1.0, September 1999

6) Intel®, Audio Codec ’97 Component Specification, Revision 2.1, May 1998http://developer.intel.com/ial/scalableplatforms/audio/index.htm

7) Microsoft®, PC 99 System Design Guide, Version 1.0, July 1999http://www.microsoft.com/hwdev/desguid/

8) Intel® 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub, June 1999http://developer.intel.com/design/chipsets/datashts/290655.htm

50 DS319-BQPP2

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51

13. PACKAGE DIMENSIONS

INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAX

A --- 0.055 0.063 --- 1.40 1.60A1 0.002 0.004 0.006 0.05 0.10 0.15B 0.007 0.009 0.011 0.17 0.22 0.27D 0.343 0.354 0.366 8.70 9.0 BSC 9.30D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10E 0.343 0.354 0.366 8.70 9.0 BSC 9.30E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60L 0.018 0.24 0.030 0.45 0.60 0.75∝ 0.000° 4° 7.000° 0.00° 4° 7.00°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm.JEDEC Designation: MS022

48L LQFP PACKAGE DRAWING

E1

E

D1D

1

e

L

∝

B

A1

A

DS319-BQPP2 51

CS4299-BQ

CS429 9 -BQ CS4299-BQ - statics.cirrus.com · T he CS429 9 -BQ is an A C’97 2.1 compatible stereo...

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