CS294-6 Reconfigurable Computing Day4 September 3, 1998 VLSI Scaling.
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Transcript of CS294-6 Reconfigurable Computing Day4 September 3, 1998 VLSI Scaling.
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CS294-6Reconfigurable Computing
Day4
September 3, 1998
VLSI Scaling
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Why Care?
• In this game, we must be able to predict the future
• Rapid technology advance
• Reason about changes and trends
• re-evaluate prior solutions given technology at time X.
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Scaling
• Premise: features scale “uniformly”– everything gets better in a predictable manner
• Parameters: (lambda) -- Mead and Conway (class)– S -- Bohr– 1/ -- Dennard
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Feature Size
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Scaling
• Channel Length (L)• Channel Width (W)
• Oxide Thickness (Tox)
• Doping (Na)
• Voltage (V)
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Scaling
• Channel Length (L) • Channel Width (W) • Oxide Thickness (Tox)
• Doping (Na) 1/• Voltage (V)
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Effects?
• Area• Capacitance• Resistance
• Threshold (Vth)
• Current (Id)
• Gate Delay (gd)
• Wire Delay (wire)
• Power
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Area
L * W
m m• 50% area• 2x capacity same area
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Area Perspective
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Capacitance
• Capacitance per unit area– Cox=SiO2
/Tox
– ToxTox/
– Cox Cox
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Capacitance
• Gate Capacitance– Cgate= A*Cox
– Cox Cox
– Cgate Cgate /
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Threshold Voltage
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Threshold Voltage
• VTHVTH
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Current
• Saturation Current– Id=(COX/2)(W/L)(Vgs-VTH)2
– Vgs=VV
– VTHVTH
– WW– Cox Cox
– IdId
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Gate Delay
gd=Q/I=(CV)/I
• VV
• IdId
• C C /
gd gd /
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Resistance
• R=L/(W*t)
• WW
• R R
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Wire Delay
wire=RLC
• R R
• C C /
wire wire
• …assuming (logical) wire lengths remain constant...
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Power Dissipation (Static)
• Resistive Power– P=V*I
– VV
– IdId
– PP
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Power Dissipation (Dynamic)
• Capacitive (Dis)charging– P=(1/2)CV2f
– VV
– C C /
– PP
• Increase Frequency?– f f ?
– P P
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Effects?
• Area 1/
• Capacitance 1/• Resistance • Threshold (Vth) 1/
• Current (Id) 1/
• Gate Delay (gd) 1/
• Wire Delay (wire) 1
• Power 1/1/
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Delays?
• If delays in gates/switching?
• If delays in interconnect?
• Logical interconnect lengths?
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Delays?
• If delays in gates/switching?– Delay reduce with 1/
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Delays
• Logical capacities growing
• Wirelengths?– No locallity– Rent’s Rule
• L n(p-0.5)
• [p>0.5]
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Capacity
• Rent: IO=C*Np
• p>0.5• AC*N2p
• Logical Area
AC*N22p
N2p N22p
N2 p) N
• Sanity Check– p=1
– N2 N
– p~0.5
– N2 N
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Compute Density
>compute density scaling>
gates dominate, p<0.5moderate p, good fraction of gate delaylarge p (wires dominate area and delay)
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Power Density
• PP (static, or increase frequency)
• PP(dynamic, same freq.)
• P/A P/A … or … P/A
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Scaling Summary
• Uniform scaling reasonably accurate for past couple of decades
• Area increase
– Real capacity maybe a little less?
• Gate delay decreases (1/)
• Wire delay not decrease, maybe increase
• Overall delay decrease less than (1/)