CS 2630 Computer...
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CS 2630 Computer Organization What did we accomplish in 8 weeks? Brandon Myers University of Iowa
Transcript of CS 2630 Computer...
CS2630ComputerOrganization
Whatdidweaccomplishin8weeks?BrandonMyers
UniversityofIowa
Courseevaluations
• ICON|student(course?)tools|Evaluations
Whytake2630?
• Brandon’sesotericanswer:graduatesofaComputer Scienceprogramshouldhaveanappreciationforhowrealcomputers work• ACMandIEEE’sanswer:ComputerOrganizationandArchitectureisatopicinComputerScienceCurricula2013(https://www.acm.org/education/CS2013-final-report.pdf )• Butmoreconcretely...
require
Whytake2630?require
1.Itwillbeuptoyoutodesignournewcomputersystems(softwareANDhardware)...computerarchitectshavebeenpanickingfornearlyadecadeandtheyarenot calmingdown
2.atsomepointyouwillbehavetomeasureasystemyou’vebuilt:performance(latency&throughput),energyusage,reliability,...Tobeabletomeasure/interpret/improveyoursystem,ithelpstounderstandhowmoreofthecomputerworks
https://commons.wikimedia.org/wiki/File:Toyota_mirai_trimmed.jpg
Whatmetricswouldyoumeasuretoknowhowgoodacaris?
Whatcantheengineerdotochangethevaluesofthosemetrics?
Whytake2630?require
Theinsightsyoubroughttothecourse:CATopics
App
High-levellanguage(e.g.,C,Java)
Instructionsetarchitecture(e.g.,MIPS)
Compiler
Operatingsystem(e.g.,Linux,Windows)
Memorysystem I/OsystemProcessor
Datapath &Control
Digitallogic
Circuits
Devices(e.g.,transistors)
Physics
lw $t0, 4($s0)addi $t0, $t0, 10sw $t0, 8($s0)
YoulearnedhowtowriteassemblycodeinHW2(usuallythecompilerdoestheworkforus)
rug:don’tneedtowriteassemblycodeforaparticulararchitecture.InsteadwriteportableJava/Python/Ccode
bumps:someCcodeisn’tportable;someprogrammerswritesnippetsofassemblycodewhenthecompilerdoesn’tdothebestthing
100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000
lw $t0, 4($s0)addi $t0, $t0, 10sw $t0, 8($s0)
Project1– MiniMAtheMIPSassemblerrug:wecanwriteMIPS
programsinalanguagemadeofhuman-readablecharacters,usepseudoinstructions,refertolabelseventhoughthemachinereadsbinarynumbers
100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000
lw $t0, 4($s0)addi $t0, $t0, 10sw $t0, 8($s0)
100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000
100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000
100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000100001000001011111000000001111000011100100001101010000000000100000000110000010000000000000001000100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000
math.astdlib.a
browser.exe
rug: linkerallowsustowriteourprogramsmodularly
PEERINSTRUCTION(actually,asurvey)stronglyagreeagreeneutraldisagreestronglyagree
abcde
1. Iunderstandtherelationshipbetweenbits,numbers,andinformation.
2. Iunderstandthestoredprogramconcept3. Iunderstandtheroleoftheinstructionsetarchitectureina
computer4. Iunderstandwhyabstractionsareessentialforbuildingcomplex
systems5. Iunderstandwhythedigitalabstractionisimportant6. Iunderstandwhythesynchronousabstractionisimportant7. Iunderstandthetradeoffsinthememoryhierarchy8. Iunderstandhowproblemscanbedecomposedintoadatapath and
acontrol9. Iappreciatethelayersofthecomputingstackandwhytheymay
needtochangeinthenearfuture.
100011100000100000000000000001000010000100001000000000000000101010101110000010000000000000001000
browser.exe
InProject2-2youplayedtheroleoftheLoaderbyloadingyourheximageintotheInstructionmemory
rug: ourprogramhastheillusionofhavingaccesstotheentireaddressspace(e.g.all232bytes)ofthecomputer
Project2-2,youdesigned,built,andtestedaprocessorthatrunsassembledMIPSprograms datapath andcontrol
rug:machinecodefortheMIPSarchitectureoughttorunonanyMIPSprocessor,regardlessofitsdesign(itsmicroarchitecture)
bumps:choicesaboutthearchitecturesometimesarebasedonassumptionsaboutthemicroarhitecture (e.g.,MIPSbranchdelayslot).
Project2-1,HW4youbuiltcomponents(likeregisterfilesandfinitestatemachines)fromsequentiallogic
rug:wecanbuildacomplexsystemoutofbasiccomponents.Synchronous abstractionallowsustonothavetoworryaboutinterfacesbetweencomponents
Digitallogic
Circuits
Instructionsetarchitecture(e.g.,MIPS)
GPUinstructionsetneuralnetwork
structureandweights
Youdon’thavetobuildthe5-stagepipelinedMIPSprocessor
http://people.cs.pitt.edu/~cho/cs2410/papers/yeager-micromag96.pdf
MIPSR10000(out-of-ordersuperscalar)
youdon’thavetobuildaMIPSprocessor
systolicarrayandcontrol
everycomponentismadeoflogicgates;youlearnedhowtobuildlogiccircuitsinHW3
logicgatemadeofpMOS andnMOStransistorsarrangedinaCMOSconfiguration
rug: ItisabiteasierjusttothinkofgatesthatarefunctionsasopposedtotransistorsattachingoutputtoVsource orVground
rug:CMOSensureseverygatehasapure0or1output!Thisideaisthedigitalabstractionthatletsthelayersabovecomposetwoelectricalcircuitswithoutworryingabouthowtheyaffecteachother.
layoutengineer’sviewofaNORgate
https://commons.wikimedia.org/wiki/File:NOR_gate_layout.png
rug:Whenbuildingafunctionaldigitallogiccircuit,noneedtoworryabouthowitisarrangedonthesilicon
https://commons.wikimedia.org/wiki/File:NOR_gate_layout.png
nMOScrosssection
https://commons.wikimedia.org/wiki/File:MOSFET_functioning_body.svg
rug:deviceengineersprovidelayoutengineerswith“designrules”.Iftheyobeytherequiredspacingbetweencomponentsthenthetransistorswillwork
OFF ON
rug:WhenoperatingatransistorinthesaturationregimesitlookslikeanelectricalswitchbetweenvoltagesGNDandVDD.Partofsupportingthedigitalabstraction.
It’snotenoughtojustbuildsoftwarethesedays
ProjectCatapult:customhardwarerunningpartofBingsearch
computervisionprocessorsrunningGoogle’saugmentedrealityplatformTango
“holographic”processorforMicrosoft’saugmentedrealityplatformHoloLens
Sparc M7chipisbuiltspecificallyforforacceleratingdatabasequeries
allinproductionnotjustresearch
GoogleTPUisbuiltformachinelearning
LifebeyondLogisim?• Logisim’s mainmodeofinputisschematicentry
• Muchdigitallogicdesignuseshardwaredescriptionlanguages(HDL)likeVerilog(lookupVeriloginyourtextbookindex)• HDLisnotmuchdifferentthanwhatyoudid,exceptitistextualinsteadofgraphical
• Typicallyhavepowerfulcompilersthanmakedevelopmenteasier thanusingLogisim,e.g.,writeastatementlike
case(ALUCtrl){0:R=X+Y1:R=X-Y…
}AndyougetanALU!
Didwereallybuildarealprocessor?
• Yes!YouimplementedmuchoftheMIPSInstructionSetArchitecture.YourProject2-2couldrunLinux(at4KHzclockfrequency)givenabootloaderprogramandLinuxcompiledforMIPS
No,Imeanlikereal hardware
No,Imeanlikereal hardware
Ifweuseahardwarecompiler,wecouldturnyourlogisim files(lookinside;it’sjustsomeXMLlistingabunchofcomponentsandwires)intoanFPGAdesignorstandard-cellVLSIdesign
moretolearnabouthowtodealwiththedetailsofthesedesignflows,butyouhaveagoodstartingpoint
Administrivia
• FinalExam• Friday,10am-12in205MLH!• opennotes/book,noelectronics• reminder:practicematerialsonICONinFiles|Exams
• Reviewtomorrowinclass• takeatleastoneofthepreviousfinalexamsandgradeyourself• comepreparedwiththelistofproblemsorspecificquestions
StuffinyourtextbookIrecommendyoulookat!
• Ch 3.4FiniteStateMachines• statetransitiondiagramsaretosequentiallogicAStruthtablesaretocombinationallogic• involvesideasthatrelatetootherpartsofCS,likefiniteautomata
• Ch 8Memorysystems• Howdowedealwiththetradeoffbetweencapacityandspeedinmemorytechnologies?(oneanswer:caches)• Howdoweruntwoprogramsonthecomputersimultaneouslyifboththinktheyownthewholeaddressspace?(oneanswer:virtualmemory)
Whatcoursesnext?• CS:3620OperatingSystems
• CS:3210ProgramminglanguagesandTools(inC++)
• CS:3640IntroductiontoNetworksandTheirApplications
• CS:3820ProgrammingLanguageConcepts
• CS:4640 ComputerSecurity
• CS:4700HighPerformanceandParallelComputing
• CS:5610:Highperformancecomputerarchitecture
• CS:4980TopicsinCS(CompilerConstructiononraspberrypi)• CS:4980TopicsinCS(AdvancedComputerArchitecturethisSpring!)
What’stolearnnext:operatingsystems
Questionswedidn’tgettoanswerfullyinCS2630Operatingsystems
• howdomultipleprogramssharethecomputer?• 2-64processors• 1 networkinterface• 1 memory• 1keyboard,mouse,screen• 100’sofrunningprograms
• howdoyoukeepprogramsisolatedfromeachotheroroneprogramfromconsumingallresources?
• howdoyouimplementsyscalls?
• howdoyouloadtheOScodeintomemorywhenyoupoweronthecomputer?
What’stolearnnext:computerarchitecture
What’stolearnnext:computerarchitecture
• theroleofparallelisminmicroarchitectures
• everyimplementationanditseffectonperformance...
𝑠𝑒𝑐𝑜𝑛𝑑𝑠𝑝𝑟𝑜𝑔𝑟𝑎𝑚 =
𝑠𝑒𝑐𝑜𝑛𝑑𝑠𝑐𝑦𝑐𝑙𝑒 ∗
𝑐𝑦𝑐𝑙𝑒𝑠𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 ∗
𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠𝑝𝑟𝑜𝑔𝑟𝑎𝑚
...andcostandenergy
Parallelisminarchitecturespipelining
vector
superscalar
dataflow
andothers...multicore,VLIW,multithreading,...
Vectormachinesfoundin...• earlysupercomputers
• IntelAVX• GPUs
SIMD:singleinstruction,multipledata
Superscalarmachines
Replicateresources,e.g.,• twodecoders,2-wide
instructioncachereadport:fetchtwoinstructionsatatime
• twoALUs:executetwoinstructionsatatime
• moreregisterfilewriteports:writebacktworegistersinonecycle
foundin...mostCPUsinserversandsmartphones
superscalar+pipelining
superscalar
Dataflowmachinesaprocessorneedstogettheinstructionandtheinputdatatothesamephysicalplaceatthesametime(knownas“dataflowlocality”)
DataflowmachineshaveabunchofExecutionunitsofvariouskind;thedata”flows”throughtheoperators
Challenges?
What’stolearnnext:parallelcomputing
Metricforperformancecomparison:Time
Myprogramrunsin100seconds
IfI“parallelizeit”on10processorsIsawthatitrunsin12seconds
Whatisthespeedup?
Tserial /Tparallel =100/12=8.33X
Predictingparallelrunningtime(Tpar)fromserialrunningtimeMyprogramrunsinTser =100seconds
IfI“parallelizeit”on10processors,howfastwillitrun(i.e.,whatisTpar)?
𝑇4567689:𝑇6;<54=>?
=1
1 − 𝑟 + 𝑟𝑠
𝑇6;<54=>? = 𝑇4567689: ∗ ( 1 − 𝑟 ∗ 1 + 𝑟 ∗1𝑠)
Inthisform,itiscalledAmdahl’slaw:saysyourspeedupislimitedbyhowmuchoftheprogramisimproved(e.g.,parallelize)
r=fractionofprogramthatisabletobeimproveds=speedupwhenapplyingtheimprovement
https://en.wikipedia.org/wiki/Amdahl's_law#/media/File:AmdahlsLaw.svg
Amdahl’slawappliedtoparallelization
r
s
Asequentialabstractmachinemodelyoualreadyknow
• RAM:randomaccessmemory• justlikeanyothercomputationalstep,accessingmemoryiscostof1
memory
processor
RAM
Oneofthefoundationalparallelmachinemodels:ParallelRandomAccessMachine(PRAM)• Allprocessorsareattachedtoasharedmemory
• Memoryaccesstakes1step
• MorerealisticvariantsofPRAMincurgreatercostfor“conflicting”memoryaccesses
• usedveryoftenforunderstandingthespeeduplimitsofparallelalgorithms;notveryrealistic
Oneofthefoundationalparallelmachinemodels:Bulksynchronousparallel(BSP)
https://en.wikipedia.org/wiki/Bulk_synchronous_parallel
w1 w2wp
𝑙
ℎ6
(seeblackboardnotes)
thisabstractmachinedoesnotsupportasmanyalgorithmsasCTA,butitissimpler
ThefutureofCS2630• Stayintouch!• TellothershowawesomeCS2630is!• Signuptobeanapprovedtutor!https://cs.uiowa.edu/resources/approved-tutors
• CS2630continuingintheTILEclassrooms• ThankyouforbeingthefirsttoparticipateinTILEversionofCS2630andnewlabassignments• workingon:potentiallyafutureopportunityforincludinglabassistants• helpstudentsbutdonotgradework• gainexperiencewithteaching• learnthematerialevenbetterbyteachingothers
