CS 152, Spring 2010 Section 2

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CS 152, Spring 2010 Section 2 Andrew Waterman University of California, Berkeley

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CS 152, Spring 2010 Section 2. Andrew Waterman. University of California, Berkeley. Agenda. Instructional account forms In-class activity Q&A on HW1, Lab 1. Instructional Account Forms. - PowerPoint PPT Presentation

Transcript of CS 152, Spring 2010 Section 2

Page 1: CS 152, Spring 2010 Section 2

CS 152, Spring 2010Section 2

Andrew Waterman

University of California, Berkeley

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Agenda

• Instructional account forms• In-class activity• Q&A on HW1, Lab 1

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Instructional Account Forms

• Once you have gotten your instructional account form, please fill out the sheet being passed around with the following info:– Full name– @berkeley.edu email address– Instructional login

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Assignment

• Short worksheet on Iron Law and variable-length instruction encoding

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Assignment Problem 1

• Option 1: Improve FPSQR–What is the overall CPI reduction?• (frequency of FPSQR)*(CPI reduction for FPSQR)• (0.02)*(20-2) = 0.36

• Option 2: Improve other FP ops–What is the overall CPI reduction?• (frequency of FP ops)*(CPI reduction for FP ops)• (0.25)*(4.0-2.5) = 0.375

• Option 2 reduces CPI further

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Assignment Problem 2A

• 90.5% of branches fit within 8 offset bits– (24-8 bits saved)*(0.905) = 14.48 bits saved

• 99.5% of branches fit within 16 offset bits– (24-16 bits saved)*(0.995-0.905) = 0.72 bits

saved

• This encoding saves 15.2 bits/branch (38%)

• Branches are 10% of program– Overall code size reduction is 3.8%

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Assignment Problem 2B

• We reduced branch length by 15.2 bits• Adding 2 bits reduces the benefit by

13%

• One alternative: use different opcodes to indicate length (if opcode space isn’t full)

• Another: Use offsets of length 6,14,22 instead of 8,16,24

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Assignment Problem 2C

• Most of the benefit was obtained by adding only a single new branch offset size (8 bits)

• Adding more branch types would meet diminishing returns

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Assignment Problem 2D

• Variable-length instructions add complexity– If looking at arbitrary code, hard to know

where instruction boundaries lie–Must decode instructions serially• Hard to implement processors that execute

more than one instruction per cycle

– Instructions can cross cache line/page boundaries

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Questions?

• HW• Lab• This in-class assignment