CS 152 Computer Architecture and Engineering Lecture 8 ...
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9/27/2016 CS152, Fall 2016 CS 152 Computer Architecture and Engineering Lecture 8 - Address Translation John Wawrzynek Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~johnw http://inst.eecs.berkeley.edu/~cs152
Transcript of CS 152 Computer Architecture and Engineering Lecture 8 ...
9/27/2016 CS152,Fall2016
CS152ComputerArchitectureandEngineering
Lecture 8- AddressTranslation
JohnWawrzynekElectricalEngineeringandComputerSciences
UniversityofCaliforniaatBerkeley
http://www.eecs.berkeley.edu/~johnwhttp://inst.eecs.berkeley.edu/~cs152
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CS152Administrivia
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§ Lab2dueFriday§ PS2dueTuesday§Quiz2nextThursday!
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LasttimeinLecture 7§ 3C’sofcachemisses
– Compulsory,Capacity,Conflict
§Writepolicies– Writeback,write-through,write-allocate, nowriteallocate
§Multi-levelcachehierarchies reducemisspenalty– 3levelscommoninmodernsystems(somehave4!)– Canchangedesigntradeoffs ofL1cacheifknowntohaveL2
§ Prefetching:retrievememorydatabeforeCPUrequest– Prefetching canwastebandwidthandcausecachepollution– Softwarevs hardwareprefetching
§ Softwarememoryhierarchyoptimizations– Loopinterchange, loopfusion,cachetiling
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BareMachine
§ Inabaremachine,theonlykindofaddressisaphysicaladdress
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PCInst.Cache D Decode E M
DataCache W+
MainMemory(DRAM)
MemoryController
PhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
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AbsoluteAddresses
§ Onlyoneprogramranatatime,withunrestrictedaccesstoentiremachine(RAM+I/Odevices)
§ Addresses inaprogramdependeduponwheretheprogramwastobeloadedinmemory
§ But itwasmoreconvenient forprogrammerstowritelocation-independent subroutines
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EDSAC,early50’s
Howcouldlocationindependencebeachieved?
Linkerand/orloadermodifyaddressesofsubroutinesandcallerswhenbuildingaprogrammemoryimage
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DynamicAddressTranslation§ Motivation
– Inearlymachines,I/OwasslowandeachI/OtransferinvolvedtheCPU(programmedI/O)
– Higherthroughputpossible ifCPUandI/Oof2ormoreprogramswereoverlapped,how?⇒multiprogrammingwithDMAI/Odevices,interrupts
§ Location-independent programs– Programmingandstoragemanagementease⇒ needforabase register
§ Protection– Independentprogramsshouldnotaffecteachotherinadvertently⇒ needforabound register
§ Multiprogrammingdrivesrequirement forresidentsupervisorsoftwaretomanagecontextswitchesbetweenmultipleprograms
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PhysicalM
emory
Program1
Program2
OS
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SimpleBaseandBoundTranslation
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LoadX
ProgramAddressSpace
BoundRegister
BoundsViolation?
PhysicalMemory
CurrentSegment
BaseRegister
+PhysicalAddressLogical
Address
Baseandboundsregistersarevisible/accessibleonlywhenprocessorisrunninginthesupervisormode
BasePhysicalAddress
SegmentLength
≥
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SeparateAreasforProgramandData
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PhysicalAddress
PhysicalAddress
LoadX
ProgramAddressSpace
MainMem
ory
DataSegment
DataBoundRegister
Mem.AddressRegister
DataBaseRegister +
BoundsViolation?
ProgramBoundRegister
ProgramCounter
ProgramBaseRegister +
ProgramSegment
LogicalAddress
LogicalAddress
Whatisanadvantageofthisseparation?
(SchemeusedonallCrayvectorsupercomputerspriortoX1,2002)
≥
≥ BoundsViolation?
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BaseandBoundMachine
Canfoldadditionofbaseregisterinto(register+immediate)addresscalculationusingacarry-saveadder(sumsthreenumberswithonlyafewgatedelaysmorethanaddingtwonumbers)
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PCInst.Cache D Decode E M
DataCache W+
MainMemory(DRAM)
MemoryController
PhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
DataBoundRegister
DataBaseRegister
+
LogicalAddress
BoundsViolation?
PhysicalAddress
ProgramBoundRegister
ProgramBaseRegister
+
LogicalAddress
BoundsViolation?≥ ≥
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MemoryFragmentation
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Asuserscomeandgo,thestorageis“fragmented”.Therefore, atsomestageprogramshavetobemovedaroundtocompactthestorage.
OSSpace
16K
24K
24K
32K
24K
user1
user2
user3
OSSpace
16K
24K
16K
32K
24K
user1
user2
user3
user5
user48K
Users4&5arrive
Users2&5leave
OSSpace
16K
24K
16K
32K
24K
user1
user48K
user3
free
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PagedMemorySystems§ Processor-generated address canbesplitinto:
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Pagetablesmakeitpossibletostorethepagesofaprogramnon-contiguously.
0123
0123
AddressSpaceofUser-1
PageTableofUser-1
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2
3
• APageTablecontainsthephysicaladdressatthestartofeachpage
PhysicalMemory
PageNumber Offset
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PrivateAddressSpaceperUser
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• Eachuserhasapagetable• Pagetablecontainsanentryforeachuserpage
VA1User1
PageTable
VA1User2
PageTable
VA1User3
PageTable
Physica
lMem
ory
free
OSpages
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WhereShouldPageTablesReside?
§ Spacerequiredbythepagetables(PT)isproportionaltotheaddressspace,numberofusers, ...
⇒ Too largetokeepinregisters
§ Idea:KeepPTs inthemainmemory– needsonereferencetoretrievethepagebaseaddressandanothertoaccessthedataword⇒ doublesthenumberofmemoryreferences!
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PageTablesinPhysicalMemory
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VA1
User1VirtualAddressSpace
User 2VirtualAddressSpace
PTUser1
PTUser2
VA1
Physica
lMem
ory
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AProblemintheEarlySixties
§Thereweremanyapplicationswhosedatacouldnotfitinthemainmemory,e.g.,payroll–Pagedmemorysystemreducedfragmentationbutstillrequiredthewholeprogramtoberesidentinthemainmemory
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DemandPaginginAtlas(1962)
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Secondary(Drum)
32x6pages
Primary32Pages
512words/page
CentralMemoryUsersees32x6x512words
ofstorage
“Apagefromsecondarystorageisbroughtintotheprimarystoragewhenever itis(implicitly)demandedbytheprocessor.”
TomKilburn
Primarymemoryasacacheforsecondarymemory
The Atlas Computer was a joint development between the University of Manchester, Ferranti, and Plessey.
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HardwareOrganizationofAtlas
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InitialAddressDecode
16ROMpages0.4-1µsec
2subsidiarypages1.4µsec
Main32pages1.4µsec
Drum(4)192pages 8Tapedecks
88sec/word
48-bitwords512-wordpages
1PageAddressRegister(PAR)per“pageframe”
Onmemoryaccesscomparetheeffective pageaddressagainstall32PARsmatch ⇒ normalaccessnomatch ⇒ pagefault
savethestateofthepartiallyexecutedinstruction
EffectiveAddress
systemcode(notswapped)
systemdata(notswapped)
0
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PARs
<effectivePN,status>
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AtlasDemandPagingScheme
Onapagefault:§ Transferfromdrumtoafreepageinprimarymemory isinitiated
§ ThePageAddressRegister(PAR)isupdated§ Ifnofreepageisleft,apageisselectedtobereplaced(basedonusage)
§ Thereplacedpageiswrittenonthedrum– tominimizedrumlatencyeffect,thefirstemptypageonthedrumwasselected
§ Thepagetableisupdatedtopointtothenewlocationofthepageonthedrum
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LinearPageTable
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§ PageTableEntry (PTE)contains:– Abittoindicate ifapageexists– PPN(physicalpagenumber)fora
memory-residentpage– DPN(diskpagenumber)forapage
onthedisk– Statusbitsforprotectionand
usage§ OSsetsthePageTableBase
Registerwheneveractiveuserprocesschanges
VPN OffsetVirtualaddressfromCPUExecuteStage
PTBaseRegister
VPN
Dataword
DataPages
Offset
PPNPPN
DPNPPN
PPNPPN
PageTable
DPN
PPN
DPNDPN
DPNPPN
SupervisorAccessibleControlRegister insideCPU
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SizeofLinearPageTable
§With32-bitaddresses,4-KBpages&4-bytePTEs:⇒ 232 /212 =220 virtualpagesperuser,assuming4-BytePTEs,⇒ 220 PTEs,i.e,4MBpagetableperuser!– 4GBofswapneededtobackupfullvirtualaddress
space
§ Largerpageshelps,but:– Internalfragmentation (Notallmemoryinpageisused)– Largerpagefaultpenalty(moretimetoreadfromdisk)
§Whatabout64-bitvirtualaddressspace???– Even1MBpageswouldrequire2448-bytePTEs(35TB!)
Whatisthe“savinggrace”?
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HierarchicalPageTable
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Level1PageTable
Level2PageTables
DataPages
pageinprimarymemorypageinsecondarymemory
RootoftheCurrentPageTable
p1
offset
p2
VirtualAddress fromCPU
(ProcessorRegister)
PTEofanonexistentpage
p1 p2offset01112212231
10-bitL1index
10-bitL2index
Physica
lMem
ory
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AddressTranslation&Protection
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• Every instructionanddataaccessneedsaddresstranslationandprotectionchecks
AgoodVMdesignneedstobefast(~onecycle)andspaceefficient
PhysicalAddress
VirtualAddress
AddressTranslation
VirtualPageNo.(VPN) offset
PhysicalPageNo.(PPN) offsetException?
Kernel/UserMode
Read/Write ProtectionCheck
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TranslationLookaside Buffers(TLB)
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Addresstranslationisveryexpensive!Inatwo-levelpagetable,eachreferencebecomesseveralmemoryaccesses
Solution:CachetranslationsinTLBTLBhit ⇒ Single-CycleTranslationTLBmiss ⇒ Page-TableWalktorefill
VPN offset
V RWD tag PPN
physicaladdress PPN offset
virtualaddress
hit?
(VPN=virtualpagenumber)
(PPN=physicalpagenumber)
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TLBDesigns§ Typically32-128entries,usuallyfullyassociative
– Eachentrymapsalargepage,hence lessspatial localityacrosspagesèmorelikelythattwoentriesconflict
– Sometimes largerTLBs (256-512entries)are4-8wayset-associative– Largersystemssometimes havemulti-level (L1andL2)TLBs
§ RandomorFIFOreplacementpolicy
§ NoprocessinformationinTLB?§ TLBReach:SizeoflargestvirtualaddressspacethatcanbesimultaneouslymappedbyTLB
Example:64TLBentries,4KBpages,onepageperentry
TLBReach=_____________________________________________?
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64entries*4KB=256KB(ifcontiguous)
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HandlingaTLBMiss
§Software(MIPS,DEC/Alpha)– TLBmisscausesanexceptionandtheoperatingsystemwalksthepagetablesandreloadsTLB.Aprivileged“untranslated” addressingmodeusedforwalk.
§Hardware(SPARCv8,x86,PowerPC,RISC-V)– Amemorymanagementunit(MMU)walksthepagetablesandreloadstheTLB.
– Ifamissing(dataorPT)pageisencountered duringtheTLBreloading,MMUgivesupandsignalsaPageFaultexceptionfortheoriginalinstruction.
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HierarchicalPageTableWalk:SPARCv8
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31 110
VirtualAddress Index1 Index2 Index3 Offset31 2317110
ContextTableRegister
ContextRegister
rootptr
PTPPTP
PTE
ContextTable
L1Table
L2TableL3Table
PhysicalAddress PPN Offset
MMUdoesthistablewalkinhardwareonaTLBmiss
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Page-BasedVirtual-MemoryMachine(HardwarePage-TableWalk)
§ Assumespagetablesheldinuntranslated physicalmemory
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PCInst.TLB
Inst.Cache D Decode E M
DataCache W+
PageFault?
Protectionviolation?PageFault?
Protectionviolation?
DataTLB
MainMemory(DRAM)
MemoryControllerPhysicalAddress
PhysicalAddress
PhysicalAddress
PhysicalAddress
Page-TableBaseRegister
VirtualAddress Physical
Address
VirtualAddress
HardwarePageTableWalker
Miss? Miss?
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AddressTranslation:puttingitalltogether
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VirtualAddress
TLBLookup
PageTableWalk
UpdateTLBPageFault(OSloadspage)
ProtectionCheck
PhysicalAddress(tocache)
miss hit
the pageis∉ memory ∈ memory denied permitted
ProtectionFault
hardwarehardwareorsoftwaresoftware
SEGFAULTWhere?
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Acknowledgements
§ Theseslidescontainmaterialdeveloped andcopyrightby:– Arvind(MIT)– KrsteAsanovic(MIT/UCB)– JoelEmer(Intel/MIT)– JamesHoe(CMU)– JohnKubiatowicz(UCB)– DavidPatterson(UCB)
§ MITmaterialderivedfromcourse6.823§ UCBmaterialderivedfromcourseCS252
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