CS 121 Digital Logic Design

31
CS 121 Digital Logic Design Gate-Level Minimization Chapter 3

description

Chapter 3. CS 121 Digital Logic Design. Gate-Level Minimization. Outline. 3.1 Introduction 3.2 The Map Method 3.3 Four-Variable Map 3 .4 Product of sums simplification 3.5 Don‘t Care Conditions 3.7 NAND and NOR Implementaion 3.8 Other Two-Level Implementaion 3.9 Exclusive-OR function. - PowerPoint PPT Presentation

Transcript of CS 121 Digital Logic Design

Page 1: CS 121 Digital Logic Design

CS 121Digital Logic

Design

Gate-Level Minimization

Chapter 3

Page 2: CS 121 Digital Logic Design

Outline3.1 Introduction3.2 The Map Method3.3 Four-Variable Map3.4 Product of sums simplification3.5 Don‘t Care Conditions3.7 NAND and NOR Implementaion3.8 Other Two-Level Implementaion3.9 Exclusive-OR function

Page 3: CS 121 Digital Logic Design

3.1 Introduction (1-1)

Gate-Level Minimization refers to the design task of finding an optimal gate-level implementation of the Boolean functions describing a digital circuit.

Notes about simplification of Boolean expression: Minimum number of terms and literals in each term

(minimum number of gates and inputs in the digram). Reduce the complexity of the digital gates. The simplest expression is not unique.

Simplification Methods: Algebraic minimization lack on specific rules. (section

2.4). Karnaugh map or K-map.

Page 4: CS 121 Digital Logic Design

A Karnaugh map is a graphical tool for assisting in the general simplification procedure.

Combination of 2, 4, … adjacent squares

The relation is:Logic circuit ↔ Boolean function ↔ Truth table ↔ K-map ↔ conical form ↔ satndrad form.

Conical form: ( sum of minterms , product of maxterms.

Standrad form: ( simplifier : sum of product , product of sum

3.2 The Map Method (1-12)

Page 5: CS 121 Digital Logic Design

Number of sequares (minterms) is , where n is the number of variables.

So in tow-variable map there are 4 squares(minterms).

3.2 The Map Method (2-12)Two-variable

maps:

Y’ Y

X

X’

Page 6: CS 121 Digital Logic Design

3.2 The Map Method (3-12)

Rules for K-map:o We can reduce functions by circling 1’s in the K-mapo Each circle represents a minterm reductiono Following circling, we can deduce minimized and-or

form. Rules to considero Every cell containing a 1 must be included at least

once.o The largest possible “power of 2 rectangle” must be

enclosed.o The 1’s must be enclosed in the smallest possible

number of rectangles.

Page 7: CS 121 Digital Logic Design

Example 1:F(X,Y) = XY’ + XY

Two-Variable maps (cont.)

3.2 The Map Method (4-12)

From the map, we see thatF (X,Y) = X.Note: There are implied 0s in other boxes.

This can be justified using algebraic manipulations:F(X,Y) = XY’ + XY

= X(Y’ +Y) = X.1

= X

11 X

Page 8: CS 121 Digital Logic Design

Example 2:G(x,y) = m1 + m2 + m3

Two-Variable maps (cont.)

3.2 The Map Method (5-12)

G(x,y) = m1 + m2 + m3

= X’Y + XY’ + XY

From the map, we can see that :

G = X + Y

1

11 X

Y

Page 9: CS 121 Digital Logic Design

Example 3:F = Σ(0, 1)

Two-Variable maps (cont.)

3.2 The Map Method (6-12)

Using algebraic manipulations:

F = Σ(0,1) = x’y + x’y’ = x’ (y+y’) = x’

11 X’

x y F0 0 10 1 11 0 01 1 0

Page 10: CS 121 Digital Logic Design

3 variables 8 squares ( minterms). On a 3-variable K-Map:

◦ One square represents a minterm with three variables◦ Two adjacent squares represent a product term with two variables◦ Four “adjacent” terms represent a product term with one variables◦ Eight “adjacent” terms is the function of all ones (logic 1).

3.2 The Map Method (7-12)Three-variable

maps:

Page 11: CS 121 Digital Logic Design

using algebraic manipulations: F = X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’ = Z’ (X’Y’ + X’Y + XY’ + XY)

= Z’ (X’ (Y’+Y) + X (Y’+Y)) = Z’ (X’+ X)

= Z’

3.2 The Map Method (8-12)Three-variable maps

(cont.):Example 1:F(X,Y) = X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’

Y Z

x 1

1

1

1

Page 12: CS 121 Digital Logic Design

Example 2:F=AB’C’ +ABC +ABC +ABC + A’B’C + A’BC’

three-Variable maps (cont.)

3.2 The Map Method (9-12)

From the map, we see thatF=A+BC +BC

B CA

1

1

1

11 1

00 01 11 1001

Page 13: CS 121 Digital Logic Design

Example 4 :F (x, y, z)= Σm (2, 3, 6, 7)

three-Variable maps (cont.)

3.2 The Map Method (10-12)

using algebraic manipulations:

F(x , y, z) = x’yz + xyz + x’yz’ + xyz’

= yz (x’ + x) + yz’ (x’ + x)

= yz + yz’ = y (z + z’) = y

y zx

1 1

11

00 01 11 1001

Y

Page 14: CS 121 Digital Logic Design

Example (3-1) , (3-2) :

three-Variable maps (cont.)

3.2 The Map Method (11-12)

Page 15: CS 121 Digital Logic Design

Example (3-3) , (3-4) :

three-Variable maps (cont.)

3.2 The Map Method (12-12)

Page 16: CS 121 Digital Logic Design

3.3 Four-Variables Map (1-9)

4 variables 16 squares ( minterms). On a 4-variable K-Map: Two adjacent squares represent a term of three literals. Four adjacent squares represent a term of two literals. Eight adjacent squares represent a term of one literal. Note: The larger the number of squares combined, the

smaller the number of literals in the term.

Page 17: CS 121 Digital Logic Design

3.3 Four-Variables Map (2-9)

Flat Map Vs. Torus

Page 18: CS 121 Digital Logic Design

3.3 Four-Variables Map (3-9)

Example 1 (3-5) :F(w,x,y,z) = ∑ ( 0,1,2,4,5,6,8,9,12,13,14)

y z

w x 1

00 01 11 1000011110

1

1 1

1 1

1 1

1

1

1Y’

W’YZ’

XYZ’

F = y‘ + w‘yz‘ + xyz‘

Page 19: CS 121 Digital Logic Design

3.3 Four-Variables Map (4-9)

Example 2 (3-6) :F = A’B’C’ + B’CD’ + A’BCD’ + AB’C’

C D

A B1

00 01 11 101

F = B‘D‘ + B‘C‘ + A‘CD‘

00011110

1

1

11 1 B’D’

B’C’

A’CD’

Page 20: CS 121 Digital Logic Design

3.3 Four-Variables Map (5-9)

Simplification using Prime Implicantso A Prime Implicant is a product term obtained by

combining the maximum possible number of adjacent squares in the map .

o If a minterm in a square is covered by only one prime implicant, that implicant is called Essential .

o Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map.

o Notes:• Two adjacent 1’s form prime implicant, if they are not within a

group of four adjacent squares.• Four adjacent 1’s form prime implicant, if they are not within

a group of eight adjacent squares and so on.

Page 21: CS 121 Digital Logic Design

3.3 Four-Variables Map (6-9)Simplification using Prime ImplicantsExample 1:F(A,B,C,D) = ∑ (0,2,3,5,7,8,9,10,11,13,15)

Minterms covered by single prime implicant

DB

CB

1 1

1 1

1 1

B

D

A

1 11 1

1

ESSENTIAL Prime Implicants

C

BD

CD

BD

DB

1 1

1 1

1 1

B

C

D

A

1 1

1 1

1

AD

BA

Page 22: CS 121 Digital Logic Design

3.3 Four-Variables Map (7-9)Simplification using Prime ImplicantsExample 1:F(A,B,C,D) = ∑ (0,2,3,5,7,8,9,10,11,13,15)

o Essential prim implicants:BD , B’D’o Prime implicant: CD , B’C, AD , AB’.o The minterms that not cover by essential implicants are: m3, m9,

m11.The simplified expression is optained from the sum of the

essential implicants and other prime implicants that may be needed to cover any remaining minterms.

o So this function can be written with these ways:• F = BD + B’D’ + CD + AD• F = BD + B’D’ + CD + AB’• F = BD + B’D’ + B’C + AD• F = BD + B’D’ + B’C + AB’

Page 23: CS 121 Digital Logic Design

3.3 Four-Variables Map (8-9)Simplification using Prime ImplicantsExample 2:F(W,X,Y,Z) = ∑ (0,2,3,8,9,10,11,12,13,14,15)

X

Y

Z

W

1 1 1

1 1 1 1

1 1 11

W

X’Y

X’Z’ Note: that all

of these prime implicants are

essential .

Page 24: CS 121 Digital Logic Design

3.3 Four-Variables Map (9-9)Simplification using Prime ImplicantsExample 3:F(W,X,Y,Z) = ∑ (0,2,3,4,7,12,13,14,15)

X

Y

Z

W

1 1 1

1 1

1 1 1 1

WX

W’Y’Z’

W’X’Y

W’YZ

XYZXY’Z

• Essential: WX• Prime: XYZ ,

XY’Z’ , W’Y’Z’, W’YZ, W’X’Y , W’X’Z’

W’X’Z’

Page 25: CS 121 Digital Logic Design

3.5 Producut-of-Sum simplification (1-9)

1. Mark with 1’s the minterms of F.2. Mark with 0’s the minterms of F’.

3. Circle 0’s to express F’.4. Complement the result in step 3 to

obtain a simplified F in product-of-sums form.

Page 26: CS 121 Digital Logic Design

3.5 Producut-of-Sum simplification (1-9)Example 1:Simplify :F= ∑(0,1,2,5,8,9,10) in Product-of-Sums Form

B

C

D

A

1 1 1

1

1 1 1

0

0 0 0

0 0 0 0

0

CD

ABBD’

• F’ = AB + CD + BD’• F = (F’)’ = (A’+B’) + (C’+D’) +

(B’+D)

Page 27: CS 121 Digital Logic Design

3.5 Producut-of-Sum simplification (1-9)

Example 2:Simplify :F(x, y, z) =(0, 2, 5,7)in Product-of-Sums Form

y zx

0

00 01 11 1001 0

0 0

XZ

X’Z’

• F’ = XZ + X’Z’• F = (F’)’ = (X’+Z’) +

(X+Z)

Page 28: CS 121 Digital Logic Design

3.6 Don't Cares Condition (1-4)

Sometimes a function table or map contains entries for which it is known:

The input values for the minterm will never occur, or The output value for the minterm is not used. Functions that have unspecified outputs for some input combinations are

called incompletely specified functions. In these cases, the output value is defined as a “don't care” ( an “x”

entry) assumed to be either 0 or 1. The choice between 0 and 1 is depending on the way the incompletely

specified function is simplied. By placing “don't cares” in the function table or map, the cost of the logic

circuit may be lowered.

Page 29: CS 121 Digital Logic Design

3.6 Don't Cares Condition (2-4)

Example : A logic function having the binary codes

for the BCD digits as its inputs. Only the codes for 0 through 9 are used.

The six codes, 1010 through 1111 never occur, so the output values for these codes are “x” to represent “don’t cares.”

Page 30: CS 121 Digital Logic Design

3.6 Don't Cares Condition (3-4)

Example (3.9) :F(W,X,Y,Z) = ∑ (1,3,7,11,15)d(W,X,Y,Z) = ∑ (0,2,5)

X

Y

Z

W

1 1 xx

1

0

x

1

1

0

0

0 0

0

0

0

F = YZ + W’Z

X

Y

Z

W

1 1 xx

1

0

x

1

1

0

0

0 0

0

0

0

F = YZ + W’X’

Page 31: CS 121 Digital Logic Design

3.6 Don't Cares Condition (4-4)

Example (3.9) :F(W,X,Y,Z) = ∑ (1,3,7,11,15)d(W,X,Y,Z) = ∑ (0,2,5)

X

Y

Z

W

1 1 xx

1

0

x

1

1

0

0

0 0

0

0

0

F’ = Z’ + WY’F = Z ( W’ + Y)