Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression

© PSU Crosstalk-Aware Energy Efficient Encoding for

Instruction Bus through Code Compression

Balaji Vaidyanathan, Yuan XieDepartment of CSE

Pennsylvania State University, University ParkPA-16801

© PSU Index Terms

Energy reductionCode-compression hardwarecrosstalk

© PSU Introduction and Motivation

Power aware embedded system design is necessary.

[1] Lahiri et al., CODES-ISSS’04[2] Sotirsadis et al., ICCAD’04

Magen et al., Intel Corporation, SLIP’04

Interconnect power is a major power consumer. Comparable to cache, memory controller, core

power [1].

Interconnect dynamic power due to toggling (↓) with technology scaling crosstalk (↑) with technology scaling [2]


GND

A BS

T H

W

CA_to_B

L

CB_to_GND

L.TαL.W

Inter-wire or crosstalk capacitance

SelfCapacitance


GND

A B

S

H

W

2T

L

CA_to_B

CB_to_GND

2.(L.T)α

L.W


CA_to_B

CB_to_GND

λ . (L.T)α

L.W

1.742 in 250nm9.82 in 70nm

Inter-wire coupling capacitance will dominate total interconnect capacitance in future technologies.


Code compression reduces code size and power. But increases entropy.

Is there a compression scheme that can be utilized to reduce interconnect power ? Variable-to-Fixed (V2F) compression scheme

(explained later) Tunstall introduced V2F coding

Xie et al. used it to reduce code size and interconnect toggle power (not crosstalk induced power).

© PSU Background

Xie et al., ISSS-CODES ‘02.

0.8

0.7

0.10.9

0.3

0.2

0.4 0.6

W i d t h

4

0

12

8

5

1

13

9

6

2

14

10

7

3

15

11

D e

p t h

0 2 0 2 1 3 1 3

4

0

12

8

5

1

13

9

6

2

14

10

7

3

15

11

D e

p t h

0 2 0 2 1 3 1 3

[C1,W1]

[C4,W4]

[C2,W2]

[C5,W5]

[C3,W3]

[C6,W6]

2 bit

Input Bits

Codeword

Next State

1 00 601 01 10001 10 14000 11 12

[C0,W0]

0.1

4

0

12

8

6

14

10

0.8

0.7

0.9

0.3

0.2

Markov V2F code compression

© PSU Background

Xie et al., ISSS-CODES ‘02.

[C1,W1]

[C4,W4]

[C2,W2]

[C5,W5]

[C3,W3]

[C6,W6]

N bit


0 1 0 1 1 1 0 1 0 0 0 0

1 0 0 0 0 0 0 1 1 1 1 0

Variable length bit

stream

to

Fixed length Codes

© PSU Background

We can assign random codes why not do a power aware assignment ?

Each code book is re-coded with power aware codes Based on application profiling (algorithm

explained later)Note

no change in compression algorithm or its efficiency.

Only code-bit mapping changes No h/w change required (for both compression

and de-compression)


© PSU Background

Pdyn = 0.5 * Ctotal * Vdd2 * f

Sotiriadis et al., IEEE CICC, 2000.

Nt = Ns + λ* Nc1.742 in 250nm9.82 in 70nm

Ctotal = Cs * Nt Wire-to-substrate/Self capacitance

Self transition / Hamming distance

Coupling Transition

Crosstalk and Power Models

© PSU Background

Pdyn = Constant * Ctotal

Ctotal = Self Capacitance * (Toggles + λ* Crosstalk_Transitions)

= Self Capacitance * (Ns + λ* Nc )

Crosstalk and Power Models

© PSU Background

Code Word

Total Transition (Nt)

0000 0 + 0 λ0001 1 + 1 λ1000 1 + 1 λ1111 4 + 0 λ0011 2 + 1 λ1100 2 + 1 λ0111 3 + 1 λ1110 3 + 1 λ0010 1 + 2 λ0100 1 + 2 λ0110 2 + 2 λ1001 2 + 2 λ1011 3 + 2 λ1101 3 + 2 λ0101 2 + 3 λ1010 2 + 3 λ

Head = (0000)Nt = Ns + λ* Nc

λ = 3

= 4

= 11

Total Transition Table

© PSU Energy-aware code assignment

Source Code

Compilation Profiling

Energy-awareCompression

Decompression Hardware Object Code

Implementation flow

© PSU Energy-aware code assignment

• The instructions in the application are assigned dummy codeword.

[C3,W3]

AA2A1

[C2,W2]

[C1,W1] E6 E7

• Vertical and horizontal adjacency of codeword is collected from the application profile.

[C1,W1]

[C4,W4]

[C2,W2]

[C5,W5]

[C3,W3]

[C6,W6]

N bit

• The codeword to be assigned are picked in pairs that are most vertically connected.

• The Codeword pairs are assigned cross-talk aware binary bits.

• Horizontal adjacency is used to take care of boundary conditions

A

B

[C2,W2]

[C5,W5]

E1

A C

S1

S2

B D

1 0 1 0 1 0 0 0

0 0 0 1 0 1 0 0

© PSU Experimental Setup

Cycle accurate TMS320C6x (Texas Instruments DSP VLIW processor) simulator.

Media benchmarks are compiled using Code Composer Studio IDE.

BPTM model for bus is used.4-bit length codewords are used.

© PSU Experimental Results

~250nm 70nm

0102030405060708090

100

2 3 4 5 6 7 8 9 10L a m b d a (λ)

ADPCM FIR MAC MODEM VERTIBI

75-95% of Interconnect dynamic power is inter-wire coupling transition

% c

ontri

butio

n of

inte

r-wire

in

unc

ompr

esse

d ap

proa

ch


Toggle Power ~250nm ~70nm

% p

ower

redu

ctio

n co

mpa

red

to

unco

mpr

esse

d ap

proa

ch

0

10

20

30

40

50

60

70

80

L a m b d a (λ)


2 3 4 5 6 7 8 9 10

42-68% inter-wire coupling power reduction55-71% total dynamic power reduction

using 32x32 Markov model


~250nm ~70nm

0

50

100

150

200

250

L a m b d a (λ)



2 3 4 5 6 7 8 9 10

225% power increase due to random codeword assignment compared to optimized case

% p

ower

of r

ando

m-c

ase

com

pare

d to

op

timize

d ap

proa

ch


~250nm ~70nm

% p

ower

of w

orst

-cas

e co

mpa

red

to

optim

ized

appr

oach

0

100

200

300

400

500

600

700

800

L a m b d a (λ)


2 3 4 5 6 7 8 9 10

570-670% power increase due to worst-case codeword assignment compared to optimized case

© PSU ConclusionCode compression hardware

considering inter-wire coupling transition is proposed.

No extra delay, power or area overhead incurred.

55-71% reduction in interconnect dynamic power is obtained.

2X power reduction compared to random-case.

Crosstalk-Aware Energy Efficient Encoding for Instruction Bus through Code Compression

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