INDEX

1. Abbreviations

2. Figures locations

3. Introduction

4. Block Diagram

4.1Block Diagram Descriptions

5. Schematic

5.1Schematic Description

6. Hardware Components

6.1 Power supply

6.2 Microcontroller

6.3 LCD (Liquid Cristal Display)

6.4 Keypad

6.5 MAX232

6.6 GSM

6.7 RFID Reader

6.8 Latch

6.9 EEPROM

6.10 Bank locker

7. Software components

7.1 Embedded ‘C’

7.2 About Kiel

8. Source code

9. Conclusion

10. Future Aspects

11. Bibliography

1. ABBREVIATIONS

Symbol Name

ACC Accumulator

B B register

PSW Program status word

SP Stack pointer

DPTR Data pointer 2 bytes

DPL Low byte

DPH High byte

P0 Port0

P1 Port1

P2 Port2

P3 Port3

IP Interrupt priority control

IE Interrupt enable control

TMOD Timer/counter mode control

TCON Timer/counter control

T2CON Timer/counter 2 control

T2MOD Timer/counter mode2 control

TH0 Timer/counter 0high byte

TL0 Timer/counter 0 low byte

TH1 Timer/counter 1 high byte

TL1 Timer/counter 1 low byte

TH2 Timer/counter 2 high byte

TL2 Timer/counter 2 low byte

SCON Serial control

SBUF Serial data buffer

RFID Radio Frequency Identification

MAX MAXIM (IC manufacturer )

TTL Transistor to Transistor Logic

ATM Automatic Teller Machine

RS 232 Recommended Standard

AC Alternating Current

DC Direct Current

LCD Liquid Crystal Display

PC Personal Computer

RPS Regulated Power Supply

RMS Root Mean Square

2. FIGURE LOCATIONS

S.No. Figure Page No.

1 Block Diagram of RF(Tx,Rx)

2 Schematic Diagram

3 Power Supply

4 Bridge Rectifier (Tx,Rx)

5 Wave forms of Rectifier

6 Smoothing Capacitors

7 Internal Block Diagram of power supply

8 Architecture of 8052

9 Oscillator connections

10 TCON Register

11 TMOD Register

12 Schematic diagram of lcd

13

16*2 alphanumeric lcd module

specifications

14 Address locations for a 1*16 line lcd

15 Block diagram of lcd

16 Power supply of lcd

17 Pin diagram of 1*16 lines lcd

18 Pin specifications

19 Character details in lcd

20 Flow chart of lcd

21 Smoke detector

22 Structure of an H-bridge

23 DC motor

24 RF transmitter

25 RF receiver

26 4*4 keypad

27 Buzzer

INTRUDUCTION

This project is mainly aimed to implement the credit card security system with SMS

confirmation to provide a secured banking system. The purpose of the project is to provide a

secured and reliable environment to the customers for their banking transactions by providing a

unique identity to every user using the RFID technology and GSM for security purpose.

Here in this project we are going to provide the at most security since it is taking the RFID as the

first authentication and activates the GSM modem for the confirmation. If user of credit card is

valid person, then the user will get confirmation message from the modem. If user is not a valid

person there will be no confirmation, thus the user of credit card can’t perform any transactions.

Whenever user inserts RFID into the reader, it will read the information and fetches to the

controller. As soon as controller gets the information from the card reader it will activates the

GSM modem for confirmation. GSM modem replies to the controller by sending a SMS through

network paths using AT commands. After getting confirmation from the modem user will

perform transactions.

Radio Frequency Identification (RFID) is a silicon chip-based transponder that

communicates via radio waves. Radio Frequency Identification is a technology which

uses tags as a component in an integrated supply chain solution set that will evolve over

the next several years. RFID tags contain a chip which holds an electronic product code

(EPC) number that points to additional data detailing the contents of the package.

Readers identify the EPC numbers at a distance, without line-of-sight scanning or

involving physical contact. Middleware can perform initial filtering on data from the

readers. Applications are evolving to comply with shipping products to automatically

processing transactions based on RFID technology.

GSM (Global System for Mobile communications) is the technology that underpins most of the

world's mobile phone networks. The GSM platform is a hugely successful wireless technology

and an unprecedented story of global achievement and cooperation. GSM has become the world's

fastest growing communications technology of all time and the leading global mobile standard,

spanning 218 countries. GSM is an open, digital cellular technology used for transmitting mobile

voice and data services. GSM operates in the 900MHz and 1.8GHz bands GSM supports data

transfer speeds of up to 9.6 kbps, allowing the transmission of basic data services such as SMS.

Micro controller

LCD Display

Power supply

RFID cardReader M

AX232

Key pad

EEPROM

BANK LOCKER

GSM

LATCH

BLOCK DIAGRAM:

POWER SUPPLY:

Step DownTransformer

BridgeRectifier

FilterCircuit

Regulator section

4.1 BLOCK DIAGRAM EXPLANATION

MICROCONTROLLER:

The microcontroller is the heart of the proposed embedded system. The controller used is

a low power, cost efficient chip manufactured by ATMEL having 8K bytes of on-chip flash

memory. Microcontroller will receive this information and display on LCD.

POWER SUPPLY:

A device or system that supplies electrical or other types of energy to an output load or

group of loads is called a power supply unit or PSU. The term is most commonly applied to

electrical energy supplies, less often to mechanical ones, and rarely to others. Here we giving 5v

to the micro controller.

KEYPAD&LCD:

Keyboards and LCDs are the most widely used input/output devices of the

microcontroller, and a basic understanding of them is essential

RFID CARDREADER:

An RFID reader is a device that is used to interrogate an RFID tag. The reader has an

antenna that emits radio waves; the tag responds by sending back its data.

GLOBAL SYSTEM FOR MOBILE COMMUNICATION (GSM):

It is a wireless communication GSM modem replies to the controller by sending a SMS

through network paths using AT commands.

EEPROM: It is used to storage (permanent) purpose.

MAX232:

The MAX232 is an integrated circuit that converts signals from an RS-232 serial port to signals suitable for use in TTL compatible digital logic circuits.

HARDWARE COMPONENTS

6.1POWER SUPPLY:

Power supply is a reference to a source of electrical power. A device or system that supplies

electrical or other types of energy to an output load or group of loads is called a power supply unit or

PSU. The term is most commonly applied to electrical energy supplies, less often to mechanical ones,

and rarely to others.

This power supply section is required to convert AC signal to DC signal and also to reduce

the amplitude of the signal. The available voltage signal from the mains is 230V/50Hz which is an AC

voltage, but the required is DC voltage (no frequency) with the amplitude of +5V and +12V for various

applications.

In this section we have Transformer, Bridge rectifier, are connected serially and voltage

regulators for +5V and +12V (7805 and 7812) via a capacitor (1000µF) in parallel are connected

parallel as shown in the circuit diagram below. Each voltage regulator output is again is connected to

the capacitors of values (100µF, 10µF, 1 µF, 0.1 µF) are connected parallel through which the

corresponding output (+5V or +12V) are taken into consideration.

Fig3: power supply diagram

Circuit Explanation

A) Transformer

A transformer is a device that transfers electrical energy from one circuit to another through

inductively coupled electrical conductors. A changing current in the first circuit (the primary)

creates a changing magnetic field; in turn, this magnetic field induces a changing voltage in the

second circuit (the secondary). By adding a load to the secondary circuit, one can make current

flow in the transformer, thus transferring energy from one circuit to the other.

The secondary induced voltage VS, of an ideal transformer, is scaled from the primary VP by a

factor equal to the ratio of the number of turns of wire in their respective windings:

Basic principle

The transformer is based on two principles: firstly, that an electric current can produce a

magnetic field (electromagnetism) and secondly that a changing magnetic field within a coil of

wire induces a voltage across the ends of the coil (electromagnetic induction). By changing the

current in the primary coil, it changes the strength of its magnetic field; since the changing

magnetic field extends into the secondary coil, a voltage is induced across the secondary.

A simplified transformer design is shown below. A current passing through the primary

coil creates a magnetic field. The primary and secondary coils are wrapped around a core of very

high magnetic permeability, such as iron; this ensures that most of the magnetic field lines

produced by the primary current are within the iron and pass through the secondary coil as well

as the primary coil.

An ideal step-down transformer showing magnetic flux in the core.

Induction law

The voltage induced across the secondary coil may be calculated from Faraday's law of

induction, which states that:

Where VS is the instantaneous voltage, NS is the number of turns in the secondary coil and Φ

equals the magnetic flux through one turn of the coil. If the turns of the coil are oriented

perpendicular to the magnetic field lines, the flux is the product of the magnetic field strength B

and the area A through which it cuts. The area is constant, being equal to the cross-sectional area

of the transformer core, whereas the magnetic field varies with time according to the excitation

of the primary. Since the same magnetic flux passes through both the primary and secondary

coils in an ideal transformer, the instantaneous voltage across the primary winding equals

Taking the ratio of the two equations for VS and VP gives the basic equation for stepping up or

stepping down the voltage

Ideal power equation

If the secondary coil is attached to a load that allows current to flow, electrical power is

transmitted from the primary circuit to the secondary circuit. Ideally, the transformer is perfectly

efficient; all the incoming energy is transformed from the primary circuit to the magnetic field

and into the secondary circuit. If this condition is met, the incoming electric power must equal

the outgoing power.

Pin coming = IPVP = Pout going = ISVS

Giving the ideal transformer equation

Pin-coming = IPVP = Pout-going = ISVS

giving the ideal transformer equation

If the voltage is increased (stepped up) (VS > VP), then the current is decreased (stepped

down) (IS < IP) by the same factor. Transformers are efficient so this formula is a reasonable

approximation.

If the voltage is increased (stepped up) (VS > VP), then the current is decreased (stepped down)

(IS < IP) by the same factor. Transformers are efficient so this formula is a reasonable

approximation.

The impedance in one circuit is transformed by the square of the turns ratio. For example,

if an impedance ZS is attached across the terminals of the secondary coil, it appears to the

primary circuit to have an impedance of

This relationship is reciprocal, so that the impedance ZP of the primary circuit appears to the

secondary to be

Detailed operation

The simplified description above neglects several practical factors, in particular the primary

current required to establish a magnetic field in the core, and the contribution to the field due to

current in the secondary circuit.

Models of an ideal transformer typically assume a core of negligible reluctance with two

windings of zero resistance. When a voltage is applied to the primary winding, a small current

flows, driving flux around the magnetic circuit of the core. The current required to create the flux

is termed the magnetizing current; since the ideal core has been assumed to have near-zero

reluctance, the magnetizing current is negligible, although still required to create the magnetic

field.

The changing magnetic field induces an electromotive force (EMF) across each

winding. Since the ideal windings have no impedance, they have no associated voltage drop, and

so the voltages VP and VS measured at the terminals of the transformer, are equal to the

corresponding EMFs. The primary EMF, acting as it does in opposition to the primary voltage, is

sometimes termed the "back EMF". This is due to Lenz's law which states that the induction of

EMF would always be such that it will oppose development of any such change in magnetic

field.

b) Bridge Rectifier

A diode bridge or bridge rectifier is an arrangement of four diodes in a bridge

configuration that provides the same polarity of output voltage for any polarity of input voltage.

When used in its most common application, for conversion of alternating current (AC) input into

direct current (DC) output, it is known as a bridge rectifier. A bridge rectifier provides full-wave

rectification from a two-wire AC input, resulting in lower cost and weight as compared to a

center-tapped transformer design, but has two diode drops rather than one, thus exhibiting

reduced efficiency over a center-tapped design for the same output voltage.

Basic Operation

When the input connected at the left corner of the diamond is positive with respect to the one

connected at the right hand corner, current flows to the right along the upper colored path to the

output, and returns to the input supply via the lower one.

Fig4.1 bridge rectifier

When the right hand corner is positive relative to the left hand corner, current flows along the

upper colored path and returns to the supply via the lower colored path.

Fig 4.2 bridge rectifier

In each case, the upper right output remains positive with respect to the lower right one.

Since this is true whether the input is AC or DC, this circuit not only produces DC power when

supplied with AC power: it also can provide what is sometimes called "reverse polarity

protection". That is, it permits normal functioning when batteries are installed backwards or DC

input-power supply wiring "has its wires crossed" (and protects the circuitry it powers against

damage that might occur without this circuit in place).

Prior to availability of integrated electronics, such a bridge rectifier was always

constructed from discrete components. Since about 1950, a single four-terminal component

containing the four diodes connected in the bridge configuration became a standard commercial

component and is now available with various voltage and current ratings.

Fig 5: wave forms of rectifier

c) Output smoothing (Using Capacitor)

For many applications, especially with single phase AC where the full-wave bridge serves to

convert an AC input into a DC output, the addition of a capacitor may be important because the

bridge alone supplies an output voltage of fixed polarity but pulsating magnitude (see diagram

above).

Fig 6: smoothing capacitor

The function of this capacitor, known as a reservoir capacitor (aka smoothing

capacitor) is to lessen the variation in (or 'smooth') the rectified AC output voltage waveform

from the bridge. One explanation of 'smoothing' is that the capacitor provides a low impedance

path to the AC component of the output, reducing the AC voltage across, and AC current

through, the resistive load. In less technical terms, any drop in the output voltage and current of

the bridge tends to be cancelled by loss of charge in the capacitor.

This charge flows out as additional current through the load. Thus the change of load current and

voltage is reduced relative to what would occur without the capacitor. Increases of voltage

correspondingly store excess charge in the capacitor, thus moderating the change in output

voltage / current. Also see rectifier output smoothing.

The simplified circuit shown has a well deserved reputation for being dangerous, because, in

some applications, the capacitor can retain a lethal charge after the AC power source is

removed. If supplying a dangerous voltage, a practical circuit should include a reliable way to

safely discharge the capacitor

If the normal load can not be guaranteed to perform this function, perhaps because

it can be disconnected, the circuit should include a bleeder resistor connected as close as

practical across the capacitor. This resistor should consume a current large enough to discharge

the capacitor in a reasonable time, but small enough to avoid unnecessary power waste.

Because a bleeder sets a minimum current drain, the regulation of the circuit, defined as

percentage voltage change from minimum to maximum load, is improved. However in many

cases the improvement is of insignificant magnitude.

The capacitor and the load resistance have a typical time constant τ = RC where

C and R are the capacitance and load resistance respectively. As long as the load resistor is large

enough so that this time constant is much longer than the time of one ripple cycle, the above

configuration will produce a smoothed DC voltage across the load.

In some designs, a series resistor at the load side of the capacitor is added. The smoothing can

then be improved by adding additional stages of capacitor–resistor pairs, often done only for sub-

supplies to critical high-gain circuits that tend to be sensitive to supply voltage noise.

The idealized waveforms shown above are seen for both voltage and current when the load on

the bridge is resistive. When the load includes a smoothing capacitor, both the voltage and the

current waveforms will be greatly changed. While the voltage is smoothed, as described above,

current will flow through the bridge only during the time when the input voltage is greater than

the capacitor voltage. For example, if the load draws an average current of n Amps, and the

diodes conduct for 10% of the time, the average diode current during conduction must be 10n

Amps. This non-sinusoidal current leads to harmonic distortion and a poor power factor in the

AC supply.

In a practical circuit, when a capacitor is directly connected to the output of a bridge,

the bridge diodes must be sized to withstand the current surge that occurs when the power is

turned on at the peak of the AC voltage and the capacitor is fully discharged. Sometimes a small

series resistor is included before the capacitor to limit this current, though in most applications

the power supply transformer's resistance is already sufficient.

Output can also be smoothed using a choke and second capacitor. The choke tends to

keep the current (rather than the voltage) more constant. Due to the relatively high cost of an

effective choke compared to a resistor and capacitor this is not employed in modern equipment.

Some early console radios created the speaker's constant field with the current from the high

voltage ("B +") power supply, which was then routed to the consuming circuits, (permanent

magnets were considered too weak for good performance) to create the speaker's constant

magnetic field. The speaker field coil thus performed 2 jobs in one: it acted as a choke, filtering

the power supply, and it produced the magnetic field to operate the speaker.

D) Voltage Regulator

A voltage regulator is an electrical regulator designed to automatically maintain a

constant voltage level.

The 78xx (also sometimes known as LM78xx) series of devices is a family of self-contained

fixed linear voltage regulator integrated circuits. The 78xx family is a very popular choice for

many electronic circuits which require a regulated power supply, due to their ease of use and

relative cheapness.

When specifying individual ICs within this family, the xx is replaced with a two-digit

number, which indicates the output voltage the particular device is designed to provide (for

example, the 7805 has a 5 volt output, while the 7812 produces 12 volts). The 78xx line is

positive voltage regulators, meaning that they are designed to produce a voltage that is positive

relative to a common ground. There is a related line of 79xx devices which are complementary

negative voltage regulators. 78xx and 79xx ICs can be used in combination to provide both

positive and negative supply voltages in the same circuit, if necessary.

78xx ICs have three terminals and are most commonly found in the TO220 form

factor, although smaller surface-mount and larger TrO3 packages are also available from some

manufacturers. These devices typically support an input voltage which can be anywhere from a

couple of volts over the intended output voltage, up to a maximum of 35 or 40

volts, and can typically provide up to around 1 or 1.5 amps of current (though smaller or larger

packages may have a lower or higher current rating).

6.2 MICROCONTROLLERS:

M ICROPROCESSORS VS. MICROCONTROLLERS:

• Microprocessors are single-chip CPUs used in microcomputers.

• Microcontrollers and microprocessors are different in three main aspects: Hardware

architecture, applications, and instruction set features.

• Hardware architecture: A microprocessor is a single chip CPU while a microcontroller is a

single IC contains a CPU and much of remaining circuitry of a complete computer (e.g., RAM,

ROM, serial interface, parallel interface, timer, and interrupt handling circuit).

• Applications: Microprocessors are commonly used as a CPU in computers while

microcontrollers are found in small, minimum component designs performing control oriented

activities.

• Microprocessor instruction sets are processing Intensive.

• Their instructions operate on nibbles, bytes, words, or even double words.

• Addressing modes provide access to large arrays of data using pointers and offsets.

• They have instructions to set and clear individual bits and perform bit operations.

• They have instructions for input/output operations, event timing, enabling and setting priority

levels for interrupts caused by external stimuli.

• Processing power of a microcontroller is much less than a microprocessor.

Difference between 8051 and 8052:The 8052 microcontroller is the 8051's "big brother." It is a slightly more powerful microcontroller, sporting a number of additional features which the developer may make use of: 256 bytes of Internal RAM (compared to 128 in the standard 8051). A third 16-bit timer, capable of a number of new operation modes and 16-bit reloads. Additional SFRs to support the functionality offered by the third timer.

AT89S52:

Features:

• Compatible with MCS-51 Products

• 8K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 1000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256K Internal RAM

• 32 Programmable I/O Lines

• 3 16-bit Timer/Counters

• Eight Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

Description Of Microcontroller 89S52:

The AT89S52 is a low-power, high-performance CMOS 8-bit micro controller with 8Kbytes of

in-system programmable flash memory. The device is manufactured

Using Atmel’s high-density nonvolatile memory technology and is compatible with the

industry-standard 80C51 micro controller. The on-chip Flash allows the program memory to be

reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a

versatile 8-bit CPU with in-system programmable flash one monolithic http; the Atmel AT89S52

is a powerful micro controller, which provides a highly flexible and cost effective solution to any

cost effective solution to any embedded control applications to any embedded control

applications

Fig8: archetechiture of 8052 The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM,

32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, full duplex serial

port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static

logic for operation down to zero frequency and supports two software selectable power saving

modes. The Idle Mode stops the CPU while allowing the RAM timer/counters, serial port, and

interrupt system to continue functioning. The Power-down mode saves the RAM contents but

freezes the oscillator, disabling all other chip functions until the next interrupt Or hardware reset.

PIN DESCRIPTION OF MICROCONTROLLER 89S52

VCC Supply voltage.

GND Ground.

Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink

eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high impedance

inputs. Port 0 can also be configured to be the multiplexed low order address/data bus during

accesses to external program and data memory. In this mode, P0 has internal pull-ups.Port 0 also

receives the code bytes during Flash Programming and outputs the code bytes during program

verification. External pull-ups are required during program verification.

Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 Output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the

internal pull-ups and can be used as inputs. In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input(P1.0/T2) and the timer/counter 2 trigger input P1.1/T2EX),

respectively, as shown in the following table. Port 1 also receives the low-order address bytes

during Flash programming and verification.

Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the

internal pull-ups and can be used as inputs. Port 2 emits the high-order address byte during

fetches from external program memory and during accesses to external data memories that use

16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when

emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI),

Port 2emits the contents of the P2 Special Function Register. Port 2 also receives the high-order

address bits and some control signals during Flash programming and verification

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are writ 1s are written to Port 3 pins, they are pulled high

by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being

pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of

various special features of the AT89S52, as shown in the following table.Port 3 also receives

some control signals for Flash programming

And verification.

RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets

the device.

ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address

during accesses to external memory. This pin is also the program pulse input (PROG) during

Flash programming. In normal operation, ALE is emitted at a constant rate of1/6 the oscillator

frequency and may be used for external timing or clocking purposes. Note, however, that one

ALE pulse is skipped during each access to external data Memory. If desired, ALE operation can

be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a

MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable

bit has no effect if the micro controller is in external execution mode.

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory. When the

AT89S52 is executing code from external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to external data

memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to

fetch code from external program memory locations starting at 0000H up to FFFFH.Note,

however, that if lock bit 1 is programmed, EA will be internally latched on reset. A should be

strapped to VCC for internal program executions. This pin also receives the 12-voltProgramming

enables voltage (VPP) during Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be

configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or

ceramic resonator may be used. To drive the device from an External clock source, XTAL2

should be left unconnected while XTAL1 is driven, as shown in Figure 2.

Figure 9:. Oscillator Connections

Special Function Register (SFR) Memory: -

Special Function Registers (SFR s) are areas of memory that control specific

functionality of the 8051 processor. For example, four SFRs permit access to the 8051’s 32

input/output lines. Another SFR allows the user to set the serial baud rate, control and access

timers, and configure the 8051’s interrupt system.

The Accumulator: The Accumulator, as its name suggests is used as a general register to

accumulate the results of a large number of instructions. It can hold 8-bit (1-byte) value and is

the most versatile register.

The “R” registers: The “R” registers are a set of eight registers that are named R0, R1. Etc up

to R7. These registers are used as auxiliary registers in many operations.

The “B” registers: The “B” register is very similar to the accumulator in the sense that it may

hold an 8-bit (1-byte) value. Two only uses the “B” register 8051 instructions: MUL AB and

DIV AB.

The Data Pointer: The Data pointer (DPTR) is the 8051’s only user accessible 16-bit (2Bytes)

register. The accumulator, “R” registers are all 1-Byte values. DPTR, as the name suggests, is

used to point to data. It is used by a number of commands, which allow the 8051 to access

external memory.

THE PROGRAM COUNTER AND STACK POINTER:

The program counter (PC) is a 2-byte address, which tells the 8051 where the next instruction to

execute is found in memory. The stack pointer like all registers except DPTR and PC may hold

an 8-bit (1-Byte) value

ADDRESSING MODES: An “addressing mode” refers that you are addressing a given memory location. In

summary, the addressing modes are as follows, with an example of each:

Each of these addressing modes provides important flexibility.

Immediate Addressing MOV A, #20 H

Direct Addressing MOV A, 30 H

Indirect Addressing MOV A, @R0

Indexed Addressing

a. External Direct MOVX A, @DPTR

b. Code In direct MOVC A, @A+DPTR

Immediate Addressing: Immediate addressing is so named because the value to be stored in memory

immediately follows the operation code in memory. That is to say, the instruction itself dictates

what value will be stored in memory. For example, the instruction:

MOV A, #20H:

This instruction uses immediate Addressing because the accumulator will be loaded

with the value that immediately follows in this case 20(hexadecimal). Immediate addressing is

very fast since the value to be loaded is included in the instruction. However, since the value to

be loaded is fixed at compile-time it is not very flexible.

Direct Addressing:

Direct addressing is so named because the value to be stored in memory is obtained by

directly retrieving it from another memory location.

for example:

MOV A, 30h

This instruction will read the data out of internal RAM address 30(hexadecimal) and store

it in the Accumulator. Direct addressing is generally fast since, although the value to be loaded

isn’t included in the instruction, it is quickly accessible since it is stored in the 8051’s internal

RAM. It is also much more flexible than Immediate Addressing since the value to be loaded is

whatever is found at the given address which may variable.

Also it is important to note that when using direct addressing any instruction that refers

to an address between 00h and 7Fh is referring to the SFR control registers that control the 8051

micro controller itself.

Indirect Addressing: Indirect addressing is a very powerful addressing mode, which in many cases provides

an exceptional level of flexibility. Indirect addressing is also the only way to access the extra 128

bytes of internal RAM found on the 8052. Indirect addressing appears as follows:

MOV A, @R0:

This instruction causes the 8051 to analyze Special Function Register (SFR) Memory:

Special Function Registers (SFRs) are areas of memory that control specific functionality of

the 8051 processor. For example, four SFRs permit access to the 8051’s 32 input/output lines.

Another SFR allows the user to set the serial baud rate, control and access timers, and configure

the 8051’s interrupt system.

Timer 2 Registers:

Control and status bits are contained in registers T2CON and T2MOD for

Timer 2 . The register pair (RCAP2H , RCAP2L) are the Capture / Reload registers for

Timer 2 in 16-bit capture mode or 16-bit auto-reload mode .

Interrupt Registers:

The individual interrupt enable bits are in the IE registe . Two priorities can be

set for each of the six interrupt sources in the IP register.

Timer 2:

Timer 2: is a 16-bit Timer / Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating Modes : capture , auto-reload ( up or down Counting ) , and baud rate generator . The modes are selected by bits in T2CON. Timer2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function , the register is incremented in response to a 1-to-0 transition at its corresponding external input pin , T2 .When the samples show a high in one cycle and a low in the next cycle, the count is incremented . Since two machine cycles (24 Oscillator periods ) are required to recognize 1-to-0 transition , the maximum count rate is 1 / 24 of the oscillator frequency .

To ensure that a given level is sampled at least once before it changes , the level should be held for at least one full machine cycle.

Capture Mode:

In the capture mode , two options are selected by bit EXEN2 in T2CON . If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON . This bit can then be used to generate an interrupt. If EXEN2 = 1 , Timer 2 performs the same operation , but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L , respectively Auto-reload (Up or Down Counter):

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD . Upon reset , the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set , Timer 2 can count up or down , depending on the value of the T2EX pin . In this mode , two options are selected by bit EXEN2 in T2CON . If EXEN2 = 0 , Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow . If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX.

Baud Rate Generator:Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK

in T2CON . Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function .The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the following equation .Modes 1 and 3 Baud Rates =Timer 2 Overflow Rate 16The timer operation is different for Timer 2 when it is used as a baud rate generator .Normally ,as a timer , it increments every machine cycle (at 1/12 the oscillator frequency).As a baud rate generator , however, it increments every state time ( at 1/2 the oscillator frequency ) .Timer 0

Timer 0 functions as either a timer or event counter in four modes of operation . Timer 0 is controlled by the four lower bits of the TMOD register and bits 0, 1, 4 and 5 of the TCON register. Mode 0 ( 13-bit Timer) Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of the TL0 register . The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments the TH0 register. Mode 1 ( 16-bit Timer )Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits . Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in cascade. The selected input increments the TL0 register. Mode 2 (8-bit Timer with Auto-Reload)Mode 2 configures timer 0 as an 8-bit timer ( TL0 register ) that automatically reloads from the TH0 register . TL0 overflow sets TF0 flag in the TCON register and reloads TL0 with the contents of TH0, which is preset by software. Mode 3 ( Two 8-bit Timers )Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. This mode is provided for applications requiring an additional 8-bit timer or counter. Timer 1

Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e., when Timer 0 is in mode 3. Baud Rates: The baud rate in Mode 0 is fixed. The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is its value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In the 89S52, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. In case of Timer 2 , these baud rates can be determined by Timer 1 , or by Timer 2 , or by both (one for transmit and the other for receive ).

Fig 10: TCON REGISTER: Timer/counter Control Register

Fig 11:TMOD REGISTER: Timer/Counter 0 and 1 Modes

RFID (Radio Frequency Identification):

Introduction

Radio Frequency Identification (RFID) technology has been attracting considerable attention

with the expectation of improved supply chain visibility for both suppliers and retailers. It will

also improve the consumer shopping experience by making it more likely that the products

they want to purchase are available.

Recent announcements from some key retailers have brought the interest in RFID to the

forefront. This guide is an attempt to familiarize the reader with RFID technology so that they

can be asking the right questions when considering the technology.

What is RFID?

RFID (Radio Frequency Identification) is a method of identifying unique items using radio

waves. Typical RFID systems are made up of 2 major components: readers and tags. The reader,

sometimes called the interrogator, sends and receives RF data to and from the tag via antennas.

A reader may have multiple antennas that are responsible for sending and receiving the radio

waves. The tag, or transponder, is made up of the microchip that stores the data, an antenna, and

a carrier to which the chip and antenna are mounted.

RFID technology is used today in many applications, including security and access control,

transportation and supply chain tracking. It is a technology that works well for collecting

multiple pieces of data on items for tracking and counting purposes in a cooperative

environment.

Is All RFID Created Equal?

There are many different versions of RFID that operate at different radio frequencies. The choice

of frequency is dependent on the requirements of the application.

Three primary frequency bands have been allocated for RFID use.

Low Frequency (125/134 KHz):

Most commonly used for access control and asset tracking.

Mid-Frequency (13.56 MHz):

Used where medium data rate and read ranges are required.

Ultra High-Frequency (850 MHz to 950 MHz and 2.4 GHz to 2.5 GHz): offer the longest

read ranges and high reading speeds.

Applications for RFID within the supply chain can be found at multiple frequencies and

different RFID solutions may be required to meet the varying needs of the marketplace.

Many of today’s RFID technologies cannot reliably cover areas wider than 4 to 5 feet,

making them unsuitable for wide openings that are the norm in manufacturing,

distribution and store

receiving dock environments. Since UHF (Ultra High Frequency) can cover portals up to 9 feet

wide it is gaining industry support as the choice bandwidth for inventory tracking applications

including pallets and cases.

Technology providers are developing readers that work with multiple system protocols and

frequencies so that users will be able to choose the RFID products that work best for their

market and products.

RFID tags are further broken down into two categories:

Active RFID Tags are battery powered .They broadcast a signal to the reader and can transmit

over the greatest Distances (100+ feet).Typically they can cost $4.00 - $20.00 or more and are

used to track high value goods like vehicles and large containers of goods. Shipboard containers

are a good example of an active RFID tag application

Passive RFID Tags do not contain a battery. Instead, they draw their power from the reader.

The reader transmits a low power radio signal through its antenna to the tag, which in turn

receives it through its own antenna to power the integrated circuit (chip). The tag will briefly

converse with the reader for verification and the exchange of data. As a result, passive tags can

transmit information over shorter distances (typically 10 feet or less) than active tags. They have

a smaller memory capacity and are considerably lower in cost ($1.00 or less) making them ideal

for tracking lower cost items.

There are two basic types of chips available on RFID tags, Read-Only and Read-

Write. Read only chips are programmed with unique information stored on them during

the manufacturing process. The information on read-only chips can never be changed.

With Read-Write chips, the user can add information to the tag or write over existing

information when the tag is within range of the reader. Read-Write chips are more expensive

that Read Only chips. Another method used is something called a "WORM" chip (Write Once

Read Many). It can be written once and then becomes "Read only" afterwards. This is a

desirable format since companies will be able to write an EPC (electronic product code) to the

tag when the product is produced and packaged.

How Will RFID Affect Our Industry?

RFID is expected to provide huge advantages to manufacturers by offering the tools to better

plan production and respond more quickly to market demand. It will facilitate automation of

inventory counts and speed shipping and receiving at the distribution level. For retailers, it will

help to reduce stock-outs, enable product tracking and potentially reduce theft and streamline the

POS function. RFID will also open other merchandising opportunities and help with the overall

consumer buying experience.

Due to the current cost of the technology (both tags and infrastructure), the initial phase of

adoption for retailers is at carton and pallet marking applications. The current technology being

adopted for carton and pallet labeling is passive UHF tags (850 MHz – 950 MHz). As the cost of

tags and readers comes down, a wider adoption at the item marking level will develop.

In order for RFID to grow quickly, it is important that standards be developed so that the

technology providers are working toward a common goal of providing low cost and compatible

technologies. Not only will it drive down costs, but standards will also help users to reap the

greatest benefit from their investment by providing value throughout the whole supply chain.

Organizations Focused on Developing RFID Standards:

EPC global, Inc., a division of the Uniform Code Council, and its sponsors are working to

standardize a new Electronic Product Code (EPC) as the next standard for identifying products.

Their goal is not to replace existing bar code standards but to expand the information available

down to unique identifiers for each marked item, and to enable more automatic reading. EPC

utilizes the basic structure of the Global Trade Item Number (GTIN).

EPC global, Inc. has proposed open standards for tags and readers with the intention of bringing

the costs down to a level where RFID tags could be applied to individual items. The work may

lead to the creation of a new global Internet network that would allow companies to track items

and enable end users to access the full benefits of RFID.

EPC global, Inc. has developed a specification for RFID tags to be used in the retail sector. The

specification does not mandate what type of tag to be used but is intended to provide guidelines

on data structure and how the tags should perform so that they can be used over a common

platform. It is tailored around the experiences gained from the implementation of UPC and its

success in the marketplace for more than 25 years. The specification requires that the chip

contain an Electronic Product Code (EPC). The chip must be able to communicate according to

an open standard and meet some minimum requirements so that it can be read by reading devices

anywhere.

6.9 The Electronic Product Code (EPC)

The EPC is a number made up of a header and 3 sets of data as shown in the figure below. The

header identifies the EPC version number – which will allow for different lengths or types of

EPC later on. The second part of the number identifies the EPC manager – typically this would

be the manufacturer of the item the EPC is attached to. The third part is called object class and

refers to the exact type of product– most often the stock-keeping unit (SKU). The fourth series

of numbers is the serial number that is unique to the item. (The second and third sets of data are

similar in function to the numbers in UPC barcodes.)

ELECTRONIC PRODUCT CODE TYPE 1

01 • 0000A89 • 00016F • 000169DCO

Header EPC Manager Object Class Serial Number

8-bits 28-bits 24-bits 36-bits

Above is an example of a 96-bit EPC. It will allow sufficient capacity for 268 million

companies. Each manufacturer will have the ability to create up to 16 million object classes

with 68 billion serial numbers in each class. This should provide sufficient capacity to cover

all products manufactured in the world for many years to come. As an interim step, the Auto-

ID center is also proposing a 64-bit tag in order to minimize cost in the near term.

Potential Issues That Need Consideration When Choosing The Type Of RFID And

Method For Application To Your Products Or Packaging.

Enthusiasm within the RFID industry has resulted in much hype about the technology over the

past several years. As a result, it is important to embrace the technology with a bit of caution.

The following are some of the issues that require close scrutiny when investigating RFID:

Tag Cost – This should not to be confused with chip cost. Although the goal is to bring the cost

of the tag (chip and antenna) down to 5 cents, this goal is in the future since it both assumes

manufacturing breakthroughs and is predicated on consumption in the billions of tags per year.

Today, the cost is closer to "less than 50 cents" for a read/write solution in high (millions)

volume. Ultimate tag cost will also be very much dependent on the type of chip required (read

only versus read/write), size of the antenna needed and how it is packaged to meet a specific

application.

Tag Size – Tag size is dependent on the read range desired. Although the chips are very tiny,

they will not operate without being mounted to an antenna. The size of the antenna will

determine the read distance performance of the tag so understanding the size of the antenna

needed for the application is more important than the size of the chip alone.

Infrastructure Cost – Much focus appears to be placed on the tag cost since it is a recurring

expenditure. Reader cost and infrastructure costs for implementing RFID must also be looked at

very closely as well. Both the software systems requirements and physical environment, in which

RFID is intended to be used, are critical to the ultimate performance of a system and may require

changes to accommodate using it effectively. As an example, RFID chips cannot be read through

metal objects. Other forms of electromagnetic interference may also impede performance of he

technology and require changes to the physical environment where RFID will be used. The

number and types of readers will also be a major expenditure depending on your application.

Read Distances – Read distances for RFID are very much dependent on the frequency chosen for the application. Tag orientation also affects the read range as the range diminishes as the tag is rotated frombeing perpendicular to the path to the reader. Reading reliability is quite good when labels are

alone in a reader field like cases on a conveyor line, but less certain when the labels are

randomly oriented as with labeled cases on a skid. The antenna size (both on the tag and the

readers) will also be a determining factor. Hand held readers are not capable of using as much

power as stationary readers and as a result provide shorter read distances.

Government Regulation – Governments around the world regulate the use of the

frequency spectrum. Different countries have already assigned certain parts of the

spectrum for other uses and as a result, there is virtually no part of the spectrum that is

available everywhere in the world for use by RFID. This means that a RFID tag may

not work in all countries. As an example if you choose the Ultra High Frequency

(UHF) frequency that

Operates at 915MHz in the U.S. and you ship your product to Europe, they may not be

able to be read it since Europe operates in the UHF spectrum at 869 MHz. This is an

important consideration when operating in a global environment.

Anti-Collision – This is an important feature of RFID chips/readers since it will allow

multiple tags to be read while grouped in one reader field. It is not available on all RFID

tags but is an important feature if you are planning to use RFID for inventory counts,

shipping and receiving where multiple tags need to be read at the same time.

Privacy Issues – Consumer groups have expressed concern over the potential (real or

imagined) privacy invasion that might result with widespread RFID item marking. These

groups are pushing for legislation that will require manufacturers to advise consumers

that the products contain RFID devices and must provide a means so that the devices can

be disabled at point of purchase. These issues are most prevalent at the item marking

level and will have little impact on the implementation of carton and pallet labeling.

RFID

Glossary of Commonly Used Terms:

Active Tag – An RFID tag that uses a battery to power its microchip and communicate

with a reader. Active tags can transmit over the greatest distances (100+ feet). Typically

they can cost $20.00 or more and are used to track high value goods like vehicles and

large containers of merchandise.

Agile Reader – A reader that can read different types of RFID tags – either made by

different manufacturers or operating on different frequencies.

Antenna – A device for sending or receiving electromagnetic waves.

Anti-Collision – A feature of RFID systems that enables a batch of tags to be read in

one reader field by preventing the radio waves from interfering with one another. It

also prevents individual tags from being read more than once.

Automatic Data Capture (ADC) – Methods of collecting data and entering it directly

into a computer system without human intervention. Automatic Identification (Auto-ID)

Refers to any technologies for capturing and processing data into a computer system

without using a keyboard. Includes bar coding, RFID and voice recognition.

Auto-ID Center – A group of potential RFID end users, technology companies and

academia. The Auto-ID center began at the Massachusetts Institute of Technology

(MIT) and is now a global entity. It is focused on driving the commercialization of

ultra-low cost RFID solutions that use Internet like infrastructure for tracking goods

throughout the global supply chain. The Auto-ID Center organization is now EPC

global.

Electronic Product Code (EPC)

A standard format for a 96-bit code that was developed by the Auto-ID Center. It is

designed to enable identification of products down to the unique item level. EPC’s

have memory allocated for the product manufacturer, product category and the

individual item. The benefit of EPC’s over traditional bar codes is their ability to be

read without line of sight and their ability to track down to the individual item versus

at the SKU level.

EPC global – The association of companies that are working together to set

standards for RFID in the retail supply chain. EPC global is a joint venture between

EAN International and the Uniform Code Council, Inc.

Radio Frequency Identification (RFID)

A method of identifying items uniquely using radio waves. Radio waves do not

require line of site and can pass through materials like cardboard and plastic but not

metals and some liquids.

Read Range

The distance from which a reader can communicate with a tag. Several factors

including frequency used orientation of the tag, power of the reader and design of

the antenna affect range.

Reader

Also called an interrogator. The RFID reader communicates via radio waves with the

RFID tag and passes information in digital form to the computer system. Readers can

be configured with antennas in many formats including handheld devices, portals or

conveyor mounted.

Read Only Tags

Tags that contain data that cannot be changed. Read only chips are less expensive

than read-write chips.

Read-Write Tags

RFID chips that can be read and written multiple times. Read/Write tags can accept data

at various points along the distribution cycle. This may include transaction data at the

retail point of sale. They are typically more expensive than read only tags but offer more

flexibility.

RFID Transponder

Another name for a RFID tag. Typically refers to a microchip that is attached to an

antenna, which communicates with a reader via radio waves. RFID tags contain serial

numbers that are permanently encoded, and which allow them to be uniquely id

"WORM" Chip (Write Once Read Many) and then becomes "Read only" afterward.

Global System For Mobile Communication (GSM):

6.3.GSM

Definition of GSM:

GSM (Global System for Mobile communications) is an open, digital cellular

technology used for transmitting mobile voice and data services.

GSM (Global System for Mobile communication) is a digital mobile telephone

system that is widely used in Europe and other parts of the world. GSM uses a variation

of Time Division Multiple Access (TDMA) and is the most widely used of the three

digital wireless telephone technologies (TDMA, GSM, and CDMA). GSM digitizes and

compresses data, then sends it down a channel with two other streams of user data, each

in its own time slot. It operates at either the 900 MHz or 1,800 MHz frequency band. It

supports voice calls and data transfer speeds of up to 9.6 kbit/s, together with the

transmission of SMS (Short Message Service).

History

In 1982, the European Conference of Postal and Telecommunications

Administrations (CEPT) created the Group Special Mobile (GSM) to develop a standard

for a mobile telephone system that could be used across Europe. In 1987, a

memorandum of understanding was signed by 13 countries to develop a common cellular

telephone system across Europe. Finally the system created by SINTEF lead by Torleiv

Maseng was selected.

In 1989, GSM responsibility was transferred to the European

Telecommunications Standards Institute (ETSI) and phase I of the GSM specifications

were published in 1990. The first GSM network was launched in 1991 by Radiolinja in

Finland with joint technical infrastructure maintenance from Ericsson.

By the end of 1993, over a million subscribers were using GSM phone networks

being operated by 70 carriers across 48 countries. As of the end of 1997, GSM service

was available in more than 100 countries and has become the de facto standard in Europe

and Asia.

GSM Frequencies

GSM networks operate in a number of different frequency ranges (separated into

GSM frequency ranges for 2G and UMTS frequency bands for 3G). Most 2G GSM

networks operate in the 900 MHz or 1800 MHz bands. Some countries in the Americas

(including Canada and the United States) use the 850 MHz and 1900 MHz bands because

the 900 and 1800 MHz frequency bands were already allocated. Most 3G GSM networks

in Europe operate in the 2100 MHz frequency band. The rarer 400 and 450 MHz

frequency bands are assigned in some countries where these frequencies were previously

used for first-generation systems.

GSM-900 uses 890–915 MHz to send information from the mobile station to the

base station (uplink) and 935–960 MHz for the other direction (downlink), providing 124

RF channels (channel numbers 1 to 124) spaced at 200 kHz. Duplex spacing of 45 MHz

is used. In some countries the GSM-900 band has been extended to cover a larger

frequency range. This 'extended GSM', E-GSM, uses 880–915 MHz (uplink) and 925–

960 MHz (downlink), adding 50 channels (channel numbers 975 to 1023 and 0) to the

original GSM-900 band.

Time division multiplexing is used to allow eight full-rate or sixteen half-rate

speech channels per radio frequency channel. There are eight radio timeslots (giving

eight burst periods) grouped into what is called a TDMA frame. Half rate channels use

alternate frames in the same timeslot. The channel data rate for all 8 channels is

270.833 Kbit/s, and the frame duration is 4.615 ms.

The transmission power in the handset is limited to a maximum of 2 watts in

GSM850/900 and 1 watt in GSM1800/1900. GSM operates in the 900MHz and 1.8GHz

bands in Europe and the 1.9GHz and 850MHz bands in the US. The 850MHz band is also

used for GSM and 3G in Australia, Canada and many South American countries. By

having harmonized spectrum across most of the globe, GSM’s international roaming

capability allows users to access the same services when travelling abroad as at home.

This gives consumers seamless and same number connectivity in more than 218

countries.

Terrestrial GSM networks now cover more than 80% of the world’s population.

GSM satellite roaming has also extended service access to areas where terrestrial

coverage is not available.

Mobile Telephony Standards

1G

The first generation of mobile telephony (written 1G) operated using analogue

communications and portable devices that were relatively large. It used primarily the

following standards:

AMPS (Advanced Mobile Phone System), which appeared in 1976 in the United

States, was the first cellular network standard. It was used primarily in the

Americas, Russia and Asia. This first-generation analogue network had weak

security mechanisms which allowed hacking of telephones lines.

TACS (Total Access Communication System) is the European version of the

AMPS model. Using the 900 MHz frequency band, this system was largely used

in England and then in Asia (Hong-Kong and Japan).

ETACS (Extended Total Access Communication System) is an improved version

of the TACS standard developed in the United Kingdom that uses a larger number

of communication channels.

The first-generation cellular networks were made obsolete by the appearance of an

entirely digital second generation.

Second Generation of Mobile Networks (2G)

The second generation of mobile networks marked a break with the first generation of

cellular telephones by switching from analogue to digital. The main 2G mobile telephony

standards are:

GSM (Global System for Mobile communications) is the most commonly used

standard in Europe at the end of the 20th century and supported in the United

States. This standard uses the 900 MHz and 1800 MHz frequency bands in

Europe. In the United States, however, the frequency band used is the 1900 MHz

band. Portable telephones that are able to operate in Europe and the United States

are therefore called tri-band.

CDMA (Code Division Multiple Access) uses a spread spectrum technique that

allows a radio signal to be broadcast over a large frequency range.

TDMA (Time Division Multiple Access) uses a technique of time division of

communication channels to increase the volume of data transmitted

simultaneously. TDMA technology is primarily used on the American continent,

in New Zealand and in the Asia-Pacific region.

With the 2G networks, it is possible to transmit voice and low volume digital data, for

example text messages (SMS, for Short Message Service) or multimedia messages

(MMS, for Multimedia Message Service). The GSM standard allows a maximum data

rate of 9.6 kbps.

Extensions have been made to the GSM standard to improve throughput. One of

these is the GPRS (General Packet Radio System) service which allows theoretical data

rates on the order of 114 Kbit/s but with throughput closer to 40 Kbit/s in practice. As

this technology does not fit within the "3G" category, it is often referred to as 2.5G

The EDGE (Enhanced Data Rates for Global Evolution) standard, billed

as 2.75G, quadruples the throughput improvements of GPRS with its theoretical data rate

of 384 Kbps, thereby allowing the access for multimedia applications. In reality, the

EDGE standard allows maximum theoretical data rates of 473 Kbit/s, but it has been

limited in order to comply with the IMT-2000 (International Mobile

Telecommunications-2000) specifications from the ITU (International

Telecommunications Union).

3G

The IMT-2000 (International Mobile Telecommunications for the year 2000)

specifications from the International Telecommunications Union (ITU) defined the

characteristics of 3G (third generation of mobile telephony). The most important of these

characteristics are:

1. High transmission data rate.

2. 144 Kbps with total coverage for mobile use.

3. 384 Kbps with medium coverage for pedestrian use.

4. 2 Mbps with reduced coverage area for stationary use.

5. World compatibility.

6. Compatibility of 3rd generation mobile services with second generation networks.

3G offers data rates of more than 144 Kbit/s, thereby allowing the access to

multimedia uses such as video transmission, video-conferencing or high-speed internet

access. 3G networks use different frequency bands than the previous networks: 1885-

2025 MHz and 2110-2200 MHz.

The main 3G standard used in Europe is called UMTS (Universal Mobile

Telecommunications System) and uses WCDMA (Wideband Code Division Multiple

Access) encoding. UMTS technology uses 5 MHz bands for transferring voice and data,

with data rates that can range from 384 Kbps to 2 Mbps. HSDPA (High Speed Downlink

Packet Access) is a third generation mobile telephony protocol, (considered as "3.5G"),

which is able to reach data rates on the order of 8 to 10 Mbps. HSDPA technology uses

the 5 GHz frequency band and uses WCDMA encoding.

Introduction to the GSM Standard

The GSM (Global System for Mobile communications) network is at the start of

the 21st century, the most commonly used mobile telephony standard in Europe. It is

called as Second Generation (2G) standard because communications occur in an entirely

digital mode, unlike the first generation of portable telephones. When it was first

standardized in 1982, it was called as Group Special Mobile and later, it became an

international standard called "Global System for Mobile communications" in 1991.

In Europe, the GSM standard uses the 900 MHz and 1800 MHz frequency bands.

In the United States, however, the frequency band used is the 1900 MHz band. For this

reason, portable telephones that are able to operate in both Europe and the United States

are called tri-band while those that operate only in Europe are called bi-band.

The GSM standard allows a maximum throughput of 9.6 kbps which allows

transmission of voice and low-volume digital data like text messages (SMS, for Short

Message Service) or multimedia messages (MMS, for Multimedia Message Service).

GSM Standards:

GSM uses narrowband TDMA, which allows eight simultaneous calls on the

same radio frequency. There are three basic principles in multiple access, FDMA

(Frequency Division Multiple Access), TDMA (Time Division Multiple Access), and

CDMA (Code Division Multiple Access). All three principles allow multiple users to

share the same physical channel. But the two competing technologies differ in the way

user sharing the common resource.

TDMA allows the users to share the same frequency channel by dividing the

signal into different time slots. Each user takes turn in a round robin fashion for

transmitting and receiving over the channel. Here, users can only transmit in their

respective time slot.

CDMA uses a spread spectrum technology that is it spreads the information

contained in a particular signal of interest over a much greater bandwidth than the

original signal. Unlike TDMA, in CDMA several users can transmit over the channel at

the same time.

TDMA in brief:

In late1980’s, as a search to convert the existing analog network to digital as a

means to improve capacity, the cellular telecommunications industry association chose

TDMA over FDMA. Time Division Multiplex Access is a type of multiplexing where

two or more channels of information are transmitted over the same link by allocating a

different time interval for the transmission of each channel. The most complex

implementation using TDMA principle is of GSM’s (Global System for Mobile

communication). To reduce the effect of co-channel interference, fading and multipath,

the GSM technology can use frequency hopping, where a call jumps from one channel to

another channel in a short interval.

Fiure.:TDMA Access

TDMA systems still rely on switch to determine when to perform a handoff.

Handoff occurs when a call is switched from one cell site to another while travelling. The

TDMA handset constantly monitors the signals coming from other sites and reports it to

the switch without caller’s awareness. The switch then uses this information for making

better choices for handoff at appropriate times. TDMA handset performs hard handoff,

i.e., whenever the user moves from one site to another, it breaks the connection and then

provides a new connection with the new site.

Advantages of TDMA:

There are lots of advantages of TDMA in cellular technologies.

1. It can easily adapt to transmission of data as well as voice communication.

2. It has an ability to carry 64 kbps to 120 Mbps of data rates. This allows the

operator to do services like fax, voice band data and SMS as well as bandwidth

intensive application such as multimedia and video conferencing.

3. Since TDMA technology separates users according to time, it ensures that there

will be no interference from simultaneous transmissions.

4. It provides users with an extended battery life, since it transmits only portion of

the time during conversations. Since the cell size grows smaller, it proves to save

base station equipment, space and maintenance.

TDMA is the most cost effective technology to convert an analog system to digital.

Disadvantages of TDMA:

One major disadvantage using TDMA technology is that the users has a

predefined time slot. When moving from one cell site to other, if all the time slots in this

cell are full the user might be disconnected. Likewise, if all the time slots in the cell in

which the user is currently in are already occupied, the user will not receive a dial tone.

The second problem in TDMA is that it is subjected to multipath distortion. To

overcome this distortion, a time limit can be used on the system. Once the time limit is

expired, the signal is ignored.

The concept of cellular network

Mobile telephone networks are based on the concept of cells, circular zones that

overlap to cover a geographical area.

Figure.: Cell Structure

Cellular networks are based on the use of a central transmitter-receiver in each

cell, called a "base station" (or Base Transceiver Station, written BTS). The smaller the

radius of a cell, the higher is the available bandwidth. So, in highly populated urban

areas, there are cells with a radius of a few hundred meters, while huge cells of up to 30

kilometers provide coverage in rural areas.

In a cellular network, each cell is surrounded by 6 neighbouring cells (thus a cell

is generally drawn as a hexagon). To avoid interference, adjacent cells cannot use the

same frequency. In practice, two cells using the same frequency range must be separated

by a distance of two to three times the diameter of the cell.

Architecture of the GSM Network

In a GSM network, the user terminal is called a mobile station. A mobile station

is made up of a SIM (Subscriber Identity Module) card allowing the user to be uniquely

identified and a mobile terminal. The terminals (devices) are identified by a unique 15-

digit identification number called IMEI (International Mobile Equipment Identity). Each

SIM card also has a unique (and secret) identification number called IMSI (International

Mobile Subscriber Identity). This code can be protected using a 4-digit key called a PIN

code.

The SIM card therefore allows each user to be identified independently of the

terminal used during communication with a base station. Communications occur through

a radio link (air interface) between a mobile station and a base station.

Figure.: Coverage Area for GSM

All the base stations of a cellular network are connected to a base station

controller (BSC) which is responsible for managing distribution of the resources. The

system consisting of the base station controller and its connected base stations is called

the Base Station Subsystem (BSS).

Finally, the base station controllers are themselves physically connected to

the Mobile Switching Centre (MSC), managed by the telephone network operator,

which connects them to the public telephone network and the Internet. The MSC belongs

to a Network Station Subsystem (NSS), which is responsible for managing user

identities, their location and establishment of communications with other subscribers. The

MSC is generally connected to databases that provide additional functions:

1. The Home Location Register (HLR) is a database containing information

(geographic position, administrative information etc.) of the subscribers registered

in the area of the switch (MSC).

2. The Visitor Location Register (VLR) is a database containing information of

users other than the local subscribers. The VLR retrieves the data of a new user

from the HLR of the user's subscriber zone. The data is maintained as long as the

user is in the zone and is deleted when the user leaves or after a long period of

inactivity (terminal off).

3. The Equipment Identify Register (EIR) is a database listing the mobile

terminals.

4. The Authentication Centre (AUC) is responsible for verifying user identities.

5. The cellular network formed in this way is designed to support mobility via

management of handovers (movements from one cell to another).

Finally, GSM networks support the concept of roaming i.e., movement from one

operator network to another.

A GSM network consists of the following components:

Mobile station: The GSM mobile station (or mobile phone) communicates with other

parts of the system through the base-station system.

    

GSM Base station system (BSS).

    

Base transceiver station (BTS):The base transceiver station (BTS) handles the

radio interface to the mobile station. The base transceiver station is the radio

equipment (transceivers and antennas)

Base station controller (BSC):The BSC provides the control functions and

physical links between the MSC and BTS. It provides functions such as handover,

cell configuration data and control of RF power levels in base transceiver stations.

A number of BSCs are served by a MSC.

        

GSM Switching System

    

Mobile services switching center (MSC): The MSC performs the telephony

switching functions of the system. It also performs such functions as toll ticketing,

network interfacing, common channel signaling, and others.

    

Home location register (HLR): The HLR database is used for storage and

management of subscriptions. The home location register stores permanent data

about subscribers, including a subscriber's service profile, location information,

and activity status.

    

Visitor location register (VLR): The VLR database contains temporary

information about subscribers that is needed by the mobile services switching

center (MSC) in order to service visiting subscribers. When a mobile station

roams into a new mobile services switching center (MSC) area, the visitor

location register (VLR) connected to that MSC will request data about the mobile

station from the HLR, reducing the need for interrogation of the home location

register (HLR).

    

Authentication center (AUC): The AUC provides authentication and encryption

parameters that verify the user's identity and ensure the confidentiality of each

call. The authentication center (AUC) also protects network operators from fraud.

    

Equipment identity register (EIR): The EIR database contains information on

the identity of mobile equipment to prevent calls from stolen, unauthorized or

defective mobile stations.

    

Message center (MXE): The MXE is a node that provides integrated voice, fax,

and data messaging.

    

Mobile service node (MSN): The MSN is the node that handles the mobile

intelligent network (IN) services.

    

Gateway mobile services switching center (GMSC): A gateway mobile

services switching center (GMSC) is a node used to interconnect two networks.

    

GSM interworking unit (GIWU): The GIWU consists of both hardware and

software that provides an interface to various networks for data communications.

Through the GSM interworking unit (GIWU), users can alternate between speech

and data during the same call.

         

Operation and support system (OSS): The OSS is the functional entity from

which the network operator monitors and controls the system. The purpose of

operation and support system is to offer support for centralized, regional, and

local operational and maintenance activities that are required for a GSM network.

Introduction to Modem:

Modem stands for modulator-demodulator.

A modem is a device or program that enables a computer to transmit data over

telephone or cable lines. Computer information is stored digitally, whereas information

transmitted over telephone lines is transmitted in the form of analog waves. A modem

converts between these two forms.

Fortunately, there is one standard interface for connecting external modems to

computers called RS-232. Consequently, any external modem can be attached to any

computer that has an RS-232 port, which almost all personal computers have. There are

also modems that come as an expansion board that can be inserted into a vacant

expansion slot. These are sometimes called onboard or internal modems.

While the modem interfaces are standardized, a number of different protocols for

formatting data to be transmitted over telephone lines exist. Some, like CCITT V.34 are

official standards, while others have been developed by private companies. Most modems

have built-in support for the more common protocols at slow data transmission speeds at

least, most modems can communicate with each other. At high transmission speeds,

however, the protocols are less standardized.

Apart from the transmission protocols that they support, the following characteristics

distinguish one modem from another:

Bps: How fast the modem can transmit and receive data. At slow rates, modems

are measured in terms of baud rates. The slowest rate is 300 baud (about 25 cps).

At higher speeds, modems are measured in terms of bits per second (bps). The

fastest modems run at 57,600 bps, although they can achieve even higher data

transfer rates by compressing the data. Obviously, the faster the transmission rate,

the faster the data can be sent and received. It should be noted that the data cannot

be received at a faster rate than it is being sent.

Voice/data: Many modems support a switch to change between voice and data

modes. In data mode, the modem acts like a regular modem. In voice mode, the

modem acts like a regular telephone. Modems that support a voice/data switch

have a built-in loudspeaker and microphone for voice communication.

Auto-answer: An auto-answer modem enables the computer to receive calls in

the absence of the operator.

Data compression: Some modems perform data compression, which enables

them to send data at faster rates. However, the modem at the receiving end must

be able to decompress the data using the same compression technique.

Flash memory: Some modems come with flash memory rather than conventional

ROM which means that the communications protocols can be easily updated if

necessary.

Fax capability: Most modern modems are fax modems, which mean that they

can send and receive faxes.

GSM Modem:

A GSM modem is a wireless modem that works with a GSM wireless network. A

wireless modem behaves like a dial-up modem. The main difference between them is that

a dial-up modem sends and receives data through a fixed telephone line while a wireless

modem sends and receives data through radio waves.

Figure.:GSM Modem

A GSM modem can be an external device or a PC Card / PCMCIA Card.

Typically, an external GSM modem is connected to a computer through a serial cable or a

USB cable. A GSM modem in the form of a PC Card / PCMCIA Card is designed for use

with a laptop computer. It should be inserted into one of the PC Card / PCMCIA Card

slots of a laptop computer. Like a GSM mobile phone, a GSM modem requires a SIM

card from a wireless carrier in order to operate.

A SIM card contains the following information:

Subscriber telephone number (MSISDN)

International subscriber number (IMSI, International Mobile Subscriber Identity)

State of the SIM card

Service code (operator)

Authentication key

PIN (Personal Identification Code)

PUK (Personal Unlock Code)

Computers use AT commands to control modems. Both GSM modems and dial-up

modems support a common set of standard AT commands. In addition to the standard AT

commands, GSM modems support an extended set of AT commands. These extended AT

commands are defined in the GSM standards. With the extended AT commands, the

following operations can be performed:

Reading, writing and deleting SMS messages.

Sending SMS messages.

Monitoring the signal strength.

Monitoring the charging status and charge level of the battery.

Reading, writing and searching phone book entries.

Figure.:Interfacing PC to Modem

The number of SMS messages that can be processed by a GSM modem per minute is

very low i.e., about 6 to 10 SMS messages per minute.

Introduction to AT Commands

AT commands are instructions used to control a modem. AT is the abbreviation of

ATtention. Every command line starts with "AT" or "at". That's the reason, modem

commands are called AT commands. Many of the commands that are used to control

wired dial-up modems, such as ATD (Dial), ATA (Answer), ATH (Hook control) and

ATO (Return to online data state) are also supported by GSM modems and mobile

phones.

Besides this common AT command set, GSM modems and mobile phones

support an AT command set that is specific to the GSM technology, which includes

SMS-related commands like AT+CMGS (Send SMS message), AT+CMSS (Send SMS

message from storage), AT+CMGL (List SMS messages) and AT+CMGR (Read SMS

messages).

It should be noted that the starting "AT" is the prefix that informs the modem

about the start of a command line. It is not part of the AT command name. For example,

D is the actual AT command name in ATD and +CMGS is the actual AT command name

in AT+CMGS.

Some of the tasks that can be done using AT commands with a GSM modem or mobile

phone are listed below:

Get basic information about the mobile phone or GSM modem. For example,

name of manufacturer (AT+CGMI), model number (AT+CGMM), IMEI number

(International Mobile Equipment Identity) (AT+CGSN) and software version

(AT+CGMR).

Get basic information about the subscriber. For example, MSISDN (AT+CNUM)

and IMSI number (International Mobile Subscriber Identity) (AT+CIMI).

Get the current status of the mobile phone or GSM/GPRS modem. For example,

mobile phone activity status (AT+CPAS), mobile network registration status

(AT+CREG), radio signal strength (AT+CSQ), battery charge level and battery

charging status (AT+CBC).

Establish a data connection or voice connection to a remote modem (ATD, ATA,

etc).

Send and receive fax (ATD, ATA, AT+F*).

Send (AT+CMGS, AT+CMSS), read (AT+CMGR, AT+CMGL), write

(AT+CMGW) or delete (AT+CMGD) SMS messages and obtain notifications of

newly received SMS messages (AT+CNMI).

Read (AT+CPBR), write (AT+CPBW) or search (AT+CPBF) phonebook entries.

Perform security-related tasks, such as opening or closing facility locks

(AT+CLCK), checking whether a facility is locked (AT+CLCK) and changing

passwords(AT+CPWD).

(Facility lock examples: SIM lock [a password must be given to the SIM card

every time the mobile phone is switched on] and PH-SIM lock [a certain SIM

card is associated with the mobile phone. To use other SIM cards with the mobile

phone, a password must be entered.])

Control the presentation of result codes / error messages of AT commands. For

example, the user can control whether to enable certain error messages

(AT+CMEE) and whether error messages should be displayed in numeric format

or verbose format (AT+CMEE=1 or AT+CMEE=2).

Get or change the configurations of the mobile phone or GSM/GPRS modem. For

example, change the GSM network (AT+COPS), bearer service type

(AT+CBST), radio link protocol parameters (AT+CRLP), SMS center address

(AT+CSCA) and storage of SMS messages (AT+CPMS).

Save and restore configurations of the mobile phone or GSM/GPRS modem. For

example, save (AT+CSAS) and restore (AT+CRES) settings related to SMS

messaging such as the SMS center address.

It should be noted that the mobile phone manufacturers usually do not implement all AT

commands, command parameters and parameter values in their mobile phones. Also, the

behavior of the implemented AT commands may be different from that defined in the

standard. In general, GSM modems, designed for wireless applications, have better

support of AT commands than ordinary mobile phones.

Basic concepts of SMS technology

1. Validity Period of an SMS Message

An SMS message is stored temporarily in the SMS center if the recipient mobile

phone is offline. It is possible to specify the period after which the SMS message will be

deleted from the SMS center so that the SMS message will not be forwarded to the

recipient mobile phone when it becomes online. This period is called the validity period.

A mobile phone should have a menu option that can be used to set the validity period.

After setting it, the mobile phone will include the validity period in the outbound SMS

messages automatically.

2. Message Status Reports

Sometimes the user may want to know whether an SMS message has reached the

recipient mobile phone successfully. To get this information, you need to set a flag in the

SMS message to notify the SMS center that a status report is required about the delivery

of this SMS message. The status report is sent to the user mobile in the form of an SMS

message.

A mobile phone should have a menu option that can be used to set whether the

status report feature is on or off. After setting it, the mobile phone will set the

corresponding flag in the outbound SMS messages for you automatically. The status

report feature is turned off by default on most mobile phones and GSM modems.

3. Message Submission Reports

After leaving the mobile phone, an SMS message goes to the SMS center. When

it reaches the SMS center, the SMS center will send back a message submission report to

the mobile phone to inform whether there are any errors or failures (e.g. incorrect SMS

message format, busy SMS center, etc). If there is no error or failure, the SMS center

sends back a positive submission report to the mobile phone. Otherwise it sends back a

negative submission report to the mobile phone. The mobile phone may then notify the

user that the message submission was failed and what caused the failure.

If the mobile phone does not receive the message submission report after a period

of time, it concludes that the message submission report has been lost. The mobile phone

may then send the SMS message again to the SMS center. A flag will be set in the new

SMS message to inform the SMS center that this SMS message has been sent before. If

the previous message submission was successful, the SMS center will ignore the new

SMS message but send back a message submission report to the mobile phone. This

mechanism prevents the sending of the same SMS message to the recipient multiple

times.

Sometimes the message submission report mechanism is not used and the

acknowledgement of message submission is done in a lower layer.

4 .Message Delivery Reports

After receiving an SMS message, the recipient mobile phone will send back a

message delivery report to the SMS center to inform whether there are any errors or

failures (example causes: unsupported SMS message format, not enough storage space,

etc). This process is transparent to the mobile user. If there is no error or failure, the

recipient mobile phone sends back a positive delivery report to the SMS center.

Otherwise it sends back a negative delivery report to the SMS center.

If the sender requested a status report earlier, the SMS center sends a status report

to the sender when it receives the message delivery report from the recipient. If the SMS

center does not receive the message delivery report after a period of time, it concludes

that the message delivery report has been lost. The SMS center then ends the SMS

message to the recipient for the second time.

Sometimes the message delivery report mechanism is not used and the

acknowledgement of message delivery is done in a lower layer.

EEPROM:

EEPROM (also written E2PROM and pronounced "e-e-prom," "double-e prom" or

simply "e-squared") stands for Electrically Erasable Programmable Read-Only Memory

and is a type of non-volatile memory used in computers and other electronic devices to

store small amounts of data that must be saved when power is removed, e.g., calibration

tables or device configuration.

When larger amounts of static data are to be stored (such as in USB flash drives) a

specific type of EEPROM such as flash memory is more economical than traditional

EEPROM devices.

EEPROMs are realized as arrays of floating-gate transistors.

EEPROM (electrically erasable programmable read-only memory) is user-modifiable

read-only memory (ROM) that can be erased and reprogrammed (written to) repeatedly

through the application of higher than normal electrical voltage. Unlike EPROM chips,

EEPROMs do not need to be removed from the computer to be modified. However, an

EEPROM chip has to be erased and reprogrammed in its entirety, not selectively. It also

has a limited life - that is, the number of times it can be reprogrammed is limited to tens

or hundreds of thousands of times. In an EEPROM that is frequently reprogrammed

while the computer is in use, the life of the EEPROM can be an important design

consideration

Functions of EEPROM

There are different types of electrical interfaces to EEPROM devices. Main categories of

these interface types are:

Serial bus

Parallel bus

How the device is operated depends on the electrical interface.

[edit] Serial bus devices

Most common serial interface types are SPI, I²C, Microwire, UNI/O, and 1-Wire. These

interfaces require between 1 and 4 control signals for operation, resulting in a memory

device in an 8 pin (or less) package.

The serial EEPROM typically operates in three phases: OP-Code Phase, Address Phase

and Data Phase. The OP-Code is usually the first 8-bits input to the serial input pin of the

EEPROM device (or with most I²C devices, is implicit); followed by 8 to 24 bits of

addressing depending on the depth of the device, then data to be read or written.

Each EEPROM device typically has its own set of OP-Code instructions to map to

different functions. Some of the common operations on SPI EEPROM devices are:

Write Enable (WREN)

Write Disable (WRDI)

Read Status Register (RDSR)

Write Status Register (WRSR)

Read Data (READ)

Write Data (WRITE)

Other operations supported by some EEPROM devices are:

Program

Sector Erase

Chip Erase commands

[edit] Parallel bus devices

Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide

enough to cover the complete memory. Most devices have chip select and write protect

pins. Some microcontrollers also have integrated parallel EEPROM.

Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM,

but these devices are larger due to the higher pin count (28 pins or more) and have been

decreasing in popularity in favor of serial EEPROM or Flash.

[edit] Other devices

EEPROM memory is used to enable features in other types of products that are not

strictly memory products. Products such as real-time clocks, digital potentiometers,

digital temperature sensors, among others, may have small amounts of EEPROM to store

calibration information or other data that needs to be available in the event of power loss.

[edit] Related types

Flash memory is a later form of EEPROM. In the industry, there is a convention to

reserve the term EEPROM to byte-wise erasable memories compared to block-wise

erasable flash memories. EEPROM takes more die area than flash memory for the same

capacity because each cell usually needs both a read, write and erase transistor, while in

flash memory the erase circuits are shared by large blocks of cells (often 512×8).

Newer non-volatile memory technologies such as FeRAM and MRAM are slowly

replacing EEPROMs in some applications, but are expected to remain a small fraction of

the EEPROM market for the foreseeable future.

[edit] Comparison with EPROM and EEPROM/Flash

The difference between EPROM and EEPROM lies in the way that the memory

programs and erases. EEPROM can be programmed and erased electrically using field

electron emission (more commonly known in the industry as "Fowler–Nordheim

tunneling").

EPROMs can't be erased electrically, and are programmed via hot carrier injection onto

the floating gate. Erase is via an ultraviolet light source, although in practice many

EPROMs are encapsulated in plastic that is opaque to UV light, and are "one-time

programmable".

Most NOR Flash memory is a hybrid style—programming is through hot carrier injection

and erase is through Fowler–Nordheim tunneling

EEPROM (IC 24C02):

Features• Low-voltage and Standard-voltage Operation – 1.8

(VCC = 1.8V to 5.5V)

• Internally Organized 256 x 8 (2K)

• Two-wire Serial Interface

• Schmitt Trigger, Filtered Inputs for Noise Suppression

• Bidirectional Data Transfer Protocol

• 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility

• Write Protect Pin for Hardware Data Protection

• 8-byte Page (2K) Write Modes

• Partial Page Writes Allowed

• Self-timed Write Cycle (5 ms max)

• High-reliability

– Endurance: 1 Million Write Cycles –

Data Retention: 100 Years

• 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead

SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages

• Lead-free/Halogen-free

• Available in Automotive

• Die Sales: Wafer Form and Tape and Reel

Description•The AT24C02B provides 2048 bits of serial electrically erasable and programmable

read-only memory (EEPROM) organized as 256 words of 8 bits each. The device is

optimized for use in many industrial and commercial applications where low-power

and low-voltage operation are essential. The AT24C02B is available in space-saving

8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead

SOT23, 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire

serial interface. In addition, the AT24C02B is available in 1.8V (1.8V to 5.5V)

version.

Pin Configurations of IC 24C02B

Table 0-1.

Pin Name Function

A0 - A2 Address Inputs

SDA Serial Data

SCLSerial Clock Input

WP Write Protect

GND Ground

VCC Power Supply

PIN DIAGRAM DESCRIPTION:

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-O Red with any number of other open-drain or open-

collector devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device

address inputs that are hard wired for the AT24C02B. As many as eight 2K devices may

be addressed on a sin-gle bus system (device addressing is discussed in detail under the

Device Addressing section).

WRITE PROTECT (WP): The AT24C02B has a write protect pin that provides

hardware data protection. The write protect pin allows normal read/write operations when

connected to ground

(GND). When the write protect pin is connected to VCC, the write protection feature is

enabled and operates as shown in Table 1-1.

Table 1-1.

WP Pin

Part of the Array Protected

Status24C02B

At VCC Full (2K) Array

At GNDNormal Read/Write Operations

Memory Organization

AT24C02B, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes

each, the 2K requires an 8-bit data word address for random word addressing.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an

external device. Data on the SDA pin may change only during SCL low time periods (see

Figure 5-2 on page 8). Data changes during SCL high periods will indicate a start or stop

condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start

condition which must precede any other command

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop

condition. After a read sequence, the stop command will place the EEPROM in a standby

power mode

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from

the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has

received each word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C02B features a low-power standby mode which is

enabled:

Upon power-up and .

After the receipt of the STOP bit and the completion of any internal operations.

2-Wire Software Reset: After an interruption in protocol, power loss or system reset,

any 2-wire part can be reset by following these steps: (a) Create a start bit condition, (b)

clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below.

The device is ready for next communications after above steps have been completed.

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

SCL

SDA8th BIT

ACK

WORDn

(1)

STOP

twrSTART

CONDITIONCONDITIO

N

Figure 4. Data Validity

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

Figure 5-2. Data Validity

SDA

SCL

DATA STABLE DATA STABLE

Figure 5-3. Start and Stop Definition

SDA

SCL

START STOP

Figure 5-4. Output Acknowledge

SCL1 8 9

DATA IN

DATA OUT

START

ACKNOWLEDGE

Device Addressing

The 2K EEPROM device requires an 8-bit device address word following a start

condition to enable the chip for a read or write operation .The device address word

consists of a mandatory one, zero sequence for the first four most significant bits as

shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and

A0 device address bits for the 2K EEPROM. These 3 bits must compare to their

corresponding hard-wired input pins. The eighth bit of the device address is the

read/write operation select bit. A read operation is initiated if this bit is high and a write

operation is initiated if this bit is low. Upon a compare of the device address, the

EEPROM will output a zero. If a compare is not made, the chip will return to a standby

state.

Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM

will again respond with a zero and then clock in the first 8-bit data word. Following

receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device,

such as a microcontroller, must terminate the write sequence with a stop condition. At

this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile

memory. All inputs are disabled during this write cycle and the EEPROM will not

respond until the write is complete

PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write.

A page write is initiated the same as a byte write, but the microcontroller does not send a

stop condition after the first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcontroller can transmit up to seven

data words. The EEPROM will respond with a zero after each data word received. The

microcontroller must terminate the page write sequence with a stop condition

The data word address lower three bits are internally incremented following the receipt of

each data word. The higher data word address bits are not incremented, retaining the

memory page row location. When the word address, internally generated, reaches the

page boundary, the following byte is placed at the beginning of the same page. If more

than eight data words are transmitted to the EEPROM, the data word address will “roll

over” and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and

the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves

sending a start condition followed by the device address word. The read/write bit is

representative of the operation desired. Only if the internal write cycle has completed will

the EEPROM respond with a zero allowing the read or write sequence to continue.

Read Operations

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to one.

There are three read operations:

Current address read

Random address read and

Sequential read.

CURRENT ADDRESS READ

The internal data word address counter maintains the last address accessed during the last

read or write operation, incremented by one. This address stays valid between operations

as long as the chip power is maintained. The address “roll over” during read is from the

last byte of the last memory page to the first byte of the first page. The address “roll

over” during write is from the last byte of the current page to the first byte of the same

page. Once the device address with the read/write select bit set to one is clocked in and

acknowledged by the EEPROM, the current address data word is serially clocked out.

The microcontroller does not respond with an input zero but does generate a following

stop condition

RANDOM READ

A random read requires a “dummy” byte write sequence to load in the data word address.

Once the device address word and data word address are clocked in and acknowledged by

the EEPROM, the microcontroller must generate another start condition. The

microcontroller now initiates a current address read by sending a device address with the

read/write select bit high. The EEPROM acknowledges the device address and serially

clocks out the data word. The microcontroller does not respond with a zero but does

generate a following stop condition

SEQUENTIAL READ

Sequential reads are initiated by either a current address read or a ran-dom address read.

After the microcontroller receives a data word, it responds with an acknowledge. As long

as the EEPROM receives an acknowledge, it will continue to increment the data word

address and serially clock out sequential data words. When the memory address limit is

reached, the data word address will “roll over” and the sequential read will continue. The

sequential read operation is terminated when the microcontroller does not respond with a

zero but does generate a following stop condition.

Figure . Device Address

MSB LSB

Figure . Byte Write

Figure . Page Write

Figure Current Address Read

Figure . Random Read

Figure Sequential Read

SERIAL COMMUNICATION

THEORY:In order to connect micro controller to a modem or a pc to modem a serial port is

used. Serial is a very common protocol for device communication that is standard on almost every PC. Most computers include two RS-232 based serial ports. Serial is also a common communication protocol that is used by many devices for instrumentation; numerous GPIB-compatible devices also come with an RS-232 port. Furthermore, serial communication can be used for data acquisition in conjunction with a remote sampling device.

The concept of serial communication is simple. The serial port sends and receives bytes of information one bit at a time. Although this is slower than parallel communication, which allows the transmission of an entire byte at once, it is simpler and can be used over longer distances. For example, the IEEE 488 specifications for parallel communication state that the cabling between equipment can be no more than 20 meters total, with no more than 2 meters between any two devices. Serial, however, can extend as much as 1200 meters.

Typically, serial is used to transmit ASCII data. Communication is completed using 3 transmission lines: (1) Ground, (2) Transmit, and (3) Receive. Since serial is asynchronous, the port is able to transmit data on one line while receiving data on another. Other lines are available for handshaking, but are not required. The important serial characteristics are baud rate, data bits, stop bits, and parity. For two ports to communicate, these parameters must match.

Baud rate: It is a speed measurement for communication. It indicates the number of

bit transfers per second. For example, 300 baud is 300 bits per second. When a clock

cycle is referred it means the baud rate. For example, if the protocol calls for a 4800 baud

rate, then the clock is running at 4800Hz. This means that the serial port is sampling the

data line at 4800Hz. Common baud rates for telephone lines are 14400, 28800, and

33600. Baud rates greater than these are possible, but these rates reduce the distance by

which devices can be separated. These high baud rates are used for device

communication where the devices are located together, as is typically the case with GPIB

devices.

Data bits: Measurement of the actual data bits in a transmission. When the computer

sends a packet of information, the amount of actual data may not be a full 8 bits. Standard

values for the data packets are 5, 7, and 8 bits. Which setting choosen depends on what

information transferred. For example, standard ASCII has values from 0 to 127 (7 bits).

Extended ASCII uses 0 to 255 (8 bits). If the data being transferred is simple text

(standard ASCII), then sending 7 bits of data per packet is sufficient for communication.

A packet refers to a single byte transfer, including start/stop bits, data bits, and parity.

Since the number of actual bits depend on the protocol selected, the term packet is used

to cover all instances.

Stop bits: used to signal the end of communication for a single packet. Typical

values are 1, 1.5, and 2 bits. Since the data is clocked across the lines and each device has

its own clock, it is possible for the two devices to become slightly out of sync. Therefore,

the stop bits not only indicate the end of transmission but also give the computers some

room for error in the clock speeds. The more bits that are used for stop bits, the greater

the lenience in synchronizing the different clocks, but the slower the data transmission

rate.

Parity: A simple form of error checking that is used in serial communication. There are

four types of parity: even, odd, marked, and spaced. The option of using no parity is also

available. For even and odd parity, the serial port sets the parity bit (the last bit after the

data bits) to a value to ensure that the transmission has an even or odd number of logic

high bits. For example, if the data is 011, then for even parity, the parity bit is 0 to keep

the number of logic-high bits even. If the parity is odd, then the parity bit is 1, resulting in

3 logic-high bits. Marked and spaced parity does not actually check the data bits, but

simply sets the parity bit high for marked parity or low for spaced parity. This allows the

receiving device to know the state of a bit to enable the device to determine if noise is

corrupting the data or if the transmitting and receiving device clocks are out of sync.

WHAT IS RS –232C

RS-232 (ANSI/EIA-232 Standard) is the serial connection found on IBM-compatible PCs. It is used for many purposes, such as connecting a mouse, printer, or modem, as well as industrial instrumentation. Because of improvements in line drivers and cables, applications often increase the performance of RS-232 beyond the distance and speed listed in the standard. RS-232 is limited to point-to-point connections between PC serial ports and devices. RS-232 hardware can be used for serial communication up to distances of 50 feet .

DB-9 pin connector

1 2 3 4 5

6 7 8 9

(Out of computer and exposed end of cable)

Pin Functions:

Data: TxD on pin 3, RxD on pin 2

Handshake: RTS on pin 7, CTS on pin 8, DSR on pin 6,

CD on pin 1, DTR on pin 4

Common: Common pin 5(ground)

Other: RI on pin 9

The method used by RS-232 for communication allows for a simple connection of three lines: Tx, Rx, and Ground. The three essential signals for 2 way RS-232Communications are these:TXD: carries data from DTE to the DCE.RXD: carries data from DCE to the DTESG: signal groundConnection Diagram:

Figure.: Interfacing to MCU RS 232

SFRs Used for Serial Communication:SCON:

TMOD:

T1:

CONNECTIONS IN MAX 232:

If you wanted to do a general RS-232 connection, you could take a bunch of long

wires and solder them directly to the electronic circuits of the equipment you are using,

but this tends to make a big mess and often those solder connections tend to break and

other problems can develop. To deal with these issues, and to make it easier to setup or

take down equipment, some standard connectors have been developed that is commonly

found on most equipment using the RS-232 standards.

These connectors come in two forms: A male and a female connector. The female

connector has holes that allow the pins on the male end to be inserted into the connector.

This is a female "DB-9" connector (properly known as DE9F):

Female Connector

The female DB-9 connector is typically used as the "plug" that goes into a typical PC. If

you see one of these on the back of your computer, it is likely not to be used for serial

communication, but rather for things like early VGA or CGA monitors (not SVGA) or

for some special control/joystick equipment.

And this is a male "DB-9" connector (properly known as DE9M):

Male Connector

This is the connector that you are more likely to see for serial communications on a

"generic" PC. Often you will see two of them side by side (for COM1 and COM2).

Special equipment that you might communicate with would have either connector, or

even one of the DB-25 connectors listed below.

The wiring of RS-232 devices involves first identifying the actual pins that are being

used. Here is how a female DB-9 connector is numbered:

Figure.: Front View

If the numbers are hard to read, it starts at the top-right corner as "1", and goes left until

the end of the row and then starts again as pin 6 on the next row until you get to pin 9 on

the bottom-left pin. "Top" is defined as the row with 5 pins.

The male connector (like what you have on your PC) is simply this same order, but

reversed from right to left.

Here each pin is usually defined as:

9-pin 25-pin pin definition

1 8 DCD (Data Carrier Detect)

2 3 RX (Receive Data)

3 2 TX (Transmit Data)

4 20 DTR (Data Terminal Ready)

5 7 GND (Signal Ground)

6 6 DSR (Data Set Ready)

7 4 RTS (Request To Send)

8 5 CTS (Clear To Send))

9 22 RI (Ring Indicator)

Pin Definition of Connectors

One thing to keep in mind when discussing these pins and their meaning is that they are

very closely tied together with modems and modem protocols. Often you don't have a

modem attached in the loop, but you still treat the equipment as if it were a modem on a

theoretical level.

MAX232:

Max 232 is a communications device used mainly for serial commands to and from a

flash ROM.The MAX232 is an integrated circuit that converts signals from an RS-232

serial port to signals suitable for use in TTL compatible digital logic circuits. The

MAX232 is a dual driver/receiver and typically converts the RX, TX, CTS and RTS

signals. The drivers provide RS-232 voltage level outputs (approx. ± 7.5 V) from a single

+ 5 V supply via on-chip charge pumps and external capacitors. This makes it useful for

implementing RS-232 in devices that otherwise do not need any voltages outside the 0 V

to + 5 V range, as power supply design does not need to be made more complicated just

for driving the RS-232 in this case.

The receivers reduce RS-232 inputs (which may be as high as ± 25 V), to standard 5 V

TTL levels. These receivers have a typical threshold of 1.3 V, and a typical hysteresis of

0.5 V.

The later MAX232A is backwards compatible with the original MAX232 but may

operate at higher baud rates and can use smaller external capacitors – 0.1 μF in place of

the 1.0 μF capacitors used with the original device.

The newer MAX3232 is also backwards compatible, but operates at a broader voltage

range, from 3 to 5.5V.

Voltage levels

It is helpful to understand what occurs to the voltage levels. When a MAX232 IC

receives a TTL level to convert, it changes a TTL Logic 0 to between +3 and +15V, and

changes TTL Logic 1 to between -3 to -15V, and vice versa for converting from RS232

to TTL. This can be confusing when you realize that the RS232 Data Transmission

voltages at a certain logic state are opposite from the RS232 Control Line voltages at the

same logic state. To clarify the matter, see the table below. For more information see RS-

232 Voltage Levels.

RS232 Line Type & Logic LevelRS232

Voltage

TTL Voltage to/from

MAX232

Data Transmission (Rx/Tx) Logic 0 +3V to +15V 0V

Data Transmission (Rx/Tx) Logic 1 -3V to -15V 5V

Control Signals (RTS/CTS/DTR/DSR)

Logic 0-3V to -15V 5V

Control Signals (RTS/CTS/DTR/DSR)

Logic 1+3V to +15V 0V

Standard serial interfacing of microcontroller (TTL) with PC or any  RS232C Standard

device , requires TTL to RS232 Level converter . A MAX232 is used for this purpose. It

provides 2-channel RS232C port and requires external 10uF capacitors. The driver

requires  a single supply of +5V .

7.7 LCD (Liquid Cristal Display)

A liquid crystal display (LCD) is a thin, flat display device made up of any number of

color or monochrome pixels arrayed in front of a light source or reflector. Each pixel

consists of a column of liquid crystal molecules suspended between two transparent

electrodes, and two polarizing filters, the axes of polarity of which are perpendicular to

each other. Without the liquid crystals between them, light passing through one would be

Figure 13:MAX 232 Pin Diagram

Figure 14:Internal Diagram

blocked by the other. The liquid crystal twists the polarization of light entering one filter

to allow it to pass through the other.

A program must interact with the outside world using input and output devices that

communicate directly with a human being. One of the most common devices attached to

an controller is an LCD display. Some of the most common LCDs connected to the

contollers are 16X1, 16x2 and 20x2 displays. This means 16 characters per line by 1 line

16 characters per line by 2 lines and 20 characters per line by 2 lines, respectively.

Many microcontroller devices use 'smart LCD' displays to output visual information.

LCD displays designed around LCD NT-C1611 module, are inexpensive, easy to use,

and it is even possible to produce a readout using the 5X7 dots plus cursor of the display.

They have a standard ASCII set of characters and mathematical symbols. For an 8-bit

data bus, the display requires a +5V supply plus 10 I/O lines (RS RW D7 D6 D5 D4 D3

D2 D1 D0). For a 4-bit data bus it only requires the supply lines plus 6 extra lines(RS

RW D7 D6 D5 D4). When the LCD display is not enabled, data lines are tri-state and

they do not interfere with the operation of the microcontroller.

Features:

(1) Interface with either 4-bit or 8-bit microprocessor.

(2) Display data RAM

(3) 80x8 bits (80 characters).

(4) Character generator ROM

(5). 160 different 5 7 dot-matrix character patterns.

(6). Character generator RAM

(7) 8 different user programmed 5 7 dot-matrix patterns.

(8).Display data RAM and character generator RAM may be

Accessed by the microprocessor.

(9) Numerous instructions

(10) .Clear Display, Cursor Home, Display ON/OFF, Cursor ON/OFF,

Blink Character, Cursor Shift, Display Shift.

(11). Built-in reset circuit is triggered at power ON.

(12). Built-in oscillator.

available. Line lengths of

8, 16,

20, 24,

32 and

40

charact

ers are

all

standar

d, in

one,

two

Description Of 16x2:

This is the first interfacing example for the Parallel Port. We will start with something

simple. This example doesn't use the Bi-directional feature found on newer ports, thus it

should work with most, if no all Parallel Ports. It however doesn't show the use of the

Status Port as an input. So what are we interfacing? A 16 Character x 2 Line LCD

Module to the Parallel Port. These LCD Modules are very common these days, and are

quite simple to work with, as all the logic required to run them is on board.

Schematic Diagram:

o Above is the quite simple schematic. The LCD

panel's Enable and Register Select is connected to the Control Port. The

Control Port is an open collector / open drain output. While most Parallel

Ports have internal pull-up resistors, there are a few which don't. Therefore

by incorporating the two 10K external pull up resistors, the circuit is more

portable for a wider range of computers, some of which may have no

internal pull up resistors.

o We make no effort to place the Data bus into reverse direction. Therefore

we hard wire the R/W line of the LCD panel, into write mode. This will

cause no bus conflicts on the data lines. As a result we cannot read back

the LCD's internal Busy Flag which tells us if the LCD has accepted and

finished processing the last instruction. This problem is overcome by

inserting known delays into our program.

o The 10k Potentiometer controls the contrast of the LCD panel. Nothing

fancy here. As with all the examples, I've left the power supply out. You

can use a bench power supply set to 5v or use a onboard +5 regulator.

Remember a few de-coupling capacitors, especially if you have trouble

with the circuit working properly.

The 2 line x 16 character LCD modules are available from a wide range of

manufacturers and should all be compatible with the HD44780. The one I

used to test this circuit was a Power tip PC-1602F and an old Philips

LTN211F-10 which was extracted from a Poker Machine! The diagram to

the right, shows the pin numbers for these devices. When viewed from the

front, the left pin is pin 14 and the right pin is pin 1

.

16 x 2 Alphanumeric LCD Module Features

Intelligent, with built-in Hitachi HD44780 compatible LCD controller and RAM

providing simple interfacing

61 x 15.8 mm viewing area

5 x 7 dot matrix format for 2.96 x 5.56 mm characters, plus cursor line

Can display 224 different symbols

Low power consumption (1 mA typical)

Powerful command set and user-produced characters

TTL and CMOS compatible

Connector for standard 0.1-pitch pin headers

16 x 2 Alphanumeric LCD Module Specifications

Pin Symbol Level Function

1 VSS - Power, GND

2 VDD - Power, 5V

3 Vo - Power, for LCD Drive

4 RS H/L

Register Select Signal

H: Data Input

L: Instruction Input

5 R/W H/LH: Data Read (LCD->MPU)

L: Data Write (MPU->LCD)

6 E H,H->L Enable

7-14 DB0-DB7 H/L Data Bus; Software selectable 4- or 8-bit mode

15 NC - NOT CONNECTED

16 NC - NOT CONNECTED

FEATURES

• 5 x 8 dots with cursor

• Built-in controller (KS 0066 or Equivalent)

• + 5V power supply (Also available for + 3V)

• 1/16 duty cycle

• B/L to be driven by pin 1, pin 2 or pin 15, pin 16 or A.K (LED)

• N.V. optional for + 3V power supply

CONTROL LINES:

EN: Line is called "Enable." This control line is used to tell the LCD that you are

sending it data. To send data to the LCD, your program should make sure this line is low

(0) and then set the other two control lines and/or put data on the data bus. When the

other lines are completely ready, bring EN high (1) and wait for the minimum amount of

time required by the LCD datasheet (this varies from LCD to LCD), and end by bringing

it low (0) again.

RS:

Line is the "Register Select" line. When RS is low (0), the data is to be treated as

a command or special instruction (such as clear screen, position cursor, etc.). When RS is

high (1), the data being sent is text data which should be displayed on the screen. For

example, to display the letter "T" on the screen you would set RS high.

RW:

Line is the "Read/Write" control line. When RW is low (0), the information on the

data bus is being written to the LCD. When RW is high (1), the program is effectively

querying (or reading) the LCD. Only one instruction ("Get LCD status") is a read

command. All others are write commands, so RW will almost always be low.

Finally, the data bus consists of 4 or 8 lines (depending on the mode of operation

selected by the user). In the case of an 8-bit data bus, the lines are referred to as DB0,

DB1, DB2, DB3, DB4, DB5, DB6, and DB7.

Logic status on control lines:

• E - 0 Access to LCD disabled

- 1 Access to LCD enabled

• R/W - 0 Writing data to LCD

- 1 Reading data from LCD

• RS - 0 Instructions

- 1 Character

Writing data to the LCD:

1) Set R/W bit to low

2) Set RS bit to logic 0 or 1 (instruction or character)

3) Set data to data lines (if it is writing)

4) Set E line to high

5) Set E line to low

Read data from data lines (if it is reading) on LCD:

1) Set R/W bit to high

2) Set RS bit to logic 0 or 1 (instruction or character)

3) Set data to data lines (if it is writing)

4) Set E line to high

5) Set E line to low

6.4 KEYPAD

Keyboards and LCDs are the most widely used input/output devices of the

microcontroller, and a basic understanding of them is essential. In this section, we first

discuss keyboard fundamentals, along with key press and key detection mechanisms,

Then we show how a keyboard is interfaced to an microcontroller.

Scanning and identifying the key

 Figure shows a 4*4 matrix connected to two ports. The rows are connected to an output

port and the columns are connected to an input port. If no key has been pressed, reading

the input port will yield 1s for all columns since they are all connected to high (Vcc) If all

the rows are grounded and a key is pressed, one of the columns will have 0 since the key

pressed provides the path to ground. It is the function of the micro controller to scan the

keyboard continuously to detect and identify the key pressed. How it is done is explained

next.

Figure 22:4x 4 key pads

Grounding rows and reading columns

 To detect a pressed key, the micro controller grounds all rows by providing 0 to the

output latch, and then it reads the columns. If the data read from the columns is D3-

D0=1111, no key has been pressed and the process continues until a key press is detected.

However, if one of the column bits has a zero, this means that a key press has occurred.

For example, if D3-D0=1101, this means that a key in the D1 column has been pressed.

After a key press is detected, the micro controller will go through the process of

identifying the key. Starting with the top row, the micro controller grounds it by

providing a low to row D0 only; then it reads the columns. If the data read is all1s, no key

in that row is activated and the process is moved to the next row. It grounds the next row,

reads the columns, and checks for any zero. This process continues until the row is

identified. After identification of the row in which the key has been pressed, the next task

is to find out which column the pressed key belongs to. This should be easy since the

microcontroller knows at any time which row and column are being accessed.

Assembly language program for detection and identification of key activation is given

below. In this program, it is assumed that P1 and P2 are initialized as output and input,

respectively. Program13.1 goes through the following four major stages:

1. To make sure that the preceding key has been released, 0s are output to all rows at

once, and the columns are read and checked repeatedly until all the columns are high.

When all columns are found to be high, the program waits for a short amount of time

before it goes to the next stage of waiting for a key to be pressed.

2)  To see if any key is pressed, the columns are scanned over and over in an infinite loop

until one of them has a 0 on it. Remember that the output latches connected to rows still

have their initial zeros (provided in stage 1), making them grounded. After the key press

detection, it waits 20ms for the bounce and then scans the columns again. This serves two

functions: (a) it ensures that the first key press detection was not an erroneous one due to

spike noise, and(b) the 20ms delay prevents the same key press from being interpreted as

a multiple key press. If after the 20-ms delay the key is still pressed, it goes to the next

stage to detect which row it belongs to; otherwise, it goes back into the loop to detect a

real key press        

3)   To detect which row the key press belongs to, it grounds one row at a time, reading

the columns each time. If it finds that all columns are high, this means that the key press

cannot belong to that row; therefore, it grounds the next row and continues until it finds

the row the key press belongs to. Upon finding the row that the key press belongs to, it

sets up the starting address for the look-up table holding the scan codes (or the ASCII

value) for that row and goes to the next stage to identify the key.

4)   To identify the key press, it rotates the column bits, one bit at a time, into the carry

flag and checks to see if it is low. Upon finding the zero, it pulls out the ASCII code for

that key from the look-up table; Otherwise, it increments the pointer to point to the next

element of the look-up table.

While the key press detection is standard for all keyboards, the process for determining

which key is pressed varies. The look-up table method shown in program can be

modified to work with any matrix up to 8*8.

There are IC chips such as National Semiconductors MM74C923 that incorporate

keyboard scanning and decoding all in one chip. Such chips use combinations of counters

and logic gates (No micro controller).

7. SOFTWARE COMPONENTS

7.1 Embedded ’c’7.2 Keil softwareInstalling the Keil software on a Windows PC

Insert the CD-ROM in your computer’s CD drive On most computers, the CD will “auto run”, and you will see the Keil installation

menu. If the menu does not appear, manually double click on the Setup icon, in

the root directory: you will then see the Keil menu.

On the Keil menu, please select “Install Evaluation Software”. (You will not

require a license number to install this software).

Follow the installation instructions as they appear.

Loading the Projects

The example projects for this book are NOT loaded automatically when you install the

Keil compiler.

These files are stored on the CD in a directory “/Pont”. The files are arranged by chapter:

for example, the project discussed in Chapter 3 is in the directory “/Pont/Ch03_00-

Hello”.

Rather than using the projects on the CD (where changes cannot be saved), please copy the files from CD onto an appropriate directory on your hard disk. Note: you will need to change the file properties after copying: file transferred from the CD will be ‘read only’.Configuring the SimulatorOpen the Keil Vision2go to Project – Open Project and browse for Hello in Ch03_00 in Pont and open it.

Go to Project – Select Device for Target ‘Target1’

Select 8052(all variants) and click OK

Now we need to check the oscillator frequency:Go to project – Options for Target ‘Target1’

Make sure that the oscillator frequency is 12MHz.

Building the TargetBuild the target as illustrated in the figure below

Running the SimulationHaving successfully built the target, we are now ready to start the debug session and run the simulator.First start a debug session

The flashing LED we will view will be connected to Port 1. We therefore want to observe the activity on this port

To ensure that the port activity is visible, we need to start the ‘periodic window update’ flag

Go to Debug - Go

While the simulation is running, view the performance analyzer to check the delay durations.

Go to Debug – Performance Analyzer and click on it

Double click on DELAY_LOOP_Wait in Function Symbols: and click Define button

8. SOURCE CODE9. CONCLUSION10. FUTUREASPECTS

11. BIBLIOGRAPHY

The 8051 Micro controller and Embedded Systems

Muhammad Ali Mazidi Janice Gillispie Mazidi

The 8051 Micro controller Architecture, Programming & Applications

Kenneth J. Ayala

Fundamentals of Micro processors and Micro computers

B. Ram

Micro processor Architecture, Programming & Applications

Ramesh S. Gaonkar

Electronic Components

D.V.Prasad

References on the Web:www.national.comwww.atmel.comwww.microsoftsearch.com

www.geocities.com