cReComp : Automated Design Tool for ROS-Compliant FPGA Component
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Transcript of cReComp : Automated Design Tool for ROS-Compliant FPGA Component
cReComp : Automated Design Tool for ROS-Compliant FPGA Component
Kazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi YokotaGraduate School of Engineering, Utsunomiya University in Japan
September, 22 MCSoC 2016 @Lyon, France 1
Outline1. Introduction• ROS & ROS-compliant FPGA component
2. Proposal of cReComp3. Development using cReComp4. Evaluation : Development productivity5. Conclusion
September, 22 MCSoC 2016 @Lyon, France 2
Outline1. Introduction2. Proposal of cReComp3. Development using cReComp4. Evaluation : Development productivity5. Conclusion
September, 22 MCSoC 2016 @Lyon, France 3
Background 1/2• Requirements for autonomous mobile robots• Wireless communication and Battery operation• Robots should operate at low power and show high performance!
• FPGA* contributes to speeding up processing in various fields• e.g.) image processing, networking packet routing• Power efficiency of FPGA is much better than CPU, micro controller [1]
• We employed FPGA to realize a robot which has high performance and needs low power
September, 22 MCSoC 2016 @Lyon, France 4
[1] Li, F., Lin, Y., He, L., and Cong, J., “Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics,” In Proceedings of the 2004 ACM/SIGDA 12th
international symposium on Field programmable gate arrays (pp. 42-50). ACM, 2004.
* FPGA : Field Programmable Gate Array
Background 2/2• Development costs of FPGA are very high!• It is not easy and hard for anyone to implement applications on FPGA• Re-usability of FPGA module is very low• Component oriented development on FPGA• That means, FPGA application is implemented a component
September, 22 MCSoC 2016 @Lyon, France 5
FPGAcomponent
Re-usable
ROS (Robot Operating System)• ROS is a software platform for component-oriented
development of robotic application software • Build tools +application tool + communication library• Communication model : Publish/Subscribe messaging
September, 22 MCSoC 2016 @Lyon, France 6
Any component can be added to or removed from robot system easily, since components are connected loosely
Component
Publish Subscribe
SubscriberA publisher can send messages to any topic, and the messages are queued in the topic.
PublisherA publisher can send messages to any topic, and the messages are queued in the topic.
Topic
Service invocationMassage (data)
Component
ROS-compliant FPGA componentSeptember, 22 MCSoC 2016 @Lyon, France 7
Circuit(User logic)
Software (CPU)
Software interface Hardware interface
Hardware (FPGA)
ROSApplication
FIFO
FIFO
ROS component
ROScomponent
Topic
Topic
Component oriented interface
• ROS-compliant FPGA component is…a technology to realize an application level interface for FPGA
• User logic : target application on FPGA• Target platform : Programmable SoC (CPU+ FPGA)
FPGAapplication(User logic)
Software (CPU)
Software interface Hardware interface
Hardware (FPGA)
ROSApplication
FIFO
FIFO
ROS component
ROScomponent
Topic
Topic
Component oriented interface
The biggest problem in conventional development for componentization
• ROS-compliant FPGA component needs an interface for communication between HW and SW
• Problem : High development cost!!
September, 22 MCSoC 2016 @Lyon, France 8
System-wideverification
Design of interfacebetween HW/SW(Hardware : HDL)
Implementationof hardware(HDL)
Design of interfacebetween HW/SW(Software : C++)
SimulationDebug
Verification
SimulationDebug
VerificationDebug
Verification
System-wideverification
4 phases in the development of componentization
Development ofuser logic
Implementation of an interface between hardware and software
Implementation as a ROS component
Adding ROS functionsto the interface(C++)
Implementationof hardware(HDL)
SimulationDebug
Verification
Development ofuser logic
Design of interfacebetween HW/SW(Hardware : HDL)
Design of interfacebetween HW/SW(Software : C++)
SimulationDebug
Verification
Implementation of an interface between hardware and software
DebugVerification
Implementation as a ROS component
Adding ROS functionsto the interface(C++)
System-wideverification
System-wideverification
Objective• For improvement of re-usability and productivity
of FPGA application• We propose cReComp which improves productivity of ROS-
compliant FPGA component
September, 22 MCSoC 2016 @Lyon, France 9
Open source software
User(Robotic developer
or FPGA developer)
Re-usable!&
Happy!
ROS-compliant FPGA component
Developer
By using cReComp,I can develop easily!
Outline1. Introduction2. Proposal of cReComp3. Development using cReComp4. Evaluation : Development productivity5. Conclusion
September, 22 MCSoC 2016 @Lyon, France 10
cReComp overview• cReComp : creator for Reconfigurable Component
• cReComp generates a component-oriented interface• The interface enables communication between HW and SW• The tool gives an abstract of user logic (hardware) in application level
• The interface model is described by 2 formats• Python format• scrp format• scrp : specification for cReComp. This is my original format for cReComp.
September, 22 MCSoC 2016 @Lyon, France 11
User logic supported by cReComp• User logic description types are
different depending on usage of FPGA• For interface of sensor, motor and so on → RTL• RTL : Register Transfer Level• For accelerator of processing such as processing → HLS• HLS : High Level Synthesis
• These 2 types of user logic are able to be input to cReComp!
• Any module is OK!
September, 22 MCSoC 2016 @Lyon, France 12
Interface generation model on cReCompSeptember, 22 MCSoC 2016 @Lyon, France 13
FIFO CtrlROS APP
Verilog-HDL
FIFO
FIFO
ConfigurationfilecReComp
User logic
Output
ROS-compliant FPGA component
C++
Communication
HardwareSoftware
Described by User
FILE Input• Input• User logic (Verilog-HDL) • Configuration file• scrp (specification for cReComp )• Python
• Output• Component-oriented interface• Circuit for communication control (Verilog-HDL)• ROS Application (C++)
• ROS message file
• Configuration contents• Bit width of FIFO• Number of receiving data from input FIFO
(HW→SW)• Number of sending data from input FIFO
(SW→HW)• Condition to receive/send• Assignment of user logic
Therefore…September, 22 MCSoC 2016 @Lyon, France 14
Configurationfile
scrp or pythoncReComp
Describe Input Output
ROS-compliant FPGA component
User logic
Developer need not design the interface for communication between HW and SW.
Only two files
Outline1. Introduction2. Proposal of cReComp3. Development using cReComp4. Evaluation : Development productivity5. Conclusion
September, 22 MCSoC 2016 @Lyon, France 15
Case study: control circuit of ultra sonic distance sensor(user logic described by RTL)
September, 22 MCSoC 2016 @Lyon, France 16
Ultra sonic distance sensor(Parallax Inc. PING)
Input : req
sonic_sensor.v(RTL)
Output : out_data01 11532 Sensor values
If “req” is asserted, sensor values are output on “out_data”
32
count clocksuntil pulse returns
User logic
1. Template generationSeptember, 22 MCSoC 2016 @Lyon, France 17
Templategeneration
crecomp -s sensor_ctl.scrp -u sonic_sensor.v
Descriptionfor
configuration
Componentization [3] Shinaya Takamaeda, “A High-level Hardware Design Environment in Python ,” Technical report of IEICE, RECONF2015-36, pp.21-26, 2015.
• The description is generated automatically by cReComp.
• User logic is analyzed by veriloggen [3]
• You may specify user logic before cReComp generates a template file.
• Input file should be the top module of your user logic.
2. Description for configuration : 1 / 2September, 22 MCSoC 2016 @Lyon, France 18
Templategeneration
Descriptionfor
configuration
Componentization
Communication setting
FIFO bit width : 32 bitsReceive data (SW→HW) : one timeSend data (HW→SW) : one time“req” is connected to input FIFO“out_data” is connected to output FIFO
2. Description for configuration : 2 / 2September, 22 MCSoC 2016 @Lyon, France 19
Templategeneration
Descriptionfor
configuration
Componentization
component_name "sensor_ctl"{
in_out_signals{
input 1 clk,input 1 rst,inout 1 sig
}
option_signals{
wire 1 finish,wire 1 busy,reg 31 dummy,reg 1 req,wire 32 data_out
}
communication xillybus{
fifo_width 32,rcv_cycle 1,snd_cycle 1,condition "busy == 0 && finish",rcv = req,rcv = dummy,snd = data_out
}userlogic_path "sonic_sensor.v" instance_name "uut"{
input 1 clk = clk,input 1 rst = rst,input 1 req = req,output 1 busy = busy,inout 1 sig = sig,output 1 finish = finish,output 32 out_data = data_out
}generate_ros_package
}
Very few code!
3. ComponentizationSeptember, 22 MCSoC 2016 @Lyon, France 20
Templategeneration crecomp -b sensor.ctl.scrp
sensor_ctl/+--hardware/
+--sensor_ctl.v+--sonic_sensor.v
+--software/+--lib_cpp.h+--Makefile+--sensor_ctl.cpp
+----ros_package/
ConfigureDescription
Componentization
Execute a command to generate a component
such directory is generated
sensor_ctl/+--inculude/+--msg/
+--sensor_ctl.msg+--src/
+--sensor_ctl.cpp+--CMakeLists.txt+--package.xml
The generated component in the design caseSeptember, 22 MCSoC 2016 @Lyon, France 21
FIFO32-bits
out_data
req
32
ROSApplication
(C++)Input
Output
Sensorreq
32
finish
out_data
busy
InterfaceCircuit
(Verilog-HDL)
sig
sig
sonic_sensor(user logic)
ROScomponent
Topic
Topic
ROScomponent
msg
msg
cReComp generates a ROS message file automaticallyIn ROS, you can define data structure in *.msg file
User logic on FPGA can be access from other ROS component by publish/subscribe!
ROS-compliant FPGA component
cReComp translates user logic signal
into ROS message
Outline1. Introduction2. Proposal of cReComp3. Development using cReComp4. Evaluation : Development productivity5. Conclusion
September, 22 MCSoC 2016 @Lyon, France 22
Evaluation : development productivity • We conducted an experiment in February, 2016• Theme : Effect on the productivity by using scrp description
• Subjects’ experience in HW/SW co-design• FPGA : from nothing to 3 years• C++ : from 1 to 6 years• Linux : from 1 to 3 years
• User logic : control circuit of sonic distance sensor• The user logic is the same as design case
September, 22 MCSoC 2016 @Lyon, France 23
Details and results of the experiment
• Evaluation methods• The difficulty rated in five stages5 : Very easy ~ 1: Very difficult• The average of elapsed time• The rating of b) was 3.7 and b) took 17 minutes.• maximum : 5, minimum : 2
September, 22 MCSoC 2016 @Lyon, France 24
Evaluation environment• FPGA board : Zedboard Avnet• Programmable SoC : Zynq-7020 Xilinx• OS:xillinux-1.3(Ubuntu12.04)• ROS:groovy• Sensor : PING Ultrasonic Distance Sensor Parallax
a) Installation of cReComp
b) Description of scrp file
c) Componentization
Experiment flow
The experiment shows…• All the subjects were able to finish their componentization in less than one hour.
September, 22 MCSoC 2016 @Lyon, France 25
Development Without cReComp(me : Kazushi Yamashia)
With cReComp(average of the subjects)
Described Lines About 300(hardware + software)
27(scrp)
Described Characters About 6000(hardware + software)
385(scrp)
Time 1 hour 46 minutes 17 minutes
Comparison on implementation of component-oriented interface
cReComp contributes to improve the productivity ofROS-compliant FPGA componentversion of cReComp was not the latest when experiment was conducted. (The latest is 1.4.4)
My experience; FPGA : 3years, C++ : 6 years, Linux : from 3 years
Outline1. Introduction2. Proposal of cReComp3. Development using cReComp4. Evaluation : Development productivity5. Conclusion
September, 22 MCSoC 2016 @Lyon, France 26
ConclusionWe proposed cReComp for easy integration of FPGA into robot system.• The experiment was conducted to evaluate development
productivity• All the subjects were able to finish componentization of experiment less
than one hour.• cReComp contributes to improve the productivity of ROS-compliant FPGA
component
Future work• We are going to conduct further experiments in October• Using the latest version of cReComp
September, 22 MCSoC 2016 @Lyon, France 27
Thank you for listening!• Acknowledgment• This research and development work was supported by the
MIC/SCOPE#152103014.• Contact• Email : [email protected]• This slide is published at slideshare after presentation
my account : kazuyamashi
September, 22 MCSoC 2016 @Lyon, France 28
cReComp is released as open source software!!git clone https://github.com/kazuyamashi/cReComp.gitpip install crecomp
cReComp : Automated Design Tool for ROS-Compliant FPGA Component
Kazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi YokotaGraduate School of Engineering, Utsunomiya University in Japan
September, 22 MCSoC 2016 @Lyon, France 29