Creating Differentiated ASICs With Quality IP · 2019-10-11 · CONFIDENTIAL | Lisa Minwell SR...

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CONFIDENTIAL | Lisa Minwell SR Director IP Marketing Creating Differentiated ASICs With Quality IP GSA IP WG MEETING – IP INTEGRATION WITH ASIC TECHNOLOGY PANEL DISCUSSION April 16, 2015

Transcript of Creating Differentiated ASICs With Quality IP · 2019-10-11 · CONFIDENTIAL | Lisa Minwell SR...

Page 1: Creating Differentiated ASICs With Quality IP · 2019-10-11 · CONFIDENTIAL | Lisa Minwell SR Director IP Marketing Creating Differentiated ASICs With Quality IP GSA IP WG MEETING

CONFIDENTIAL |

Lisa Minwell SR Director IP Marketing

Creating Differentiated ASICs With Quality IP

GSA IP WG MEETING – IP INTEGRATION WITH ASIC TECHNOLOGY PANEL DISCUSSION

April 16, 2015

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Who is eSilicon?

• Independent Provider of Semiconductor Design and Manufacturing Solutions (SDMS) • Delivering custom ICs and custom IP

via a fast, flexible, lower-risk, automated path to volume production

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• Networking and Communication • Large complex chips • Integration of MANY SerDes on-chip • Sophisticated IP • BIST, ECC • Large quantity of memory on and off-chip • Complex packaging – 2.5D

• Consumer (IoT) • Low-power and low-cost solutions • Chip-level differentiation is at the heart of IoT competitiveness

• Technology and IP selection • Optimized IP provides differentiation

Market-Driven Solutions

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IP Factory

eSilicon Combines an “IP Factory” With An ASIC Mentality

• No shortage of tools

• Lots of engineering

• Processes

• High-quality IP

IP Shop

• May bring something unique

• Boutique IP

• Small team, small resources

• May not have all processes in place to build high quality IP

• Cost of re-spin is HUGE

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Design For Yield Bridging the Gap Between Designer and Foundry

Need to provide fully validated IP to their customers

Use model is critical because it is quite common for IP to be “abused” in a way or mode that the IP vendor never expected

Need standardized quality metric The “clean” IP can then be used

with more confidence Power Clock domains Testability Physical

IP Providers

Addressing co-optimization issues during the design phase means reaching out to all the ecosystem players

Improving the design both to achieve higher yield and to increase the performance of the devices that can be achieved for a given process

Designer Foundry

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• There’s lots of good IP out there... Does it work together and give you the results you are looking for?

• Visibility into the PPA, silicon verification

• Need - Risk reduction & improving visibility and transparency to the end result

• Know what your getting ahead of time, reduce risk, improve visibility, get what you expect when you put it together

• Need services after the sale - Block level optimization

• eSilicon has developed cloud-based, big data analytics as internal tools to reduce risk and improve the usability of the IP

Risk Reduction – Improved Visibility and Transparency

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Enabling Your Silicon Success™