Cracking Explained

7/25/2019 Cracking Explained

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This article was originally published in Engineering Edge Vol. 5 Iss. 1

2016 Mentor Graphics Corporation all rights reserved

By Mohammed Amir Eleffendi, Li Yang, Pearl Agyakwa,

and Mark Johnson, Department of Electrical andElectronics Engineering, University of Nottingham, UK

egradation of the thermal

conduction path is one of

the most common failure

mechanisms of power

semiconductor packages. Typically,

solder fatigue happens due to the thermo-

mechanical stresses at the interfacing

contacts resulting from mismatched

coefcient of thermal expansionsbetween different materials (which

make up the heat ow path) and causes

cracking. Thermal transient measurement

using Mentor Graphics' T3Sterhardware

is a common characterization method

for heat conduction path in power

semiconductor packages.

The heat ow path in this type of test can

be represented by an equivalent electrical

Resistance-Capacitance Cauer-type

model. T3Ster uses thermal impedance via

structure functions as a non-destructive

evaluation technique to detect structuraldefects in the heat conduction path.

In this work, junction-to-case thermal

resistance Rthjc

and cracked area, from

structure functions, are compared to the

cracked and unattached area estimated by

Scanning Acoustic Microscopy (SAM) for

a conventional 1.2 kV/200 A IGBT power

module that is actively power-cycled to

degrade the solder at the substrate-base

plate interface. SAM imaging was performed

at regular intervals for multiple stages

of the power cycling test to observe the

gradual degradation of the solder layer. The

Power Module under test (see Figure. 1)

was an off-the-shelf 3-phase IGBT module

consisting of three substrate tiles mounted

on a copper baseplate with two IGBT chips

and two freestanding diodes on each [1].

D

Quantication of Cracked Areas in the Thermal Path ofHigh-power Multi-chip Modules using MicReD PowerTester1500A

The IGBT module was mounted onto acold plate with a 25 m thick Kapton lm

used as an interfacing material between

the cold plate and the baseplate. The

purpose of this lm was to increase the

case-to-ambient thermal resistance in

order to achieve a temperature swing

at the substrate-case interface and so

accelerate the degradation of the substrate

mount-down solder layer compared to

other failure mechanisms. All IGBTs were

biased with a gate-emitter voltage VGE

= 15 V such that the cycling current IC

as well as the measurement current IM

were shared between the three legs of the

module. The collectoremitter voltage VCE

is a global measurement across the whole

module and therefore, it represents an

average measurement of the three legs. A

Figure 1.Layout of the Power Module under test (left) with the MicReD Industrial 1500A

Power Tester Unit (that contains a T3Ster) used in the Power Cycling Test (right)

Cracking Explained

calibration curve TJ =f(VCE) at a constantmeasurement current of IM = 200 mA was

used to calculate junction temperature TJ.

The cycling current IC was regulated by

the Power Tester to preserve a constant

TJ=120 K with T

Jmax= 140C and

TJmin = 20C as estimated from VCE with

the water temperature maintained at 20C.

The heating time and cooling time were

xed at 50 s, and 60 s respectively. This

achieved a T of 70 K at the substrate

with T max = 90C and T min = 20C. The

test started with an initial cycling current

IC = 236 A which resulted in a power

dissipation PD = 704 W. As the thermal

resistance increased during the test due

to solder fatigue, the cycling current was

regulated to keep theTJconstant. Under

these conditions, the wire-bond lift-off


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Power Electronics


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Figure 2.Scanning Acoustic Microscopy (SAM) images at different cycles during the power cycling test.

Figure 3.Estimated attached area of solder layer during the cycling test from SAM images.

Figure 4.Cumulative T3Ster structure function showing different layers of the thermal stack as number of cycles increase

mechanism is not the dominant mechanism

and the substrate mount-down solder

degrades before any wire-bond lift-off is

observed. The power cycling was paused

regularly every 1000 cycles, at which time

a thermal impedance measurement was

made of the module in situ by the 1500A

Power Tester and this resulted in a total

of 17 thermal impedance measurements

during the test.

SAM characterization was carried out

during the power cycling test using a

PVA TePla AM300. Scanning acoustic

microscopy is a non-destructive technique

that allows us to image the internal

features of a specimen and can detect

discontinuities and voids of sub-micronthickness. It creates 2D greyscale images

from the reected ultrasonic echoes.

Defects at any of the internal layers cause

discontinuity in the structure and block

the ultrasonic signal preventing it from

penetrating through the layers beneath

the defected areas. Thus, defects in the

substrate solder result in a black shadow

appearing in the C scan images taken from

the chip level (Figure 2). In this way, the C

scan images were used to obtain distinct

boundaries between the attached and

discontinuous areas. However, the exact

location of the defects within the structurecan be unclear from SAM images, and

therefore, correlative metallurgical cross-

sectioning was necessary. The power

cycling test was terminated after 17,700

cycles by which time the total junction-

to-ambient thermal resistance Rthja had

increased by 14% from its original value.

After examination, all IGBT devices were

still electrically functional. Following the

nal SAM observation, metallurgical cross-

sections were prepared and examined

under an optical microscope in order to

conrm the degradation mode.

The IGBT module was imaged in its

original state, i.e. prior to power cycling.

No cracks or voids were observed in the

internal layers at that stage (Figure 2). The

power cycling test was interrupted for

SAM imaging at 9100, 10,450, 13,350,

and 15,500 cycles. At 17,700 cycles, the

test was terminated and a nal scan was

performed. The percentage of attached

area was calculated as Attached Area (%)

= Number of White Pixels/Total Number

of Pixels. Figure 3 shows the estimated

attached area of the solder layer at different

cycle numbers during the cycling test.

At zero cycles, the attached area was

estimated to be 93%. This is because

the processing algorithm recognizes

the separation lines between different


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substrates and between copper traces

and the wire bond footprints as black

(cracked) pixels. However, this feature

does not affect the observed trends as it

is persistent in the remaining images. As

the number of cycles increases, cracking

propagates through the solder causing the

attached area to be reduced gradually until

it reaches 43% attached area after 17,700

cycles.

Figure 4 shows that a change develops

in the structure function as the number of

cycles increases. This change appears as

an increasing thermal resistance since the

curve is shifting to the right over the x-axis

with the increasing number of cycles. The

change starts at the interface between thebase-plate region and substrate where an

expansion over the x-axis can be spotted.

However, it is difcult to conclude from

this plot alone exactly where in the solder

interface region the cracking is happening.

The junction-to-case thermal resistance

Rthjc

can be measured from the structure

function at the end of the baseplate region

and before the start of the Kapton lm

region. Figure 5 shows Rthjc

as a function

of number of cycles. It can be seen that

Rthjc

stays unchanged until 8000 cycles,

and from this point onwards it increasesprogressively until the end of the test.

The total increment in Rthjc

is about 70%

from its original value which is estimated

as 0.024C/W. This increment is a result

of cracks in the solder at the substrate-

base-plate interface which is conrmed by

metallurgical cross-sectioning as shown in

gure 6.

Figure 5 also shows values of Rthjc

measured at 7000, 9000, 11,000, 15,000,

and 17,000 cycles plotted as a function

of the percentage of attached area as

estimated from the SAM images of gure2. It can be seen that as the attached

area decreases the thermal resistance

increases rapidly. It is also noted in gure 5

that the sensitivity of the structure function

for structural defects is dependent on the

location of the semiconductor chip relative

to the location of the defect. That is, it has

higher sensitivity for defects located directly

below the chip such that the defect has a

direct thermal effect on the chip, whereas

a defect located far from the chip would

result in lower sensitivity of the structure

function for that defect. That is the reason

why no change in the structure function is

seen until 35% of the substrate-case solder

layer is cracked through. Cracking of the

solder starts at the corners of the substrate

and initially this has little effect on the heat

owing from the semiconductor chips

towards the heatsink. With propagation

of the cracking towards the center of the

substrate, the heat ow is obstructed and

only then does the structure function start

to indicate the presence of a defect.

Figure 7 shows the T3Ster differential

structure function K(R) between 7000

cycles and 15,000 cycles. Each peak in

this plot indicates a new layer of material

with a different cross-sectional area.

A decrease in the amplitude of a peak

indicates a reduction in cross-sectional

area of the layer related to that peak. The

shift in the location of the peak along the

x-axis indicates a change in the thermal

resistance of this layer. Hence, the thermal

resistance of the individual layers can be

identied. In addition, the thickness can

be identied if the material properties are

known. The most signicant peak is Peak

3, which is related to the baseplate layer.

The other peaks are shown related to the

different materials heat is owing through.

The most signicant changes can be seen

in the amplitude of Peaks 2 & 3, which

are decreasing. Peak 1 and Peak 4, on

the other hand, remain at almost constant

amplitude. This decrease in the amplitude

signies a reduced cross-sectional area of

Figure 5.The change in the junction-to-case thermal resistance Rthjc during the power cycling test as

a result of solder fatigue and how it correlates to the cross sectional attached area of the layer.

Figure 6.Image of metallurgical cross-section showing the cracking

resulting from power cycling at the substrate-baseplate interface.

Figure 7.T3Ster differential structure function during the power cycle

test. Different peaks indicate different layers (as shown)

Power Electronics


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the solder layer which is at the interface

between the DBC substrate and the

baseplate. This is accompanied by an

increase in the thermal resistance of the

solder layer which is indicated by a shift in

the location of Peak 2 and Peak 3 along

the positive x-axis.

The K-value of Peak 3 (that is, the Case)

from the T3Ster differential structure

function (Figure 7) can be plotted against

the number of cycles and this is shown in

gure 8. A decrease in the K-value is clear

as the number of power cycles increases,

and is indicative of reduced cross-sectional

area. In order to reveal the relationship

between the two quantities, the cross-

sectional area estimated earlier from theSAM images was compared to the K-value

given by a differential T3Ster structure

function. This is correlated in gure 9 where

the K-value can be seen to be linearly

related to the cross-sectional area squared.

This is in agreement with theoretical

relationships we have evaluated [1] and is

an important nding of this study.

If we now look at the individual IGBTs in

our module under test, all were functional

after 17,700 power cycling tests. At this

point in the test, the SAM image showed

different levels of discontinuity beneaththe individual IGBT devices. Therefore, an

investigation was carried out to examine

whether this non-uniformity in heat ow

can be observed in the structure functions

for the individual IGBT chips in addition

to the module as a whole. For this study,

thermal paste was used as the interface

material instead of the Kapton lm used

during the power cycling test. The local

thermal impedance of each individual

IGBT in the module was measured and

the structure function was calculated.

The attached area under each individual

IGBT is estimated from the SAM imageat 17,700 cycles and these are shown

in gure 10. The IGBT devices were

numbered from 1 to 6 and the area under

each IGBT was cropped to calculate

the attached area using a MatLab

methodology [1].

The estimated percentage attached area

under each device is shown in gure

11 with values from lowest to highest

being Device 4, followed by Device 2,

then Device 3, Device 5, Device 6, and

nally Device 1. Figure 11 also shows

the cumulative structure function for the

individual IGBTs. A large difference can

be seen between the curves as a result

of the different levels of discontinuity in

the substrate to baseplate interface area

Figure 8.K value of the case region shows a steady decline over

the power cycling test indicating a decreasing cross-sectional area.

Figure 9.K value given by the differential structure function at the baseplate region it has a

linear correlation to the square of the fractional cross-sectional area of the solder layer.

Figure 10.SAM image of the cycled module at 17,700 cycles shows

different levels of delamination under the 6 IGBT devices.


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below each IGBT. The different thermal

layers can be most easily identied on the

curves related to Device 1 and Device 6

as they are the least affected by solder

fatigue. Features of the different layers

in the structure start to disappear as the

level of local delamination increases in

the other devices. Device 4 is the worst

affected by cracking and its different

layers' features cannot be distinguished.

Hence, we concluded that the junction-

to-ambient thermal resistance Rthja

may be

directly compared with the percentage of

attached area below the individual IGBTs.

Figure 12 shows Rthja

of the individual

IGBTs as a function of attached area of

the solder under each IGBT. Similar to theresult shown in gure 5, it can be seen

that the Rthja can be correlated to the

attached area. If we also produce and

plot K-value against the square of the

percentage of attached area, gure 13

shows yet again a clear linear correlation

can be deduced with K-value being a

function of the square of the fractional

attached area of each individual IGBT.

Conclusions

An evaluation using MicReD T3Ster

structure functions within a Mentor

Graphics 1500A Power Tester as a non-destructive testing tool for examining

the integrity of the heat ow path in

high power multi-chip semiconductor

modules under repeated cycling has

been carried out. A 1.2 kV/200 A IGBT

power module (with six IGBTs) was power

cycled to activate the solder fatigue

failure mechanism at the substrate

baseplate interface. Thermal impedance

measurements and SAM imaging were

performed at regular intervals during the

power cycling test. From this data, the

thermal structure function was calculated

and the cracked area in the solder layerwas estimated. Failure analysis by cross-

sectioning conrmed the location of the

discontinuity at the substratebaseplate

solder layer. A clear correlation was found

in this study between the change in the

junction-to-case thermal resistance Rthjc

estimated from the structure function and

the remaining attached area of the solder

layer calculated from SAM images. It was

shown that the K-value obtained from the

differential structure function was linearly

related to the square of the percentage

of attached area estimated from SAM

images. Similar results were found for the

structure function calculated from the local

measurement of the thermal impedances

of individual IGBT devices in the module.

Hence, the MicReD 1500A Power Tester

and its structure functions can be used

to estimate degradation in specic layers

of a power module and individual devices

non-destructively. Consequently, it can

be used as a primary inspection tool to

rapidly test the integrity of heat ow path

in power modules before deciding whether

further, but potentially time-consuming

alternatives like SAM, or destructive

analysis is required.

References

[1] M.A. Eleffendi, et al., Quantication

of cracked area in thermal path of high-

power multi-chip modules using transient

thermal impedance measurement,

Microelectronics Reliability (2015), http://

dx.doi.org/10.1016/j.microrel.2016.01.002

Figure 11.Percentage of attached area local to the IGBT devices and the cumulative

structure function of each individual IGBT device after 17,700 cycles.

Figure 12.The junction-to-ambient thermal resistance Rthja of the individual IGBTs

after 17,700 cycles as a function of the attached area below each IGBT.

Figure 13.K-value as a function of the square of the fractional attached area of the individual IGBTs.

Power Electronics


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This article originally appeared inEngineering Edge Vol. 5 Iss. 1

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www.mentor.com/mechanical/products/engineering-edge

2016 Mentor Graphics Corporation,

all rights reserved. This document contains

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