CPE 335 Computer Organization MIPS Arithmetic – Part I ......Review: 2’s Complement Binary...

CPE 335Computer Organizationg

MIPS Arithmetic – Part I

Content from Chapter 3and Appendix B

Dr. Iyad Jafar

Adatped from Dr. Gheith Abandah Slides

http://www.abandah.com/gheith/Courses/CPE335 S08/index.html

CPE 232 MIPS Arithmetic 1

http://www.abandah.com/gheith/Courses/CPE335_S08/index.html

MIPS Number Representations

Computer programs calculate both positive a negative numbers.

One approach is to use the sign and magnitudeOne approach is to use the sign and magnitude representation.

Use separate bit for the sign

Shortcomings:

Where to put the sign ? p g

Positive and negative zeros !

Need complex hardware to perform arithmetic p p

Alternative: use the complement notation; specifically


Alternative: use the complement notation; specifically the two’s complement !

32 bit i d b (2’ l t)MIPS Number Representations

32-bit signed numbers (2’s complement):0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten

maxinttwo ten

...

0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten000 0000 0000 0000 0000 0000 0000 0000 2 83 6 81000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten

1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten...

1111 1111 1111 1111 1111 1111 1111 1110 21111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten

minintMSB

LSB

If we use N bits to represent a signed number using two’s complement, then

Th i b i 2N 1 1The maximum number is 2N-1 – 1

The minimum number is -2N-1


Review: 2’s Complement Binary Representation2’ bi d i l2’sc binary decimal

1000 -81001 -7-(23 - 1) =

-23 =

Negate1010 -61011 -51100 4

( )Negate

1100 -41101 -31110 -2

1011

1111 -10000 00001 11010

and add a 1

0001 10010 20011 3

complement all the bits

0100 40101 50110 6


0110 60111 723 - 1 =

MIPS Number RepresentationsConverting signed numbers to decimal

• (1111 1110 ) =(1111 1110 )2 =

-1*2^7 + 1*2^6 + 1*2^5 + 1*2^4 + 1*2^3 + 2^2 + 1*2^1 0*2^0 2+ 0*2^0 = -2

Converting <32-bit values into 32-bit valuesSign Extension: copy the most significant bit (the sign bit) into g py g ( g )the “empty” bits

0010 -> 0000 00101010 -> 1111 10101010 > 1111 1010

Zero Extension: place zeros in the extended bits.


0010 -> 0000 0010

1010 -> 0000 1010

MIPS Number Representation How to negate a number ?

There is no special instruction e e s o spec a st uct o

Suppose we have x = - x

b $ 0 $ $ 0sub $s0 , $zero , $s0

This is in contrast to complementing a number !

x = ~x

Bitwise complement of xBitwise complement of x

There is no single instruction

Recall the XOR operation x ⊕ 1 = x’

addi $t0, $zero, -1


, ,

xor $s0, $s0, $t0

MIPS Instruction Support for Signed numbers add vs addu, sub vs subu, and addi vs addiu

Addition/subtraction is performed in the same dd t o /subt act o s pe o ed t e sa emanner

Is overflow exception generated ? p g

lb vs lbu

lb i t d th dditi l bitlb sign extend the additional bits

lbu zero extend the additional bits

slt vs sltu and slti vs sltiu

slt and slti perform signed comparison with aslt and slti perform signed comparison with a constant

sltu and sltiu perform unsigned comparison with a


sltu and sltiu perform unsigned comparison with a constant

ExampleSuppose that

$s0 = 1111 1111 1111 1111 1111 1111 1111 1111 $s0

$s1 = 0000 0000 0000 0000 0000 0000 0000 0001

th h t i th l t d i $t0 i th f ll ithen what is the value stored in $t0 in the following cases :

slt $t0, $s1, $s0

• Signed comparison

• $t0 = 0 since $s1 = 1 and $s0 = -1• $t0 = 0 since $s1 = 1 and $s0 = -1

sltu $t0, $s1, $s0

• Unsigned comparison

• $t0 = 1 since $s1 = 1 and $s0 = 2^32 -1


Binary Addition

Binary addition is simple !

0 + 0 = 0 and 0 carry

0 + 1 = 1 and 0 carry0 1 1 and 0 carry

1 + 0 = 1 and 0 carry

1 + 1 = 0 and 1 carry

Add corresponding bits and propagate the carry, if any, t th t bit


to the next bit.

Review: A Full Addercarry_in A B carry_in carry_out S

0 0 0 0 00 0 1 0 1

1-bit Full Adder

A

BS

0 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 1dde

carry_out

1 0 0 0 11 0 1 1 01 1 0 1 0

S = A ⊕ B ⊕ carry in

1 1 1 1 1

S = A ⊕ B ⊕ carry_in

carry out = A&B | A&carry in | B&carry incarry_out A&B | A&carry_in | B&carry_in

How can we use it to build a 32-bit adder?


How can we modify it easily to build an adder/subtractor?

A 32-bit Ripple Carry Adder/Subtractor

Remember 2’s complement is just 1-bit

FA S0

c0=carry_in

A0

add/sub

jcomplement all the bits

FA S0

c1

1-bit S

A1

B0

control

dd 1 i th l t i ifi t

FA S1

c2

1-bitA2

B1B0

(0=add,1=sub) B0 if control = 0, !B0 if control = 1

add a 1 in the least significant bit

Subtraction is equivalent to

1 bit FA S2

c3

A2

B2

Subtraction is equivalent to adding the negative of the number

1 bit

c31

. . .

A

A 0111 → 0111 B - 0110 → + c32=carry out

1-bit FA S31

A31

B311001


B 0110 → + 32 y_

0001

10011

1 0001

Overflow DetectionO fl th lt i t l t t i 32 bitOverflow: the result is too large to represent in 32 bits

Overflow occurs whenadding two positives yields a negative or, adding two negatives gives a positiveor, subtract a negative from a positive gives a negativeor, subtract a positive from a negative gives a positive

On your own: Prove that you can detect overflow by:Carry into MSB XOR Carry out of MSB, ex for 4 bit signed

bnumbers

1 110 1 01 110

0 1 1 1

0 0 1 1+

7

3

1

1 1 0 0

1 0 1 1+

–4

– 5

0


1 1 1001 0 – 6 71

Improving Addition PerformanceThe ripple-carry adder is slow

We have to wait until the carry is propagated to the finalWe have to wait until the carry is propagated to the final position in order to read out the addition/subtraction result.

Carry generation is associated with two levels of gates at each bit position (Coi = AiBi + AiCini + BiCini ).

Total delay = gate delay x 2 x number of bits

E l 16 bit dd d l i 32 d l itExample: 16 bit adder delay is 32 delay units

++++


Carry-Lookahead AdderNeed fast way to find the carry

Design a separate unit that computes carries for differentDesign a separate unit that computes carries for different bits in parallel !


Carry-Lookahead AdderIn a 4 bit adder, the equations of the carries are

c1 = (b0 . c0) + (a0 . c0) + (a0 . b0) c2 = (b1 . c1) + (a1 . c1) + (a1 . b1) c3 = (b2 . c2) + (a2 . c2) + (a2 . b2)c4 = (b3 . c3) + (a3 . c3) + (a3 . b3)

By substitution c2 = (a1 . a0 . b0) + (a1 . a0 . c0) + (a1 . b0 . c0) + (b1 . a0 . b0)

+ (b1 . a0 . c0 ) + (b1 . b0 . c0) + (a1.b1)3 (b2 1 0 b0) + (b2 1 0 0) + (b2 1 b0 0) +c3 = (b2 . a1 . a0 . b0) + (b2 . a1 . a0 . c0) + (b2 . a1 . b0 . c0) + (b2 . b1 . a0 . b0) + (b2 . b1 . a0 . c0 ) + (b2 . b1 . b0 . c0) + (b2 . a1 . b1) + (a2 . a1 . a0 . b0) + (a2 . a1 . a0 . c0) + (a2 . a1 . b0 . c0) + (a2 b1 a0 b0) + (a2 b1 a0 c0 ) + (a2 b1 b0 c0) +c0) + (a2 . b1 . a0 . b0) + (a2 . b1 . a0 . c0 ) + (a2 . b1 . b0 . c0) + (a2 . a1 . b1) + (a2.b2)

c4 = ……


Imagine the equation if the adder is 32 bits ?? .

Carry-Lookahead AdderWe can reduce the logic cost by simple simplification

ci+1 = (bi . ci) + (ai . ci) + (ai . bi) = (ai . bi) + (ai + bi) . ci= gi + pi . ci

i tgi : carry generate pi : carry propagate

C fCarry equations for 4 bit adderc1 = g0 + p0 . c0 c2 = g1 + (p1 g0) + (p1 p0 c0)c2 = g1 + (p1 . g0) + (p1 . p0 . c0)c3 = g2 + (p2 . g1) + (p2 . p1 . g0) + (p2 . p1 . p0 . c0)c4 = g3 + (p3 g2) + (p3 p2 g1) + (p3 p2 p1 g0) +c4 = g3 + (p3 . g2) + (p3 . p2 . g1) + (p3 . p2 . p1 . g0) +

(p3 . p2 . p1 . p0 . c0)

Delay to generate c4 is 3 gate delay


Delay to generate c4 is 3 gate delay

Still cost is high for larger adders ! ! !

Carry-Lookahead Adder- Second level of Abstraction

Assume 16 bit adder that consists of 4 single 4-bit adders with carry-lookahead implementation

c0c4c4

c1c2c3 b0a0p0g0

c1c2c3 b0a0

++++

4-bit carry lookahead adders0


4-bit carry lookahead adder

Carry-Lookahead Adder- Second level of AbstractionNeed to generate the carry propagate and generate signals at higher level

Think of each 4 bit adder block as a singleThink of each 4-bit adder block as a single

unit that can either generate or propagate

a carry.

Super propagate signals0 3 2 1 0P0 = p3 p2 p1 p0

P1 = p7 p6 p5 p4P2 = p11 p10 p9 p8P3 = p15 p14 p13 p12

Super generate signalsG0 = g3+(p3 g2)+(p3 p2 g1)+(p3 p2 p1 g0)G1 = g7+(p7 g6)+(p7 p6 g5)+(p7 p6 p5 g4)G2 = g11+(p11 g10)+(p11 p10 g9)+(p11 p10 p9 g8)


G3 = g15+(p15 g14)+(p15 p14 g13)+(p15 p14 p13 g12)

Carry-Lookahead Adder- Second level of Abstraction

Carry signal at higher levels are C1 = G0 + (P0 c0)C2 G1 + (P1 G0) + (P1 P0 0)C2 = G1 + (P1 G0) + (P1 P0 c0)C3 = G2 + (P2 G1) + (P2 P1 G0) + (P2 P1 P0 c0)C4 = G3 + (P3 G2) + (P3 P2 G1) + (P3 P2 P1 G0)

+ (P3 P2 P1 P0 c0)

Each supper carry signal is two level implementation in terms of Pi and Giimplementation in terms of Pi and Gi

Pi is one level of gates while Gi is two and expressed in terms of pi and gip p g

pi and gi are one level of gates

Total delay is 2 + 2 + 1 = 5Total delay is 2 + 2 + 1 = 5

16-bit CLA is 5 times faster than the 16-bit ripple carry adder


y

MIPS Arithmetic Logic Unit (ALU)

Need to support the logic operationsNeed to support arithmetic operationsNeed to support the set-on-less-than instructionNeed to support test for equalityImmediates are sign or zero extended outside the ALUImmediates are sign or zero extended outside the ALU with wiring (i.e., no logic needed)


MIPS Arithmetic Logic Unit (ALU)fMust support the Arithmetic/Logic

operations of the ISA

zero ovf

11

add, addi, addiu, addu

sub, subu, neg

l l di di

32

32result

A

ALUmult, multu, div, divu

sqrt

d di i i32

32

B4

and, andi, nor, or, ori, xor, xori

beq, bne, slt, slti, sltiu, sltum (operation)

With special handling forsign extend – addi, addiu andi, ori, xori, slti, sltiusltiu

zero extend – lbu, addiu, sltiu

no overflow detected – addu, addiu, subu, multu,


no overflow detected addu, addiu, subu, multu, divu, sltiu, sltu

MIPS Arithmetic Logic Unit (ALU)Start with 1-bit ALU Can easily implement the logic instruction AND and ORsince they map directly to hardware. Perform all possible operations in parallel then use a multiplexer to select the result based on the instruction type.The control signal Operation is issued by the control unit


MIPS Arithmetic Logic Unit (ALU)For the ADD instruction, use a full adder. The CarryIninput will be used later on to expand the 1-bit ALU to n-BitBit. Expand the multiplexer inputs and select lines to accommodate for the add instructionaccommodate for the add instruction.


MIPS Arithmetic Logic Unit (ALU)For the subtract instruction, we use 2’s complement subtraction.We need to complement B and add 1. Define Binvert to select between B and B’ and set CarryIn to 1.


MIPS Arithmetic Logic Unit (ALU)Combine Binvert and CarryIn in one signal Bnegatesince they have the same value all the time.


MIPS Arithmetic Logic Unit (ALU)Supporting the NOR operation requires no separate gate.Use Demorgan’s theorem and the AND gate and define th i l Ai tthe signal Ainvert(A+B)’ = A’.B’


MIPS Arithmetic Logic Unit (ALU)Constructing 32-bit ALUReplicate the 1-bit ALU and connect the CarryIn signals All cells receive thesame control signals


MIPS Arithmetic Logic Unit (ALU)Supporting the SLT instruction

Expand the multiplexer for one more input.Subtract the two registers and feed the sign bit (the result of bit 31) back to the least significant bit. The slt input of the multiplexer is connected to 0 for remainingThe slt input of the multiplexer is connected to 0 for remaining bits .

CPE 232 MIPS Arithmetic 28LSB MSB

MIPS Arithmetic Logic Unit (ALU)32-bit ALU with SLT support.


MIPS Arithmetic Logic Unit (ALU)Supporting conditional branch instructions

Need to generate a signal that indicates whether the result is zero or notzero or not. Simply OR the result bits and take the complement. This signal will be used to make the selection between theThis signal will be used to make the selection between the branch address and the PC.

Example on using the Zero signal to


Example on using the Zero signal to select the address for BEQ instruction

MIPS Arithmetic Logic Unit (ALU)Final ALU with overflow detection


MIPS Arithmetic Logic Unit (ALU)Control signals values and corresponding operations

Ai t B t O ti I t tiAinvert Bnegate Operation Instruction0 0 00 AND0 0 01 OR0 0 01 OR0 0 10 ADD0 1 10 SUB


0 1 11 SLT1 1 00 NOR

CPE 335 Computer Organization MIPS Arithmetic – Part I ......Review: 2’s Complement Binary...

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