Course Outline - Weber State Universityfaculty.weber.edu/snaik/EE3110/01Chapter 5-2.pdf ·...
Transcript of Course Outline - Weber State Universityfaculty.weber.edu/snaik/EE3110/01Chapter 5-2.pdf ·...
EE 3110 Microelectronics I Suketu Naik
1Course Outline
1. Chapter 1: Signals and Amplifiers
2. Chapter 3: Semiconductors
3. Chapter 4: Diodes
4. Chapter 5: MOS Field Effect Transistors (MOSFET)
5. Chapter 6: Bipolar Junction Transistors (BJT)
6. Chapter 2 (optional): Operational Amplifiers
EE 3110 Microelectronics I Suketu Naik
2
Chapter 5:
MOSFETs
Part II
EE 3110 Microelectronics I Suketu Naik
3NMOS at DC
Example 5.3 (modified): NMOS Transistor
Design the circuit of Figure 5.21, that is, determine the values of RD
and RS
ID = 1mA and VD = +0.5V
Vtn = 0.4V, mnCox = 100mA/V2
L = 1mm, and W = 32mm
Neglect the channel-length modulation effect (i. e. assume that l = 0).
EE 3110 Microelectronics I Suketu Naik
4NMOS at DC
Exercises D5.9
Determine the value of R such that
VD = 0.8V
Vtn = 0.5V, mnCox = 0.4 mA/V2
W=0.72 mm, and L = 0.18 mm
Exercises D5.10
Combine the circuit in D5.9 with transistor Q2 and find R2 such that Q2 is at the edge of saturation.
EE 3110 Microelectronics I Suketu Naik
5Example 5.8: CMOS Transistors (Inverter)
NMOS and PMOS transistors in the
circuit of Figure 5.26(a) are matched,
with k’n(Wn/Ln) = k’p(Wp/Lp) = 1mA/V2
and Vtn = -Vtp = 1V. Assume l = 0 for
both devices.
Find the drain currents iDN and iDP
for vI = 0V, +2.5V, -2.5V.
Find voltage vO for
vI = 0V, +2.5V, -2.5V.
EE 3110 Microelectronics I Suketu Naik
65.4.1. Obtaining a Voltage Amplifier
In section 1.5, we learned that voltage
controlled current source (VCCS) can serve
as transconductance amplifier.
Q: How can we translate current output to
voltage?
A: Measure voltage drop across load
resistor.
Figure 5.27: (a) simple
MOSFET amplifier with input
vGS and output vDS
Transconductance
Amplifier
functionof input
supply
(eq5. ) 30Gout vv
DS DD D Dv v i R
EE 3110 Microelectronics I Suketu Naik
75.4.2. Voltage Transfer Characteristic
Voltage transfer characteristics (VTC) –
plot of output voltage vs. input voltage
Three regions exist in VTC
vGS < Vt OFF
vOV = vGS – Vt < 0
ID = 0, vout = vDD
Vt < vGS < vDS + Vt SATURATION
vOV = vGS – Vt > 0
ID = ½ kn(vGS – Vt)2
vDS >> vOV
vout = VDD – IDRD
vDS + Vt < vGS < VDD TRIODE
vOV = vGS – Vt > 0
ID = kn(vGS – Vt – vDS)vDS
vDS < vOV
vout = VDD – IDRD
Figure 5.27: (b) the voltage
transfer characteristic (VTC) of
the amplifier
EE 3110 Microelectronics I Suketu Naik
8
Q: What observations can be drawn?
A: Cutoff FET represents
transistor off (vout=VDD) Cutoff
AMP represents vout = 0
A: As vGS increases,
vDS (effectively) decreases
iD increases
vout decreases nonlinearly
gain decreases
A: Once vDS > VDD, all power is
dissipated by resistor RD
5.4.2. Voltage Transfer Characteristic
Figure 5.27: (b) the voltage transfer
characteristic (VTC) of the amplifier
cutoff FET cutoff AMP
EE 3110 Microelectronics I Suketu Naik
95.4.2. Voltage Transfer Characteristic
Q: How do we define vDS in terms of vGS for
saturation?
Note: vGS and vDS are instantaneous voltages
(DC+AC)
Figure 5.27: (b) the voltage transfer
characteristic (VTC) of the amplifier
from previous slide
this is equation is simply ohm's law / KVL
2
GS
(eq5.32)
(eq5.33)
1
2
2 1 1V
D
DS DD n GS t D
n D DD
tBn D
i
v V k v V R
k R VV
k R
Q: How do we define point B –
boundary between saturation and
triode regions?
EE 3110 Microelectronics I Suketu Naik
105.4.3. Biasing the MOSFET to Obtain Linear Amplification
Q: How can we linearize VTC?
A: Biasing
A: DC voltage VGS is
selected to obtain operation
at point Q on segment AB
Q: How do we choose VGS?
A: Next slide
Figure 5.28: biasing the MOSFET
amplifier at point Q located on segment
AB of VTC
2
this equation is simply ohm's law
(eq5.34) 2
1
source D DV I R
DS DD n GS t DV V k V V R
EE 3110 Microelectronics I Suketu Naik
11
Bias point / DC operating pt.
(Q) – point of linearization for
MOSFET
Q: How will Q help us?
A: Because VTC is linear
near Q, we may perform
linear amplification of
signal << Q
Figure 5.28: biasing the MOSFET
amplifier at point Q located on segment
AB of VTC
2
this equation is simply ohm's law
(eq5.34) 2
1
source D DV I R
DS DD n GS t DV V k V V R
5.4.3. Biasing the MOSFET to Obtain Linear Amplification
EE 3110 Microelectronics I Suketu Naik
12
Linear amplification
around Q in
saturation region
5.4.3. Biasing the MOSFET to Obtain Linear Amplification
EE 3110 Microelectronics I Suketu Naik
13
Q: How is linear gain achieved?
step #1: Bias MOSFET with
dc voltage VGS as defined by
(5.34)
step #2: Superimpose
amplifier input (vgs) upon VGS
step #3: Resultant vds should
be linearly proportional to
small-signal component vgs
GS GS gs
ds gs
t V t
t t
v v
v v
5.4.3. Biasing the MOSFET to Obtain Linear Amplification
2
this equation is simply ohm's law
(eq5.34) 2
1
source D DV I R
DS DD n GS t DV V k V V R
EE 3110 Microelectronics I Suketu Naik
14Q: How is linear gain achieved?
As long as vgs(t) is small, its effect
on vds(t) will be linear: facilitating
linear amplification.
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15Input and Output Voltages
EE 3110 Microelectronics I Suketu Naik
16
means that is small
replace with (5.32)
simplify
212
(eq
(eq5.35)
(eq5.36)
(eq5
5.35)
.
GS
vgs
DS
GS
GS GS
DSv
GS v V
DD n GS t D
GSv V
v n GS t
v
D
v
dvA
dv
d V k v V R
dv
A k V V R
A
action:
action:
replacewith
7 3 )
OV
v n V
V
O DA k V R
action:
Q: How is linear gain achieved?
EE 3110 Microelectronics I Suketu Naik
175.4.4. Small-Signal Voltage Gain
Q: What observations can
be made about voltage gain?
A: Gain is negative (180
deg phase shift)
A: Gain is proportional to:
load resistance (RD)
transistor conductance
parameter (kn)
overdrive voltage (vOV)
means that is small
replace with (5.32)
simplif
1
y
2
2
(eq5.35)
(eq5.35)
(eq5.36)
(eq5.37)
GS
DS
vgs
GS
GS GS
DSv
GS v V
DD n GS t D
GSv V
v n GS t D
v
v
dvA
dv
d V k v V R
dv
A k V V R
A
action:
action:
replacewith
OV
n D
V
v OVA k V R
action:
EE 3110 Microelectronics I Suketu Naik
18
Equation (5.38) is another
version of (5.37) which
incorporates (5.17).
It demonstrates that gain
is ratio of:
voltage drop across RD
half of over voltage
212
inc(5.1
orpo7)
rate
(eq5.37)
(eq5.3/2
8)
D n OV
v n OV D
D Dv
v
V
i
O
k
A k V R
I RA
V
action:
5.4.4. Small-Signal Voltage Gain
EE 3110 Microelectronics I Suketu Naik
19
Q: How does (5.38) relate to physical devices?
A: For modern CMOS technology, vOV is usually no
less than 0.2V.
A: This means that max achievable gain is
approximately 10VDD.
0.1
10/2
DD
D D
v D
V
V
D
OV
I RA V
V
maxmax
For example, 0.13 μm CMOS technology with VDD = 1.3 V
yields maximum gain of 13 V/V.
5.4.4. Small-Signal Voltage Gain
EE 3110 Microelectronics I Suketu Naik
20Example 5.9: MOSFET Amplifier
Problem Statement: Consider the amplifier circuit shown in Figure
5.29(a). The transistor is specified to have Vt = 0.4V, k’n = 0.4mA/V2, W/L
= 10, and l = 0. Also, let VDD = 1.8V, RD = 17.5 kΩ, and VGS = 0.6V.
Q(a): For vgs = 0 (and hence vds = 0), find VOV, ID, VDS, and Av.
Q(b): What is the maximum symmetrical signal swing allowed at the drain?
Hence, find the maximum allowable amplitude of a sinusoidal vgs.
EE 3110 Microelectronics I Suketu Naik
215.4.5. Determining the VTC via Graphical Analysis
Graphical method for
determining VTC is shown in
Figure 5.31.
Draw load line based on eq.5.36
Based on observation that, for
each value of vGS, circuit will
operate at intersection of iD and
vDS.
Note: that slope of load line
= -1/RD
(eq5.39) DSDDD
D D
vVi
R R
EE 3110 Microelectronics I Suketu Naik
22
Point A – where vGS = Vt
Point Q – where MOSFET
may be biased for amplifier
operation
vGS = VGS, vDS = VDS
Point B – where MOSFET
leaves saturation / enters
triode
Point C – where MOSFET is
deep in triode region and
vGS = VDD
Points A (open) and C (closed) are
suitable for switch applications
Point Q is suitable for amplifier applications
5.4.5. Determining the VTC via Graphical Analysis
EE 3110 Microelectronics I Suketu Naik
23MOSFET as a Switch
Open
vGS = Vt
Input =‘0’
(very small)
vDS = VDD
Output =‘1’
(VDD=2.5 V or 5 V)
Closed
vGS = VDD Input =‘1’
(VDD=2.5 V or 5 V)
vDS = VDS|cOutput = ‘0’
(very small VDS)
EE 3110 Microelectronics I Suketu Naik
245.4.6. Locating the Bias Point Q
Bias point (Q) – is determined by value of vGS and load resistance RD.
Trade-off between
Required gain
Linear range: allowable signal swing at output.
linear range is large
gain is low
gain is high
linear range is small
EE 3110 Microelectronics I Suketu Naik
255.4.6. Locating the Bias Point Q
To define load resistance RD, one
should refer to the iD - vDS plane.
Two examples of RD are shown
Q2: too close to triode
Not enough legroom
(negative peaks get cut-
off)
Q1: too close to VDD
Not enough headroom
(positive peaks get cut-off)
Ideally, we want to be somewhere
in the middle
The objective is to stop vDS from clipping or entering triode region
EE 3110 Microelectronics I Suketu Naik
265.5. Small-Signal Operation and Models
Figure 5.34: Conceptual circuit utilized to study the
operation of the MOSFET as a small-signal amplifier.
DC bias voltages
VGS and VDS
Output
voltage
Input voltage
to be amplified
EE 3110 Microelectronics I Suketu Naik
275.5.1. The DC Bias Point
Q: How is dc bias current ID defined?
only applies in saturation where
2 2
(eq5.40)
(eq5.41)
1
1
2
2
DS OV
D n GS t n OV
DS DD D
V
D
V
I k V V k V
V V R I
EE 3110 Microelectronics I Suketu Naik
285.5.2. The Signal Current in the Drain Terminal
Q: What is effect of vgs on iD?
Step #1: Define vGS as in
(5.42).
Step #2: Define iD, separate
terms as function of VGS and
vgs
state (5.1
2
7
2
2
)
1
2
(eq5.43)
(eq5.42)
(eq5
1
2 2
.17)
GS
OV
GS gs t
v
GS GS gs
D n GS gs t
GS t
v
V
n
GS t
D
v V
gs gs
v V v
i k V v V
V Vk
V V v vi
action:
expand the squaredterm via and
simp f
2
2
li y
(eq5.
1
21
43 )
2
GS t gs
D n GS t
n GS t gs n g
V V v
s
i k V V
k V V v k v
action:
action:
EE 3110 Microelectronics I Suketu Naik
29Q: What is effect of vgs on iD?
Step #3: Classify terms.
DC bias current (ID).
Linear gain – is desirable.
Nonlinear distortion – is undesirable
current gaindistortionter
2
merm
2
t
(eq5.43) 1 1
2 2D
D n GS t n GS t gs n gs
I
i k V V k V V v k v
linearnonlineardc bias
Note that to minimize
nonlinear distortion, vgs
should be kept small.
½knvgs2 << kn(VGS-Vt)vgs
vgs << 2(VGS-Vt)
vgs << 2vOV
EE 3110 Microelectronics I Suketu Naik
30
If vgs << 2vOV , neglect distortion
2 2
current gain
distortiontermterm
1 1
2 2(eq5.43)
(eq5.47)
D
D n GS t n GS t gs n gs
gs
m n GS t
I
d
i k V V k V V v k v
vg k V V
i
linearnonlineardc bias
MOSFET transconductance
Q: What is effect of vgs on iD?
𝑔𝑚 =𝑖𝑑𝑣𝑔𝑠
= 𝑘𝑛(𝑉𝐺𝑆−𝑉𝑡𝑛)
EE 3110 Microelectronics I Suketu Naik
31MOSFET Transconductance gm
eq (5.49)
EE 3110 Microelectronics I Suketu Naik
325.5.3. The Voltage Gain
Q: How is voltage gain (Av) defined?
Step #1: Define vDS for circuit of KVL
dc comp
apply small-signalcondition
regroup terms sim
onent
plify
ds
DS
DS DD D D DD D D d
DD D D D d DS DDS d
v
V
v V R i V R I i
V R I R i V Rv i
action:
action: action:
Figure 5.34
EE 3110 Microelectronics I Suketu Naik
33
Step #2: Isolate vds component of vDS
Step #3: Solve for gain (Av)
isolate
insert (5.47)
(
solve for gai
)
n
5.47
(eq5.50
(eq5.50)
(eq5.51)
)
ds
ds D d
D m gs
dsv m D
s
g
v
s
d
v R i
R g v
vA g R
v
v
action:
action:
action:
5.5.3. The Voltage Gain
𝑔𝑚 =𝑖𝑑𝑣𝑔𝑠
= 𝑘𝑛(𝑉𝐺𝑆−𝑉𝑡𝑛)
Figure 5.34
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345.5.3. The Voltage Gain
Output signal is shifted from
input by 180O.
Input signal vgs << 2(VGS – Vt).
Operation should remain in
MOSFET saturation region
vDS > vGS – Vt (negative
peak)
vDS < VDD (positive peak)
Figure 5.36: Total instantaneous
voltages vGS and vDS for the circuit
in Figure 5.34.
EE 3110 Microelectronics I Suketu Naik
355.5.5. Small-Signal Equivalent Models
From the perspective of the signal
(vgs), FET behaves as voltage
controlled current source (VCCS).
Accepts vgs between gate and
source
Provides current (iD) at drain
Input resistance should be as
high as possible
gate terminal draws iG = 0
Output resistance is high
Figure 5.37: Small-signal models for the
MOSFET: (a) neglecting the dependence of iD
on vDS in saturation (the channel-length
modulation effect) and (b) including the effect
of channel length modulation
EE 3110 Microelectronics I Suketu Naik
36
Model (b) is more accurate
than model (a)
ro = VA / ID
Small signal parameters (gm, ro)
both depend on dc bias point
If channel-length modulation
is considered, (5.51) becomes
(5.54).
less accurate, b/c does not considerchannel length modulation
more accurate, b/c does considerchannel length modulation
(eq5.51)
(eq5.54 ||)
dsv m D
gs
dsv m D o
gs
vA g R
v
vA g R r
v
5.5.5. Small-Signal Equivalent Models
EE 3110 Microelectronics I Suketu Naik
375.5.6. The Transconductance gm
Observations from (5.47)
gm is proportional to mn,
Cox, ratio W/L, dc
component VOV
MOSFET with short /
wide channel provides
maximum gain
Gain may be increased via
VGS, but not without
reducing allowable swing
of vgs.
make somesubstitutions
simplify
(eq5.47)
(eq5.47)
(eq5 )
.55
n
m
gs
m n GS t
d
n GS t
m n V
k
O
vg k V V
i
Wk V V
L
Wk V
L
g
g
action:
action:
𝑔𝑚 =𝑖𝑑𝑣𝑔𝑠
= 𝑘𝑛(𝑉𝐺𝑆−𝑉𝑡𝑛)
EE 3110 Microelectronics I Suketu Naik
38
Observations from (5.47)
gm is proportional to square root
of dc bias current (ID)
For given ID, gm is proportional
to (W/L)1/2
Dependent on 3 design parameters:
W/L, VOV , ID
solve(5.40) for
substitute for as defined b e
2
a ov
(eq5.40)
(eq5.
(eq5.5
1
(e
q
6
2
55)
(eq5
5.40)2
/
2
5
/
.
)
OV
OV
D n OV
D
OV
n
m n OV
Dn
n
m
V
V
WI k V
L
IV
k W L
Wg k V
L
IWk
k W Lg
L
action:
action:
simplify
6) 2 /m n Dg k W L I
action:
5.5.6. The Transconductance gm
EE 3110 Microelectronics I Suketu Naik
395.5.6: The Transconductance gm
Figure 5.38 illustrates the
relationship defined in (5.57).
Figure 5.38: The slope of the tangent at
the bias point Q intersects the vOV axis
at 1/2VOV. Thus gm = ID/(1/2VOV).
replace
simpl
2
ify
2
2 2
(eq5.55)
(eq
(eq5
5.5
7)
.56)
nW
k
m n OV
DOV
GS t
D Dm
GS t OV
L
m
Wg k V
L
IV
V V
I Ig
V V
g
V
action:
action:
EE 3110 Microelectronics I Suketu Naik
40Example 5.10: MOSFET Amplifier
Figure 5.39(a): MOSFET amplifier with a drain-to-gate resistance RG for biasing
purposes. The input signal vI is coupled to the gate via a large capacitor, and the
output signal at the drain is coupled to the load resistance RL via another large
capacitor.
Vt = 1.5 V, k’n(W/L) = 0.25 mA/V2, and VA = 50 V.
(a) Find small-signal voltage gain,
(b) Find input resistance, and the largest allowable input signal.
DC Analysis
AC (small signal)
Analysis
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415.5.7. The T Equivalent-Circuit Model
Figure 5.40:
Development of the T
equivalent-circuit
model for the MOSFET.
For simplicity, ro has
been omitted; however,
it may be added
between D and S in the
T model of (d).
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425.5.7. The T Equivalent-Circuit Model
Include ro (channel-length modulation effect)
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43Small Signal Models of MOSFET
Hybrid-π model T model